1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0-only */ 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * include/linux/mfd/wl1273-core.h 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun * Some definitions for the wl1273 radio receiver/transmitter chip. 6*4882a593Smuzhiyun * 7*4882a593Smuzhiyun * Copyright (C) 2010 Nokia Corporation 8*4882a593Smuzhiyun * Author: Matti J. Aaltonen <matti.j.aaltonen@nokia.com> 9*4882a593Smuzhiyun */ 10*4882a593Smuzhiyun 11*4882a593Smuzhiyun #ifndef WL1273_CORE_H 12*4882a593Smuzhiyun #define WL1273_CORE_H 13*4882a593Smuzhiyun 14*4882a593Smuzhiyun #include <linux/i2c.h> 15*4882a593Smuzhiyun #include <linux/mfd/core.h> 16*4882a593Smuzhiyun 17*4882a593Smuzhiyun #define WL1273_FM_DRIVER_NAME "wl1273-fm" 18*4882a593Smuzhiyun #define RX71_FM_I2C_ADDR 0x22 19*4882a593Smuzhiyun 20*4882a593Smuzhiyun #define WL1273_STEREO_GET 0 21*4882a593Smuzhiyun #define WL1273_RSSI_LVL_GET 1 22*4882a593Smuzhiyun #define WL1273_IF_COUNT_GET 2 23*4882a593Smuzhiyun #define WL1273_FLAG_GET 3 24*4882a593Smuzhiyun #define WL1273_RDS_SYNC_GET 4 25*4882a593Smuzhiyun #define WL1273_RDS_DATA_GET 5 26*4882a593Smuzhiyun #define WL1273_FREQ_SET 10 27*4882a593Smuzhiyun #define WL1273_AF_FREQ_SET 11 28*4882a593Smuzhiyun #define WL1273_MOST_MODE_SET 12 29*4882a593Smuzhiyun #define WL1273_MOST_BLEND_SET 13 30*4882a593Smuzhiyun #define WL1273_DEMPH_MODE_SET 14 31*4882a593Smuzhiyun #define WL1273_SEARCH_LVL_SET 15 32*4882a593Smuzhiyun #define WL1273_BAND_SET 16 33*4882a593Smuzhiyun #define WL1273_MUTE_STATUS_SET 17 34*4882a593Smuzhiyun #define WL1273_RDS_PAUSE_LVL_SET 18 35*4882a593Smuzhiyun #define WL1273_RDS_PAUSE_DUR_SET 19 36*4882a593Smuzhiyun #define WL1273_RDS_MEM_SET 20 37*4882a593Smuzhiyun #define WL1273_RDS_BLK_B_SET 21 38*4882a593Smuzhiyun #define WL1273_RDS_MSK_B_SET 22 39*4882a593Smuzhiyun #define WL1273_RDS_PI_MASK_SET 23 40*4882a593Smuzhiyun #define WL1273_RDS_PI_SET 24 41*4882a593Smuzhiyun #define WL1273_RDS_SYSTEM_SET 25 42*4882a593Smuzhiyun #define WL1273_INT_MASK_SET 26 43*4882a593Smuzhiyun #define WL1273_SEARCH_DIR_SET 27 44*4882a593Smuzhiyun #define WL1273_VOLUME_SET 28 45*4882a593Smuzhiyun #define WL1273_AUDIO_ENABLE 29 46*4882a593Smuzhiyun #define WL1273_PCM_MODE_SET 30 47*4882a593Smuzhiyun #define WL1273_I2S_MODE_CONFIG_SET 31 48*4882a593Smuzhiyun #define WL1273_POWER_SET 32 49*4882a593Smuzhiyun #define WL1273_INTX_CONFIG_SET 33 50*4882a593Smuzhiyun #define WL1273_PULL_EN_SET 34 51*4882a593Smuzhiyun #define WL1273_HILO_SET 35 52*4882a593Smuzhiyun #define WL1273_SWITCH2FREF 36 53*4882a593Smuzhiyun #define WL1273_FREQ_DRIFT_REPORT 37 54*4882a593Smuzhiyun 55*4882a593Smuzhiyun #define WL1273_PCE_GET 40 56*4882a593Smuzhiyun #define WL1273_FIRM_VER_GET 41 57*4882a593Smuzhiyun #define WL1273_ASIC_VER_GET 42 58*4882a593Smuzhiyun #define WL1273_ASIC_ID_GET 43 59*4882a593Smuzhiyun #define WL1273_MAN_ID_GET 44 60*4882a593Smuzhiyun #define WL1273_TUNER_MODE_SET 45 61*4882a593Smuzhiyun #define WL1273_STOP_SEARCH 46 62*4882a593Smuzhiyun #define WL1273_RDS_CNTRL_SET 47 63*4882a593Smuzhiyun 64*4882a593Smuzhiyun #define WL1273_WRITE_HARDWARE_REG 100 65*4882a593Smuzhiyun #define WL1273_CODE_DOWNLOAD 101 66*4882a593Smuzhiyun #define WL1273_RESET 102 67*4882a593Smuzhiyun 68*4882a593Smuzhiyun #define WL1273_FM_POWER_MODE 254 69*4882a593Smuzhiyun #define WL1273_FM_INTERRUPT 255 70*4882a593Smuzhiyun 71*4882a593Smuzhiyun /* Transmitter API */ 72*4882a593Smuzhiyun 73*4882a593Smuzhiyun #define WL1273_CHANL_SET 55 74*4882a593Smuzhiyun #define WL1273_SCAN_SPACING_SET 56 75*4882a593Smuzhiyun #define WL1273_REF_SET 57 76*4882a593Smuzhiyun #define WL1273_POWER_ENB_SET 90 77*4882a593Smuzhiyun #define WL1273_POWER_ATT_SET 58 78*4882a593Smuzhiyun #define WL1273_POWER_LEV_SET 59 79*4882a593Smuzhiyun #define WL1273_AUDIO_DEV_SET 60 80*4882a593Smuzhiyun #define WL1273_PILOT_DEV_SET 61 81*4882a593Smuzhiyun #define WL1273_RDS_DEV_SET 62 82*4882a593Smuzhiyun #define WL1273_PUPD_SET 91 83*4882a593Smuzhiyun #define WL1273_AUDIO_IO_SET 63 84*4882a593Smuzhiyun #define WL1273_PREMPH_SET 64 85*4882a593Smuzhiyun #define WL1273_MONO_SET 66 86*4882a593Smuzhiyun #define WL1273_MUTE 92 87*4882a593Smuzhiyun #define WL1273_MPX_LMT_ENABLE 67 88*4882a593Smuzhiyun #define WL1273_PI_SET 93 89*4882a593Smuzhiyun #define WL1273_ECC_SET 69 90*4882a593Smuzhiyun #define WL1273_PTY 70 91*4882a593Smuzhiyun #define WL1273_AF 71 92*4882a593Smuzhiyun #define WL1273_DISPLAY_MODE 74 93*4882a593Smuzhiyun #define WL1273_RDS_REP_SET 77 94*4882a593Smuzhiyun #define WL1273_RDS_CONFIG_DATA_SET 98 95*4882a593Smuzhiyun #define WL1273_RDS_DATA_SET 99 96*4882a593Smuzhiyun #define WL1273_RDS_DATA_ENB 94 97*4882a593Smuzhiyun #define WL1273_TA_SET 78 98*4882a593Smuzhiyun #define WL1273_TP_SET 79 99*4882a593Smuzhiyun #define WL1273_DI_SET 80 100*4882a593Smuzhiyun #define WL1273_MS_SET 81 101*4882a593Smuzhiyun #define WL1273_PS_SCROLL_SPEED 82 102*4882a593Smuzhiyun #define WL1273_TX_AUDIO_LEVEL_TEST 96 103*4882a593Smuzhiyun #define WL1273_TX_AUDIO_LEVEL_TEST_THRESHOLD 73 104*4882a593Smuzhiyun #define WL1273_TX_AUDIO_INPUT_LEVEL_RANGE_SET 54 105*4882a593Smuzhiyun #define WL1273_RX_ANTENNA_SELECT 87 106*4882a593Smuzhiyun #define WL1273_I2C_DEV_ADDR_SET 86 107*4882a593Smuzhiyun #define WL1273_REF_ERR_CALIB_PARAM_SET 88 108*4882a593Smuzhiyun #define WL1273_REF_ERR_CALIB_PERIODICITY_SET 89 109*4882a593Smuzhiyun #define WL1273_SOC_INT_TRIGGER 52 110*4882a593Smuzhiyun #define WL1273_SOC_AUDIO_PATH_SET 83 111*4882a593Smuzhiyun #define WL1273_SOC_PCMI_OVERRIDE 84 112*4882a593Smuzhiyun #define WL1273_SOC_I2S_OVERRIDE 85 113*4882a593Smuzhiyun #define WL1273_RSSI_BLOCK_SCAN_FREQ_SET 95 114*4882a593Smuzhiyun #define WL1273_RSSI_BLOCK_SCAN_START 97 115*4882a593Smuzhiyun #define WL1273_RSSI_BLOCK_SCAN_DATA_GET 5 116*4882a593Smuzhiyun #define WL1273_READ_FMANT_TUNE_VALUE 104 117*4882a593Smuzhiyun 118*4882a593Smuzhiyun #define WL1273_RDS_OFF 0 119*4882a593Smuzhiyun #define WL1273_RDS_ON 1 120*4882a593Smuzhiyun #define WL1273_RDS_RESET 2 121*4882a593Smuzhiyun 122*4882a593Smuzhiyun #define WL1273_AUDIO_DIGITAL 0 123*4882a593Smuzhiyun #define WL1273_AUDIO_ANALOG 1 124*4882a593Smuzhiyun 125*4882a593Smuzhiyun #define WL1273_MODE_RX BIT(0) 126*4882a593Smuzhiyun #define WL1273_MODE_TX BIT(1) 127*4882a593Smuzhiyun #define WL1273_MODE_OFF BIT(2) 128*4882a593Smuzhiyun #define WL1273_MODE_SUSPENDED BIT(3) 129*4882a593Smuzhiyun 130*4882a593Smuzhiyun #define WL1273_RADIO_CHILD BIT(0) 131*4882a593Smuzhiyun #define WL1273_CODEC_CHILD BIT(1) 132*4882a593Smuzhiyun 133*4882a593Smuzhiyun #define WL1273_RX_MONO 1 134*4882a593Smuzhiyun #define WL1273_RX_STEREO 0 135*4882a593Smuzhiyun #define WL1273_TX_MONO 0 136*4882a593Smuzhiyun #define WL1273_TX_STEREO 1 137*4882a593Smuzhiyun 138*4882a593Smuzhiyun #define WL1273_MAX_VOLUME 0xffff 139*4882a593Smuzhiyun #define WL1273_DEFAULT_VOLUME 0x78b8 140*4882a593Smuzhiyun 141*4882a593Smuzhiyun /* I2S protocol, left channel first, data width 16 bits */ 142*4882a593Smuzhiyun #define WL1273_PCM_DEF_MODE 0x00 143*4882a593Smuzhiyun 144*4882a593Smuzhiyun /* Rx */ 145*4882a593Smuzhiyun #define WL1273_AUDIO_ENABLE_I2S BIT(0) 146*4882a593Smuzhiyun #define WL1273_AUDIO_ENABLE_ANALOG BIT(1) 147*4882a593Smuzhiyun 148*4882a593Smuzhiyun /* Tx */ 149*4882a593Smuzhiyun #define WL1273_AUDIO_IO_SET_ANALOG 0 150*4882a593Smuzhiyun #define WL1273_AUDIO_IO_SET_I2S 1 151*4882a593Smuzhiyun 152*4882a593Smuzhiyun #define WL1273_PUPD_SET_OFF 0x00 153*4882a593Smuzhiyun #define WL1273_PUPD_SET_ON 0x01 154*4882a593Smuzhiyun #define WL1273_PUPD_SET_RETENTION 0x10 155*4882a593Smuzhiyun 156*4882a593Smuzhiyun /* I2S mode */ 157*4882a593Smuzhiyun #define WL1273_IS2_WIDTH_32 0x0 158*4882a593Smuzhiyun #define WL1273_IS2_WIDTH_40 0x1 159*4882a593Smuzhiyun #define WL1273_IS2_WIDTH_22_23 0x2 160*4882a593Smuzhiyun #define WL1273_IS2_WIDTH_23_22 0x3 161*4882a593Smuzhiyun #define WL1273_IS2_WIDTH_48 0x4 162*4882a593Smuzhiyun #define WL1273_IS2_WIDTH_50 0x5 163*4882a593Smuzhiyun #define WL1273_IS2_WIDTH_60 0x6 164*4882a593Smuzhiyun #define WL1273_IS2_WIDTH_64 0x7 165*4882a593Smuzhiyun #define WL1273_IS2_WIDTH_80 0x8 166*4882a593Smuzhiyun #define WL1273_IS2_WIDTH_96 0x9 167*4882a593Smuzhiyun #define WL1273_IS2_WIDTH_128 0xa 168*4882a593Smuzhiyun #define WL1273_IS2_WIDTH 0xf 169*4882a593Smuzhiyun 170*4882a593Smuzhiyun #define WL1273_IS2_FORMAT_STD (0x0 << 4) 171*4882a593Smuzhiyun #define WL1273_IS2_FORMAT_LEFT (0x1 << 4) 172*4882a593Smuzhiyun #define WL1273_IS2_FORMAT_RIGHT (0x2 << 4) 173*4882a593Smuzhiyun #define WL1273_IS2_FORMAT_USER (0x3 << 4) 174*4882a593Smuzhiyun 175*4882a593Smuzhiyun #define WL1273_IS2_MASTER (0x0 << 6) 176*4882a593Smuzhiyun #define WL1273_IS2_SLAVEW (0x1 << 6) 177*4882a593Smuzhiyun 178*4882a593Smuzhiyun #define WL1273_IS2_TRI_AFTER_SENDING (0x0 << 7) 179*4882a593Smuzhiyun #define WL1273_IS2_TRI_ALWAYS_ACTIVE (0x1 << 7) 180*4882a593Smuzhiyun 181*4882a593Smuzhiyun #define WL1273_IS2_SDOWS_RR (0x0 << 8) 182*4882a593Smuzhiyun #define WL1273_IS2_SDOWS_RF (0x1 << 8) 183*4882a593Smuzhiyun #define WL1273_IS2_SDOWS_FR (0x2 << 8) 184*4882a593Smuzhiyun #define WL1273_IS2_SDOWS_FF (0x3 << 8) 185*4882a593Smuzhiyun 186*4882a593Smuzhiyun #define WL1273_IS2_TRI_OPT (0x0 << 10) 187*4882a593Smuzhiyun #define WL1273_IS2_TRI_ALWAYS (0x1 << 10) 188*4882a593Smuzhiyun 189*4882a593Smuzhiyun #define WL1273_IS2_RATE_48K (0x0 << 12) 190*4882a593Smuzhiyun #define WL1273_IS2_RATE_44_1K (0x1 << 12) 191*4882a593Smuzhiyun #define WL1273_IS2_RATE_32K (0x2 << 12) 192*4882a593Smuzhiyun #define WL1273_IS2_RATE_22_05K (0x4 << 12) 193*4882a593Smuzhiyun #define WL1273_IS2_RATE_16K (0x5 << 12) 194*4882a593Smuzhiyun #define WL1273_IS2_RATE_12K (0x8 << 12) 195*4882a593Smuzhiyun #define WL1273_IS2_RATE_11_025 (0x9 << 12) 196*4882a593Smuzhiyun #define WL1273_IS2_RATE_8K (0xa << 12) 197*4882a593Smuzhiyun #define WL1273_IS2_RATE (0xf << 12) 198*4882a593Smuzhiyun 199*4882a593Smuzhiyun #define WL1273_I2S_DEF_MODE (WL1273_IS2_WIDTH_32 | \ 200*4882a593Smuzhiyun WL1273_IS2_FORMAT_STD | \ 201*4882a593Smuzhiyun WL1273_IS2_MASTER | \ 202*4882a593Smuzhiyun WL1273_IS2_TRI_AFTER_SENDING | \ 203*4882a593Smuzhiyun WL1273_IS2_SDOWS_RR | \ 204*4882a593Smuzhiyun WL1273_IS2_TRI_OPT | \ 205*4882a593Smuzhiyun WL1273_IS2_RATE_48K) 206*4882a593Smuzhiyun 207*4882a593Smuzhiyun #define SCHAR_MIN (-128) 208*4882a593Smuzhiyun #define SCHAR_MAX 127 209*4882a593Smuzhiyun 210*4882a593Smuzhiyun #define WL1273_FR_EVENT BIT(0) 211*4882a593Smuzhiyun #define WL1273_BL_EVENT BIT(1) 212*4882a593Smuzhiyun #define WL1273_RDS_EVENT BIT(2) 213*4882a593Smuzhiyun #define WL1273_BBLK_EVENT BIT(3) 214*4882a593Smuzhiyun #define WL1273_LSYNC_EVENT BIT(4) 215*4882a593Smuzhiyun #define WL1273_LEV_EVENT BIT(5) 216*4882a593Smuzhiyun #define WL1273_IFFR_EVENT BIT(6) 217*4882a593Smuzhiyun #define WL1273_PI_EVENT BIT(7) 218*4882a593Smuzhiyun #define WL1273_PD_EVENT BIT(8) 219*4882a593Smuzhiyun #define WL1273_STIC_EVENT BIT(9) 220*4882a593Smuzhiyun #define WL1273_MAL_EVENT BIT(10) 221*4882a593Smuzhiyun #define WL1273_POW_ENB_EVENT BIT(11) 222*4882a593Smuzhiyun #define WL1273_SCAN_OVER_EVENT BIT(12) 223*4882a593Smuzhiyun #define WL1273_ERROR_EVENT BIT(13) 224*4882a593Smuzhiyun 225*4882a593Smuzhiyun #define TUNER_MODE_STOP_SEARCH 0 226*4882a593Smuzhiyun #define TUNER_MODE_PRESET 1 227*4882a593Smuzhiyun #define TUNER_MODE_AUTO_SEEK 2 228*4882a593Smuzhiyun #define TUNER_MODE_AF 3 229*4882a593Smuzhiyun #define TUNER_MODE_AUTO_SEEK_PI 4 230*4882a593Smuzhiyun #define TUNER_MODE_AUTO_SEEK_BULK 5 231*4882a593Smuzhiyun 232*4882a593Smuzhiyun #define RDS_BLOCK_SIZE 3 233*4882a593Smuzhiyun 234*4882a593Smuzhiyun struct wl1273_fm_platform_data { 235*4882a593Smuzhiyun int (*request_resources) (struct i2c_client *client); 236*4882a593Smuzhiyun void (*free_resources) (void); 237*4882a593Smuzhiyun void (*enable) (void); 238*4882a593Smuzhiyun void (*disable) (void); 239*4882a593Smuzhiyun 240*4882a593Smuzhiyun u8 forbidden_modes; 241*4882a593Smuzhiyun unsigned int children; 242*4882a593Smuzhiyun }; 243*4882a593Smuzhiyun 244*4882a593Smuzhiyun #define WL1273_FM_CORE_CELLS 2 245*4882a593Smuzhiyun 246*4882a593Smuzhiyun #define WL1273_BAND_OTHER 0 247*4882a593Smuzhiyun #define WL1273_BAND_JAPAN 1 248*4882a593Smuzhiyun 249*4882a593Smuzhiyun #define WL1273_BAND_JAPAN_LOW 76000 250*4882a593Smuzhiyun #define WL1273_BAND_JAPAN_HIGH 90000 251*4882a593Smuzhiyun #define WL1273_BAND_OTHER_LOW 87500 252*4882a593Smuzhiyun #define WL1273_BAND_OTHER_HIGH 108000 253*4882a593Smuzhiyun 254*4882a593Smuzhiyun #define WL1273_BAND_TX_LOW 76000 255*4882a593Smuzhiyun #define WL1273_BAND_TX_HIGH 108000 256*4882a593Smuzhiyun 257*4882a593Smuzhiyun struct wl1273_core { 258*4882a593Smuzhiyun struct mfd_cell cells[WL1273_FM_CORE_CELLS]; 259*4882a593Smuzhiyun struct wl1273_fm_platform_data *pdata; 260*4882a593Smuzhiyun 261*4882a593Smuzhiyun unsigned int mode; 262*4882a593Smuzhiyun unsigned int i2s_mode; 263*4882a593Smuzhiyun unsigned int volume; 264*4882a593Smuzhiyun unsigned int audio_mode; 265*4882a593Smuzhiyun unsigned int channel_number; 266*4882a593Smuzhiyun struct mutex lock; /* for serializing fm radio operations */ 267*4882a593Smuzhiyun 268*4882a593Smuzhiyun struct i2c_client *client; 269*4882a593Smuzhiyun 270*4882a593Smuzhiyun int (*read)(struct wl1273_core *core, u8, u16 *); 271*4882a593Smuzhiyun int (*write)(struct wl1273_core *core, u8, u16); 272*4882a593Smuzhiyun int (*write_data)(struct wl1273_core *core, u8 *, u16); 273*4882a593Smuzhiyun int (*set_audio)(struct wl1273_core *core, unsigned int); 274*4882a593Smuzhiyun int (*set_volume)(struct wl1273_core *core, unsigned int); 275*4882a593Smuzhiyun }; 276*4882a593Smuzhiyun 277*4882a593Smuzhiyun #endif /* ifndef WL1273_CORE_H */ 278