include/asm/sysreg.h

1 /* SPDX-License-Identifier: GPL-2.0-only */
14 #include <linux/kasan-tags.h>
20  *	[20-19] : Op0
21  *	[18-16] : Op1
22  *	[15-12] : CRn
23  *	[11-8]  : CRm
24  *	[7-5]   : Op2
30 #define CRn_shift	12
81  * As per Arm ARM for v8-A, Section "C.5.1.3 op0 == 0b00, architectural hints,
238 #define SYS_PAR_EL1_F			BIT(0)
252 #define SYS_PMSIDR_EL1_MAXSIZE_SHIFT	12
346 #define TRBLIMITR_LIMIT_SHIFT		12
347 #define TRBLIMITR_NVM			BIT(5)
352 #define TRBLIMITR_ENABLE		BIT(0)
356 #define TRBBASER_BASE_SHIFT		12
359 #define TRBSR_IRQ			BIT(22)
360 #define TRBSR_TRG			BIT(21)
361 #define TRBSR_WRAP			BIT(20)
362 #define TRBSR_ABORT			BIT(18)
363 #define TRBSR_STOP			BIT(17)
378 #define TRBIDR_FLAG			BIT(5)
379 #define TRBIDR_PROG			BIT(4)
397 #define SYS_VBAR_EL1			sys_reg(3, 0, 12, 0, 0)
398 #define SYS_DISR_EL1			sys_reg(3, 0, 12, 1, 1)
400 #define SYS_ICC_IAR0_EL1		sys_reg(3, 0, 12, 8, 0)
401 #define SYS_ICC_EOIR0_EL1		sys_reg(3, 0, 12, 8, 1)
402 #define SYS_ICC_HPPIR0_EL1		sys_reg(3, 0, 12, 8, 2)
403 #define SYS_ICC_BPR0_EL1		sys_reg(3, 0, 12, 8, 3)
404 #define SYS_ICC_AP0Rn_EL1(n)		sys_reg(3, 0, 12, 8, 4 | n)
409 #define SYS_ICC_AP1Rn_EL1(n)		sys_reg(3, 0, 12, 9, n)
414 #define SYS_ICC_DIR_EL1			sys_reg(3, 0, 12, 11, 1)
415 #define SYS_ICC_RPR_EL1			sys_reg(3, 0, 12, 11, 3)
416 #define SYS_ICC_SGI1R_EL1		sys_reg(3, 0, 12, 11, 5)
417 #define SYS_ICC_ASGI1R_EL1		sys_reg(3, 0, 12, 11, 6)
418 #define SYS_ICC_SGI0R_EL1		sys_reg(3, 0, 12, 11, 7)
419 #define SYS_ICC_IAR1_EL1		sys_reg(3, 0, 12, 12, 0)
420 #define SYS_ICC_EOIR1_EL1		sys_reg(3, 0, 12, 12, 1)
421 #define SYS_ICC_HPPIR1_EL1		sys_reg(3, 0, 12, 12, 2)
422 #define SYS_ICC_BPR1_EL1		sys_reg(3, 0, 12, 12, 3)
423 #define SYS_ICC_CTLR_EL1		sys_reg(3, 0, 12, 12, 4)
424 #define SYS_ICC_SRE_EL1			sys_reg(3, 0, 12, 12, 5)
425 #define SYS_ICC_IGRPEN0_EL1		sys_reg(3, 0, 12, 12, 6)
426 #define SYS_ICC_IGRPEN1_EL1		sys_reg(3, 0, 12, 12, 7)
448 #define SYS_PMCR_EL0			sys_reg(3, 3, 9, 12, 0)
449 #define SYS_PMCNTENSET_EL0		sys_reg(3, 3, 9, 12, 1)
450 #define SYS_PMCNTENCLR_EL0		sys_reg(3, 3, 9, 12, 2)
451 #define SYS_PMOVSCLR_EL0		sys_reg(3, 3, 9, 12, 3)
452 #define SYS_PMSWINC_EL0			sys_reg(3, 3, 9, 12, 4)
453 #define SYS_PMSELR_EL0			sys_reg(3, 3, 9, 12, 5)
454 #define SYS_PMCEID0_EL0			sys_reg(3, 3, 9, 12, 6)
455 #define SYS_PMCEID1_EL0			sys_reg(3, 3, 9, 12, 7)
483  * n: 0-15
489  * n: 0-15
494 #define SYS_AMEVCNTR1_EL0(n)		SYS_AM_EL0(12 + ((n) >> 3), (n) & 7)
537 #define SYS_VDISR_EL2			sys_reg(3, 4, 12, 1,  1)
538 #define __SYS__AP0Rx_EL2(x)		sys_reg(3, 4, 12, 8, x)
544 #define __SYS__AP1Rx_EL2(x)		sys_reg(3, 4, 12, 9, x)
550 #define SYS_ICH_VSEIR_EL2		sys_reg(3, 4, 12, 9, 4)
551 #define SYS_ICC_SRE_EL2			sys_reg(3, 4, 12, 9, 5)
552 #define SYS_ICH_HCR_EL2			sys_reg(3, 4, 12, 11, 0)
553 #define SYS_ICH_VTR_EL2			sys_reg(3, 4, 12, 11, 1)
554 #define SYS_ICH_MISR_EL2		sys_reg(3, 4, 12, 11, 2)
555 #define SYS_ICH_EISR_EL2		sys_reg(3, 4, 12, 11, 3)
556 #define SYS_ICH_ELRSR_EL2		sys_reg(3, 4, 12, 11, 5)
557 #define SYS_ICH_VMCR_EL2		sys_reg(3, 4, 12, 11, 7)
559 #define __SYS__LR0_EL2(x)		sys_reg(3, 4, 12, 12, x)
569 #define __SYS__LR8_EL2(x)		sys_reg(3, 4, 12, 13, x)
595 #define SYS_VBAR_EL12			sys_reg(3, 5, 12, 0, 0)
606 #define SCTLR_ELx_DSSBS	(BIT(44))
607 #define SCTLR_ELx_ATA	(BIT(43))
617 #define SCTLR_ELx_ITFSB	(BIT(37))
618 #define SCTLR_ELx_ENIA	(BIT(SCTLR_ELx_ENIA_SHIFT))
619 #define SCTLR_ELx_ENIB	(BIT(30))
620 #define SCTLR_ELx_ENDA	(BIT(27))
621 #define SCTLR_ELx_EE    (BIT(25))
622 #define SCTLR_ELx_IESB	(BIT(21))
623 #define SCTLR_ELx_WXN	(BIT(19))
624 #define SCTLR_ELx_ENDB	(BIT(13))
625 #define SCTLR_ELx_I	(BIT(12))
626 #define SCTLR_ELx_SA	(BIT(3))
627 #define SCTLR_ELx_C	(BIT(2))
628 #define SCTLR_ELx_A	(BIT(1))
629 #define SCTLR_ELx_M	(BIT(0))
632 #define SCTLR_EL2_RES1	((BIT(4))  | (BIT(5))  | (BIT(11)) | (BIT(16)) | \
633 			 (BIT(18)) | (BIT(22)) | (BIT(23)) | (BIT(28)) | \
634 			 (BIT(29)))
650 #define SCTLR_EL1_ATA0		(BIT(42))
658 #define SCTLR_EL1_BT1		(BIT(36))
659 #define SCTLR_EL1_BT0		(BIT(35))
660 #define SCTLR_EL1_UCI		(BIT(26))
661 #define SCTLR_EL1_E0E		(BIT(24))
662 #define SCTLR_EL1_SPAN		(BIT(23))
663 #define SCTLR_EL1_NTWE		(BIT(18))
664 #define SCTLR_EL1_NTWI		(BIT(16))
665 #define SCTLR_EL1_UCT		(BIT(15))
666 #define SCTLR_EL1_DZE		(BIT(14))
667 #define SCTLR_EL1_UMA		(BIT(9))
668 #define SCTLR_EL1_SED		(BIT(8))
669 #define SCTLR_EL1_ITD		(BIT(7))
670 #define SCTLR_EL1_CP15BEN	(BIT(5))
671 #define SCTLR_EL1_SA0		(BIT(4))
673 #define SCTLR_EL1_RES1	((BIT(11)) | (BIT(20)) | (BIT(22)) | (BIT(28)) | \
674 			 (BIT(29)))
717 #define ID_AA64ISAR0_SHA2_SHIFT		12
735 #define ID_AA64ISAR1_JSCVT_SHIFT	12
784 #define ID_AA64PFR0_EL3_SHIFT		12
803 #define ID_AA64PFR1_RASFRAC_SHIFT	12
850 #define ID_AA64MMFR0_SNSMEM_SHIFT	12
888 #define ID_AA64MMFR1_HPD_SHIFT		12
908 #define ID_AA64MMFR2_IESB_SHIFT		12
920 #define ID_AA64DFR0_BRPS_SHIFT		12
942 #define ID_ISAR4_SMC_SHIFT		12
952 #define ID_ISAR0_CMPBRANCH_SHIFT	12
959 #define ID_ISAR5_SHA2_SHIFT		12
967 #define ID_ISAR6_SB_SHIFT		12
976 #define ID_MMFR0_SHARELVL_SHIFT		12
985 #define ID_MMFR4_CNP_SHIFT		12
994 #define ID_PFR0_STATE3_SHIFT		12
1002 #define ID_DFR0_COPTRC_SHIFT		12
1014 #define MVFR0_FPTRAP_SHIFT		12
1023 #define MVFR1_SIMDINT_SHIFT		12
1032 #define ID_PFR1_VIRTUALIZATION_SHIFT	12
1066 #define CPACR_EL1_ZEN_EL1EN	(BIT(16)) /* enable EL1 access */
1067 #define CPACR_EL1_ZEN_EL0EN	(BIT(17)) /* enable EL0 access, if EL1EN set */
1070 /* TCR EL1 Bit Definitions */
1071 #define SYS_TCR_EL1_TCMA1	(BIT(58))
1072 #define SYS_TCR_EL1_TCMA0	(BIT(57))
1075 #define SYS_GCR_EL1_RRND	(BIT(16))
1081  * only uses tags in the range 0xF0-0xFF, which we map to MTE tags 0x0-0xF.
1102 /* TFSR{,E0}_EL1 bit definitions */
1109 #define SYS_MPIDR_SAFE_VAL	(BIT(31))
1115 #define TRFCR_EL2_CX			BIT(3)
1116 #define TRFCR_ELx_ExTRE			BIT(1)
1117 #define TRFCR_ELx_E0TRE			BIT(0)
1121 	.irp	num,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30
1141 "	.irp	num,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30\n" \
1211  * set mask are set. Other bits are left as-is.