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/OK3568_Linux_fs/kernel/drivers/gpu/drm/amd/include/asic_reg/nbio/
H A Dnbio_2_3_default.h26 #define mmBIF_BX_PF_MM_INDEX_DEFAULT 0x00000000
27 #define mmBIF_BX_PF_MM_DATA_DEFAULT 0x00000000
28 #define mmBIF_BX_PF_MM_INDEX_HI_DEFAULT 0x00000000
32 #define mmSYSHUB_INDEX_OVLP_DEFAULT 0x00000000
33 #define mmSYSHUB_DATA_OVLP_DEFAULT 0x00000000
34 #define mmPCIE_INDEX_DEFAULT 0x00000000
35 #define mmPCIE_DATA_DEFAULT 0x00000000
36 #define mmPCIE_INDEX2_DEFAULT 0x00000000
37 #define mmPCIE_DATA2_DEFAULT 0x00000000
38 #define mmSBIOS_SCRATCH_0_DEFAULT 0x00000000
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H A Dnbio_7_0_default.h26 #define cfgNB_NBCFG0_NB_VENDOR_ID_DEFAULT 0x00000000
27 #define cfgNB_NBCFG0_NB_DEVICE_ID_DEFAULT 0x00000000
28 #define cfgNB_NBCFG0_NB_COMMAND_DEFAULT 0x00000000
29 #define cfgNB_NBCFG0_NB_STATUS_DEFAULT 0x00000000
30 #define cfgNB_NBCFG0_NB_REVISION_ID_DEFAULT 0x00000000
31 #define cfgNB_NBCFG0_NB_REGPROG_INF_DEFAULT 0x00000000
32 #define cfgNB_NBCFG0_NB_SUB_CLASS_DEFAULT 0x00000000
33 #define cfgNB_NBCFG0_NB_BASE_CODE_DEFAULT 0x00000000
34 #define cfgNB_NBCFG0_NB_CACHE_LINE_DEFAULT 0x00000000
35 #define cfgNB_NBCFG0_NB_LATENCY_DEFAULT 0x00000000
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H A Dnbio_6_1_default.h26 #define cfgPSWUSCFG0_VENDOR_ID_DEFAULT 0x00000000
27 #define cfgPSWUSCFG0_DEVICE_ID_DEFAULT 0x00000000
28 #define cfgPSWUSCFG0_COMMAND_DEFAULT 0x00000000
29 #define cfgPSWUSCFG0_STATUS_DEFAULT 0x00000000
30 #define cfgPSWUSCFG0_REVISION_ID_DEFAULT 0x00000000
31 #define cfgPSWUSCFG0_PROG_INTERFACE_DEFAULT 0x00000000
32 #define cfgPSWUSCFG0_SUB_CLASS_DEFAULT 0x00000000
33 #define cfgPSWUSCFG0_BASE_CLASS_DEFAULT 0x00000000
34 #define cfgPSWUSCFG0_CACHE_LINE_DEFAULT 0x00000000
35 #define cfgPSWUSCFG0_LATENCY_DEFAULT 0x00000000
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/OK3568_Linux_fs/kernel/Documentation/devicetree/bindings/mtd/
H A Dlpc32xx-slc.txt29 reg = <0x20020000 0x1000>;
46 reg = <0x00000000 0x00064000>;
/OK3568_Linux_fs/kernel/arch/arm/mach-lpc32xx/
H A Dphy3250.c47 .slave_channels = &pl08x_slave_channels[0],
64 OF_DEV_AUXDATA("arm,pl080", 0x31000000, "pl08xdmac", &pl08x_pd),
65 OF_DEV_AUXDATA("nxp,lpc3220-slc", 0x20020000, "20020000.flash",
67 OF_DEV_AUXDATA("nxp,lpc3220-mlc", 0x200a8000, "200a8000.flash",
88 .atag_offset = 0x100,
H A Dlpc32xx.h17 * AHB 0 physical base addresses
19 #define LPC32XX_SLC_BASE 0x20020000
20 #define LPC32XX_SSP0_BASE 0x20084000
21 #define LPC32XX_SPI1_BASE 0x20088000
22 #define LPC32XX_SSP1_BASE 0x2008C000
23 #define LPC32XX_SPI2_BASE 0x20090000
24 #define LPC32XX_I2S0_BASE 0x20094000
25 #define LPC32XX_SD_BASE 0x20098000
26 #define LPC32XX_I2S1_BASE 0x2009C000
27 #define LPC32XX_MLC_BASE 0x200A8000
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/OK3568_Linux_fs/u-boot/arch/arm/include/asm/arch-lpc32xx/
H A Dcpu.h13 #define SLC_NAND_BASE 0x20020000 /* SLC NAND Flash registers base */
14 #define SSP0_BASE 0x20084000 /* SSP0 registers base */
15 #define SD_CARD_BASE 0x20098000 /* SD card interface registers base */
16 #define MLC_NAND_BASE 0x200A8000 /* MLC NAND Flash registers base */
17 #define DMA_BASE 0x31000000 /* DMA controller registers base */
18 #define USB_BASE 0x31020000 /* USB registers base */
19 #define LCD_BASE 0x31040000 /* LCD registers base */
20 #define ETHERNET_BASE 0x31060000 /* Ethernet registers base */
21 #define EMC_BASE 0x31080000 /* EMC configuration registers base */
24 #define CLK_PM_BASE 0x40004000 /* System control registers base */
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/OK3568_Linux_fs/kernel/Documentation/devicetree/bindings/arm/
H A Dcoresight-cti.yaml81 pattern: "^cti(@[0-9a-f]+)$"
123 const: 0
129 '^trig-conns@([0-9]+)$':
230 reg = <0x20020000 0x1000>;
241 reg = <0x859000 0x1000>;
257 reg = <0x858000 0x1000>;
265 #size-cells = <0>;
267 trig-conns@0 {
268 reg = <0>;
285 arm,trig-in-sigs = <0 1>;
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/OK3568_Linux_fs/u-boot/arch/arm/dts/
H A Drk3xxx.dtsi41 reg = <0x20018000 0x4000>;
42 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
52 reg = <0x2001c000 0x4000>;
53 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
64 reg = <0x20078000 0x4000>;
77 #clock-cells = <0>;
83 reg = <0x10138000 0x1000>;
90 reg = <0x1013c000 0x100>;
95 reg = <0x1013c200 0x20>;
96 interrupts = <GIC_PPI 11 0x304>;
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H A D.rk3066a-mk808.dtb.dts.tmp
H A D.rk3188-radxarock.dtb.dts.tmp
/OK3568_Linux_fs/kernel/arch/arm/boot/dts/
H A Dlpc32xx.dtsi20 #size-cells = <0>;
22 cpu@0 {
25 reg = <0x0>;
32 #clock-cells = <0>;
39 #clock-cells = <0>;
49 ranges = <0x00000000 0x00000000 0x10000000>,
50 <0x20000000 0x20000000 0x30000000>,
51 <0xe0000000 0xe0000000 0x04000000>;
55 reg = <0x08000000 0x20000>;
59 ranges = <0x00000000 0x08000000 0x20000>;
[all …]
H A Drk3128x.dtsi32 #size-cells = <0>;
37 reg = <0xf00>;
50 reg = <0xf01>;
59 reg = <0xf02>;
68 reg = <0xf03>;
81 0 254 20
86 1 4 0
134 reg = <0x110f0000 0x4000>;
135 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
180 1 5 0
[all …]
/OK3568_Linux_fs/kernel/arch/arm64/boot/dts/broadcom/northstar2/
H A Dns2.dtsi33 /memreserve/ 0x81000000 0x00200000;
46 #size-cells = <0>;
48 A57_0: cpu@0 {
51 reg = <0 0>;
59 reg = <0 1>;
67 reg = <0 2>;
75 reg = <0 3>;
80 CLUSTER0_L2: l2-cache@0 {
92 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_RAW(0xff) |
94 <GIC_PPI 14 (GIC_CPU_MASK_RAW(0xff) |
[all …]
/OK3568_Linux_fs/external/rkwifibt/drivers/rtl8821cs/hal/phydm/rtl8821c/
H A Dphydm_hal_api8821c.c34 u32 igi = 0x20; in phydm_igi_toggle_8821c()
36 igi = odm_get_bb_reg(dm, R_0xc50, 0x7f); in phydm_igi_toggle_8821c()
37 odm_set_bb_reg(dm, R_0xc50, 0x7f, (igi - 2)); in phydm_igi_toggle_8821c()
38 odm_set_bb_reg(dm, R_0xc50, 0x7f, igi); in phydm_igi_toggle_8821c()
44 s8 rx_pwr_all = 0; in phydm_cck_rssi_8821c()
45 s8 lna_gain = 0; in phydm_cck_rssi_8821c()
52 if (dm->cck_agc_report_type == 0) in phydm_cck_rssi_8821c()
66 #if 0 in phydm_rfe_8821c()
72 odm_set_bb_reg(dm, R_0xcb0, (MASKBYTE2 | MASKLWORD), 0x704570); in phydm_rfe_8821c()
73 odm_set_bb_reg(dm, R_0xeb0, (MASKBYTE2 | MASKLWORD), 0x704570); in phydm_rfe_8821c()
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/OK3568_Linux_fs/kernel/drivers/net/wireless/rockchip_wlan/rtl8821cs/hal/phydm/rtl8821c/
H A Dphydm_hal_api8821c.c35 u32 igi = 0x20; in phydm_igi_toggle_8821c()
37 igi = odm_get_bb_reg(dm, R_0xc50, 0x7f); in phydm_igi_toggle_8821c()
38 odm_set_bb_reg(dm, R_0xc50, 0x7f, (igi - 2)); in phydm_igi_toggle_8821c()
39 odm_set_bb_reg(dm, R_0xc50, 0x7f, igi); in phydm_igi_toggle_8821c()
45 s8 rx_pwr_all = 0; in phydm_cck_rssi_8821c()
46 s8 lna_gain = 0; in phydm_cck_rssi_8821c()
53 if (dm->cck_agc_report_type == 0) in phydm_cck_rssi_8821c()
67 #if 0 in phydm_rfe_8821c()
73 odm_set_bb_reg(dm, R_0xcb0, (MASKBYTE2 | MASKLWORD), 0x704570); in phydm_rfe_8821c()
74 odm_set_bb_reg(dm, R_0xeb0, (MASKBYTE2 | MASKLWORD), 0x704570); in phydm_rfe_8821c()
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/OK3568_Linux_fs/kernel/net/ipv6/
H A Dsit.c62 #define HASH(addr) (((__force u32)addr^((__force u32)addr>>4))&0xF)
105 int ifindex = dev ? dev->ifindex : 0; in ipip6_tunnel_lookup()
129 t = rcu_dereference(sitn->tunnels_wc[0]); in ipip6_tunnel_lookup()
140 unsigned int h = 0; in __ipip6_bucket()
141 int prio = 0; in __ipip6_bucket()
189 ipv6_addr_set(&t->ip6rd.prefix, htonl(0x20020000), 0, 0, 0); in ipip6_tunnel_clone_6rd()
190 t->ip6rd.relay_prefix = 0; in ipip6_tunnel_clone_6rd()
192 t->ip6rd.relay_prefixlen = 0; in ipip6_tunnel_clone_6rd()
216 if (err < 0) in ipip6_tunnel_create()
222 return 0; in ipip6_tunnel_create()
[all …]
/OK3568_Linux_fs/kernel/drivers/net/wireless/realtek/rtw88/
H A Drtw8821c.c37 efuse->lna_type_2g = map->lna_type_2g[0]; in rtw8821c_read_efuse()
38 efuse->lna_type_5g = map->lna_type_5g[0]; in rtw8821c_read_efuse()
40 efuse->country_code[0] = map->country_code[0]; in rtw8821c_read_efuse()
43 efuse->regd = map->rf_board_option & 0x7; in rtw8821c_read_efuse()
44 efuse->thermal_meter[0] = map->thermal_meter; in rtw8821c_read_efuse()
49 for (i = 0; i < 4; i++) in rtw8821c_read_efuse()
61 return 0; in rtw8821c_read_efuse()
65 0x081, 0x088, 0x090, 0x099, 0x0a2, 0x0ac, 0x0b6, 0x0c0, 0x0cc, 0x0d8,
66 0x0e5, 0x0f2, 0x101, 0x110, 0x120, 0x131, 0x143, 0x156, 0x16a, 0x180,
67 0x197, 0x1af, 0x1c8, 0x1e3, 0x200, 0x21e, 0x23e, 0x261, 0x285, 0x2ab,
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/OK3568_Linux_fs/kernel/drivers/net/ethernet/broadcom/bnx2x/
H A Dbnx2x_hsi.h17 #define FW_ENCODE_32BIT_PATTERN 0x1e1e1e1e
23 #define BNX2X_MAX_ISCSI_TRGT_CONN_MASK 0xFFFF
24 #define BNX2X_MAX_ISCSI_TRGT_CONN_SHIFT 0
25 #define BNX2X_MAX_ISCSI_INIT_CONN_MASK 0xFFFF0000
31 #define BNX2X_MAX_FCOE_TRGT_CONN_MASK 0xFFFF
32 #define BNX2X_MAX_FCOE_TRGT_CONN_SHIFT 0
33 #define BNX2X_MAX_FCOE_INIT_CONN_MASK 0xFFFF0000
42 #define PIN_CFG_NA 0x00000000
43 #define PIN_CFG_GPIO0_P0 0x00000001
44 #define PIN_CFG_GPIO1_P0 0x00000002
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H A Dbnx2x_main.c127 MODULE_PARM_DESC(mrrs, " Force Max Read Req Size (0..3) (for debug)");
148 BCM57710 = 0,
287 { 0 }
413 DP(msglvl, "DMAE: opcode 0x%08x\n" in bnx2x_dp_dmae()
415 "comp_addr [%x:%08x], comp_val 0x%08x\n", in bnx2x_dp_dmae()
421 DP(msglvl, "DMAE: opcode 0x%08x\n" in bnx2x_dp_dmae()
423 "comp_addr [%x:%08x], comp_val 0x%08x\n", in bnx2x_dp_dmae()
431 DP(msglvl, "DMAE: opcode 0x%08x\n" in bnx2x_dp_dmae()
433 "comp_addr [%x:%08x], comp_val 0x%08x\n", in bnx2x_dp_dmae()
439 DP(msglvl, "DMAE: opcode 0x%08x\n" in bnx2x_dp_dmae()
[all …]