1/* 2 * Copyright (c) 2018 Fuzhou Rockchip Electronics Co., Ltd 3 * 4 * SPDX-License-Identifier: (GPL-2.0+ OR MIT) 5 */ 6 7#include <dt-bindings/gpio/gpio.h> 8#include <dt-bindings/interrupt-controller/irq.h> 9#include <dt-bindings/interrupt-controller/arm-gic.h> 10#include <dt-bindings/pinctrl/rockchip.h> 11#include <dt-bindings/clock/rk3228-cru.h> 12#include <dt-bindings/power/rk3228-power.h> 13#include <dt-bindings/suspend/rockchip-rk322x.h> 14#include <dt-bindings/soc/rockchip,boot-mode.h> 15#include <dt-bindings/thermal/thermal.h> 16#include <dt-bindings/soc/rockchip-system-status.h> 17#include "rk322x-dram-default-timing.dtsi" 18#include "skeleton.dtsi" 19 20/ { 21 interrupt-parent = <&gic>; 22 23 aliases { 24 serial0 = &uart0; 25 serial1 = &uart1; 26 serial2 = &uart2; 27 spi0 = &spi0; 28 }; 29 30 cpus { 31 #address-cells = <1>; 32 #size-cells = <0>; 33 34 cpu0: cpu@f00 { 35 device_type = "cpu"; 36 compatible = "arm,cortex-a7"; 37 reg = <0xf00>; 38 enable-method = "psci"; 39 resets = <&cru SRST_CORE0>; 40 operating-points-v2 = <&cpu0_opp_table>; 41 #cooling-cells = <2>; /* min followed by max */ 42 dynamic-power-coefficient = <122>; 43 clock-latency = <40000>; 44 clocks = <&cru ARMCLK>; 45 }; 46 47 cpu1: cpu@f01 { 48 device_type = "cpu"; 49 compatible = "arm,cortex-a7"; 50 reg = <0xf01>; 51 enable-method = "psci"; 52 resets = <&cru SRST_CORE1>; 53 operating-points-v2 = <&cpu0_opp_table>; 54 }; 55 56 cpu2: cpu@f02 { 57 device_type = "cpu"; 58 compatible = "arm,cortex-a7"; 59 reg = <0xf02>; 60 enable-method = "psci"; 61 resets = <&cru SRST_CORE2>; 62 operating-points-v2 = <&cpu0_opp_table>; 63 }; 64 65 cpu3: cpu@f03 { 66 device_type = "cpu"; 67 compatible = "arm,cortex-a7"; 68 reg = <0xf03>; 69 enable-method = "psci"; 70 resets = <&cru SRST_CORE3>; 71 operating-points-v2 = <&cpu0_opp_table>; 72 }; 73 }; 74 75 cpu0_opp_table: opp_table0 { 76 compatible = "operating-points-v2"; 77 opp-shared; 78 79 rockchip,avs = <1>; 80 rockchip,leakage-scaling-sel = < 81 0 254 20 82 >; 83 clocks = <&cru PLL_APLL>; 84 rockchip,max-volt = <1350000>; 85 rockchip,leakage-voltage-sel = < 86 1 4 0 87 5 254 1 88 >; 89 nvmem-cells = <&cpu_leakage>; 90 nvmem-cell-names = "cpu_leakage"; 91 92 opp-408000000 { 93 opp-hz = /bits/ 64 <408000000>; 94 opp-microvolt = <950000 950000 1200000>; 95 opp-microvolt-L0 = <950000 950000 1200000>; 96 opp-microvolt-L1 = <950000 950000 1200000>; 97 clock-latency-ns = <40000>; 98 opp-suspend; 99 }; 100 opp-600000000 { 101 opp-hz = /bits/ 64 <600000000>; 102 opp-microvolt = <975000 975000 1200000>; 103 opp-microvolt-L0 = <975000 975000 1200000>; 104 opp-microvolt-L1 = <975000 975000 1200000>; 105 }; 106 opp-816000000 { 107 opp-hz = /bits/ 64 <816000000>; 108 opp-microvolt = <1000000 1000000 1200000>; 109 opp-microvolt-L0 = <1000000 1000000 1200000>; 110 opp-microvolt-L1 = <1000000 1000000 1200000>; 111 }; 112 opp-1008000000 { 113 opp-hz = /bits/ 64 <1008000000>; 114 opp-microvolt = <1175000 1175000 1200000>; 115 opp-microvolt-L0 = <1175000 1175000 1200000>; 116 opp-microvolt-L1 = <1125000 1125000 1200000>; 117 }; 118 opp-1200000000 { 119 opp-hz = /bits/ 64 <1200000000>; 120 opp-microvolt = <1175000 1175000 1200000>; 121 opp-microvolt-L0 = <1175000 1175000 1200000>; 122 opp-microvolt-L1 = <1125000 1125000 1200000>; 123 }; 124 }; 125 126 amba { 127 compatible = "arm,amba-bus"; 128 #address-cells = <1>; 129 #size-cells = <1>; 130 ranges; 131 132 pdma: pdma@110f0000 { 133 compatible = "arm,pl330", "arm,primecell"; 134 reg = <0x110f0000 0x4000>; 135 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, 136 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>; 137 #dma-cells = <1>; 138 clocks = <&cru ACLK_DMAC>; 139 clock-names = "apb_pclk"; 140 arm,pl330-periph-burst; 141 }; 142 }; 143 144 arm-pmu { 145 compatible = "arm,cortex-a7-pmu"; 146 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>, 147 <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>, 148 <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>, 149 <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>; 150 interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>; 151 }; 152 153 dmc: dmc { 154 compatible = "rockchip,rk3228-dmc", "rockchip,rk322x-dram"; 155 clocks = <&cru SCLK_DDRC>; 156 clock-names = "dmc_clk"; 157 operating-points-v2 = <&dmc_opp_table>; 158 system-status-freq = < 159 /*system status freq(KHz)*/ 160 SYS_STATUS_NORMAL 330000 161 >; 162 dram_freq = <330000000>; 163 rockchip,dram_timing = <&dram_timing>; 164 #cooling-cells = <2>; 165 status = "disabled"; 166 167 ddr_power_model: ddr_power_model { 168 compatible = "ddr_power_model"; 169 dynamic-power-coefficient = <120>; 170 static-power-coefficient = <200>; 171 ts = <32000 4700 (-80) 2>; 172 thermal-zone = "soc-thermal"; 173 }; 174 }; 175 176 dmc_opp_table: dmc-opp-table { 177 compatible = "operating-points-v2"; 178 179 rockchip,leakage-voltage-sel = < 180 1 5 0 181 6 254 1 182 >; 183 nvmem-cells = <&logic_leakage>; 184 nvmem-cell-names = "ddr_leakage"; 185 186 opp-300000000 { 187 opp-hz = /bits/ 64 <300000000>; 188 opp-microvolt = <1050000>; 189 opp-microvolt-L0 = <1050000>; 190 opp-microvolt-L1 = <1000000>; 191 }; 192 opp-330000000 { 193 opp-hz = /bits/ 64 <330000000>; 194 opp-microvolt = <1050000>; 195 opp-microvolt-L0 = <1050000>; 196 opp-microvolt-L1 = <1000000>; 197 }; 198 opp-400000000 { 199 opp-hz = /bits/ 64 <400000000>; 200 opp-microvolt = <1050000>; 201 opp-microvolt-L0 = <1050000>; 202 opp-microvolt-L1 = <1000000>; 203 status = "disabled"; 204 }; 205 opp-600000000 { 206 opp-hz = /bits/ 64 <600000000>; 207 opp-microvolt = <1100000>; 208 opp-microvolt-L0 = <1100000>; 209 opp-microvolt-L1 = <1050000>; 210 status = "disabled"; 211 }; 212 opp-666000000 { 213 opp-hz = /bits/ 64 <666000000>; 214 opp-microvolt = <1150000>; 215 opp-microvolt-L0 = <1150000>; 216 opp-microvolt-L1 = <1100000>; 217 status = "disabled"; 218 }; 219 opp-700000000 { 220 opp-hz = /bits/ 64 <700000000>; 221 opp-microvolt = <1150000>; 222 opp-microvolt-L0 = <1150000>; 223 opp-microvolt-L1 = <1100000>; 224 status = "disabled"; 225 }; 226 opp-786000000 { 227 opp-hz = /bits/ 64 <786000000>; 228 opp-microvolt = <1150000>; 229 opp-microvolt-L0 = <1150000>; 230 opp-microvolt-L1 = <1100000>; 231 status = "disabled"; 232 }; 233 opp-800000000 { 234 opp-hz = /bits/ 64 <800000000>; 235 opp-microvolt = <1150000>; 236 opp-microvolt-L0 = <1150000>; 237 opp-microvolt-L1 = <1100000>; 238 status = "disabled"; 239 }; 240 }; 241 242 firmware { 243 optee: optee { 244 compatible = "linaro,optee-tz"; 245 method = "smc"; 246 }; 247 }; 248 249 timer { 250 compatible = "arm,armv7-timer"; 251 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>, 252 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>, 253 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>, 254 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 255 clock-frequency = <24000000>; 256 }; 257 258 xin24m: oscillator { 259 compatible = "fixed-clock"; 260 clock-frequency = <24000000>; 261 clock-output-names = "xin24m"; 262 #clock-cells = <0>; 263 }; 264 265 i2s1: i2s1@100b0000 { 266 compatible = "rockchip,rk3228-i2s", "rockchip,rk3066-i2s"; 267 reg = <0x100b0000 0x4000>; 268 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>; 269 #address-cells = <1>; 270 #size-cells = <0>; 271 clock-names = "i2s_clk", "i2s_hclk"; 272 clocks = <&cru SCLK_I2S1>, <&cru HCLK_I2S1_8CH>; 273 dmas = <&pdma 14>, <&pdma 15>; 274 dma-names = "tx", "rx"; 275 pinctrl-names = "default"; 276 pinctrl-0 = <&i2s1_bus>; 277 status = "disabled"; 278 }; 279 280 i2s0: i2s0@100c0000 { 281 compatible = "rockchip,rk3228-i2s", "rockchip,rk3066-i2s"; 282 reg = <0x100c0000 0x4000>; 283 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; 284 #address-cells = <1>; 285 #size-cells = <0>; 286 clock-names = "i2s_clk", "i2s_hclk"; 287 clocks = <&cru SCLK_I2S0>, <&cru HCLK_I2S0_8CH>; 288 dmas = <&pdma 11>, <&pdma 12>; 289 dma-names = "tx", "rx"; 290 status = "disabled"; 291 }; 292 293 spdif: spdif@100d0000 { 294 compatible = "rockchip,rk3228-spdif"; 295 reg = <0x100d0000 0x1000>; 296 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>; 297 clocks = <&cru SCLK_SPDIF>, <&cru HCLK_SPDIF_8CH>; 298 clock-names = "mclk", "hclk"; 299 dmas = <&pdma 10>; 300 #dma-cells = <1>; 301 dma-names = "tx"; 302 pinctrl-names = "default"; 303 pinctrl-0 = <&spdif_tx>; 304 status = "disabled"; 305 }; 306 307 i2s2: i2s2@100e0000 { 308 compatible = "rockchip,rk3228-i2s", "rockchip,rk3066-i2s"; 309 reg = <0x100e0000 0x4000>; 310 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>; 311 #address-cells = <1>; 312 #size-cells = <0>; 313 clock-names = "i2s_clk", "i2s_hclk"; 314 clocks = <&cru SCLK_I2S2>, <&cru HCLK_I2S2_2CH>; 315 dmas = <&pdma 0>, <&pdma 1>; 316 dma-names = "tx", "rx"; 317 status = "disabled"; 318 }; 319 320 tsp: tsp@100f0000 { 321 compatible = "rockchip,rk3228-tsp"; 322 reg = <0x100f0000 0x10000>; 323 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>; 324 interrupt-names = "irq_tsp"; 325 clocks = <&cru SCLK_TSP>, <&cru HCLK_TSP>, <&cru SCLK_HSADC>; 326 clock-names = "clk_tsp", "hclk_tsp", "aclk_tsp"; 327 pinctrl-names = "default"; 328 pinctrl-0 = <&tsp_d0 329 &tsp_d1 330 &tsp_d2 331 &tsp_d3 332 &tsp_d4 333 &tsp_d5 334 &tsp_d6 335 &tsp_d7 336 &tsp_sync 337 &tsp_clk 338 &tsp_fail 339 &tsp_valid>; 340 status = "disabled"; 341 }; 342 343 grf: syscon@11000000 { 344 compatible = "rockchip,rk3228-grf", "syscon", "simple-mfd"; 345 reg = <0x11000000 0x1000>; 346 #address-cells = <1>; 347 #size-cells = <1>; 348 349 io_domains: io-domains { 350 compatible = "rockchip,rk322x-io-voltage-domain"; 351 status = "disabled"; 352 }; 353 354 reboot_mode: reboot-mode { 355 compatible = "syscon-reboot-mode"; 356 offset = <0x5c8>; 357 mode-normal = <BOOT_NORMAL>; 358 mode-recovery = <BOOT_RECOVERY>; 359 mode-bootloader = <BOOT_FASTBOOT>; 360 mode-loader = <BOOT_BL_DOWNLOAD>; 361 mode-ums = <BOOT_UMS>; 362 }; 363 364 u2phy0: usb2-phy@760 { 365 compatible = "rockchip,rk3228-usb2phy"; 366 reg = <0x0760 0x0c>; 367 clocks = <&cru SCLK_OTGPHY0>; 368 clock-names = "phyclk"; 369 #clock-cells = <0>; 370 clock-output-names = "usb480m_phy0"; 371 status = "disabled"; 372 373 u2phy0_otg: otg-port { 374 #phy-cells = <0>; 375 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>, 376 <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>, 377 <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>; 378 interrupt-names = "otg-bvalid", "otg-id", 379 "linestate"; 380 status = "disabled"; 381 }; 382 383 u2phy0_host: host-port { 384 #phy-cells = <0>; 385 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>; 386 interrupt-names = "linestate"; 387 status = "disabled"; 388 }; 389 }; 390 391 u2phy1: usb2-phy@800 { 392 compatible = "rockchip,rk3228-usb2phy"; 393 reg = <0x0800 0x0c>; 394 clocks = <&cru SCLK_OTGPHY1>; 395 clock-names = "phyclk"; 396 #clock-cells = <0>; 397 clock-output-names = "usb480m_phy1"; 398 status = "disabled"; 399 400 u2phy1_otg: otg-port { 401 #phy-cells = <0>; 402 interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>; 403 interrupt-names = "linestate"; 404 status = "disabled"; 405 }; 406 407 u2phy1_host: host-port { 408 #phy-cells = <0>; 409 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>; 410 interrupt-names = "linestate"; 411 status = "disabled"; 412 }; 413 }; 414 415 power: power-controller { 416 compatible = "rockchip,rk3228-power-controller"; 417 #power-domain-cells = <1>; 418 #address-cells = <1>; 419 #size-cells = <0>; 420 status = "okay"; 421 422 pd_vpu@RK3228_PD_VPU { 423 reg = <RK3228_PD_VPU>; 424 clocks = <&cru ACLK_VPU>, <&cru HCLK_VPU>; 425 pm_qos = <&qos_vpu>; 426 }; 427 428 pd_rkvdec@RK3228_PD_RKVDEC { 429 reg = <RK3228_PD_RKVDEC>; 430 clocks = <&cru ACLK_RKVDEC>, 431 <&cru HCLK_RKVDEC>, 432 <&cru SCLK_VDEC_CABAC>, 433 <&cru SCLK_VDEC_CORE>; 434 pm_qos = <&qos_rkvdec_r>, <&qos_rkvdec_w>; 435 }; 436 }; 437 }; 438 439 uart0: serial@11010000 { 440 compatible = "snps,dw-apb-uart"; 441 reg = <0x11010000 0x100>; 442 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>; 443 clock-frequency = <24000000>; 444 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>; 445 clock-names = "baudclk", "apb_pclk"; 446 pinctrl-names = "default"; 447 pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>; 448 reg-shift = <2>; 449 reg-io-width = <4>; 450 status = "disabled"; 451 }; 452 453 uart1: serial@11020000 { 454 compatible = "snps,dw-apb-uart"; 455 reg = <0x11020000 0x100>; 456 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>; 457 clock-frequency = <24000000>; 458 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>; 459 clock-names = "baudclk", "apb_pclk"; 460 pinctrl-names = "default"; 461 pinctrl-0 = <&uart1_xfer>; 462 reg-shift = <2>; 463 reg-io-width = <4>; 464 status = "disabled"; 465 }; 466 467 uart2: serial@11030000 { 468 compatible = "snps,dw-apb-uart"; 469 reg = <0x11030000 0x100>; 470 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>; 471 clock-frequency = <24000000>; 472 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>; 473 clock-names = "baudclk", "apb_pclk"; 474 pinctrl-names = "default"; 475 pinctrl-0 = <&uart21_xfer>; 476 reg-shift = <2>; 477 reg-io-width = <4>; 478 status = "disabled"; 479 }; 480 481 efuse: efuse@11040000 { 482 compatible = "rockchip,rk322x-efuse"; 483 reg = <0x11040000 0x20>; 484 #address-cells = <1>; 485 #size-cells = <1>; 486 clocks = <&cru PCLK_EFUSE_256>; 487 clock-names = "pclk_efuse"; 488 489 /* Data cells */ 490 efuse_id: id@7 { 491 reg = <0x7 0x10>; 492 }; 493 cpu_leakage: cpu_leakage@17 { 494 reg = <0x17 0x1>; 495 }; 496 logic_leakage: logic-leakage@19 { 497 reg = <0x19 0x1>; 498 }; 499 hdmi_phy_flag: hdmi_phy_flag@1d { 500 reg = <0x1d 0x1>; 501 bits = <1 1>; 502 }; 503 tve_dac: tve_dac@1d { 504 reg = <0x1d 0x1>; 505 bits = <3 5>; 506 }; 507 }; 508 509 i2c0: i2c@11050000 { 510 compatible = "rockchip,rk3228-i2c"; 511 reg = <0x11050000 0x1000>; 512 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; 513 #address-cells = <1>; 514 #size-cells = <0>; 515 clock-names = "i2c"; 516 clocks = <&cru PCLK_I2C0>; 517 pinctrl-names = "default"; 518 pinctrl-0 = <&i2c0_xfer>; 519 status = "disabled"; 520 }; 521 522 i2c1: i2c@11060000 { 523 compatible = "rockchip,rk3228-i2c"; 524 reg = <0x11060000 0x1000>; 525 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; 526 #address-cells = <1>; 527 #size-cells = <0>; 528 clock-names = "i2c"; 529 clocks = <&cru PCLK_I2C1>; 530 pinctrl-names = "default"; 531 pinctrl-0 = <&i2c1_xfer>; 532 status = "disabled"; 533 }; 534 535 i2c2: i2c@11070000 { 536 compatible = "rockchip,rk3228-i2c"; 537 reg = <0x11070000 0x1000>; 538 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>; 539 #address-cells = <1>; 540 #size-cells = <0>; 541 clock-names = "i2c"; 542 clocks = <&cru PCLK_I2C2>; 543 pinctrl-names = "default"; 544 pinctrl-0 = <&i2c2_xfer>; 545 status = "disabled"; 546 }; 547 548 i2c3: i2c@11080000 { 549 compatible = "rockchip,rk3228-i2c"; 550 reg = <0x11080000 0x1000>; 551 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>; 552 #address-cells = <1>; 553 #size-cells = <0>; 554 clock-names = "i2c"; 555 clocks = <&cru PCLK_I2C3>; 556 pinctrl-names = "default"; 557 pinctrl-0 = <&i2c3_xfer>; 558 status = "disabled"; 559 }; 560 561 spi0: spi@11090000 { 562 compatible = "rockchip,rk3228-spi"; 563 reg = <0x11090000 0x1000>; 564 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>; 565 #address-cells = <1>; 566 #size-cells = <0>; 567 pinctrl-names = "default"; 568 pinctrl-0 = <&spi0_clk &spi0_tx &spi0_rx &spi0_cs0 &spi0_cs1>; 569 clocks = <&cru SCLK_SPI0>, <&cru PCLK_SPI0>; 570 clock-names = "spiclk", "apb_pclk"; 571 status = "disabled"; 572 }; 573 574 wdt: watchdog@110a0000 { 575 compatible = "rockchip,rk322x-wdt", "snps,dw-wdt"; 576 reg = <0x110a0000 0x100>; 577 clocks = <&cru PCLK_CPU>; 578 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>; 579 status = "disabled"; 580 }; 581 582 pwm0: pwm@110b0000 { 583 compatible = "rockchip,rk3288-pwm"; 584 reg = <0x110b0000 0x10>; 585 #pwm-cells = <3>; 586 clocks = <&cru PCLK_PWM>; 587 clock-names = "pwm"; 588 pinctrl-names = "active"; 589 pinctrl-0 = <&pwm0_pin>; 590 status = "disabled"; 591 }; 592 593 pwm1: pwm@110b0010 { 594 compatible = "rockchip,rk3288-pwm"; 595 reg = <0x110b0010 0x10>; 596 #pwm-cells = <3>; 597 clocks = <&cru PCLK_PWM>; 598 clock-names = "pwm"; 599 pinctrl-names = "active"; 600 pinctrl-0 = <&pwm1_pin>; 601 status = "disabled"; 602 }; 603 604 pwm2: pwm@110b0020 { 605 compatible = "rockchip,rk3288-pwm"; 606 reg = <0x110b0020 0x10>; 607 #pwm-cells = <3>; 608 clocks = <&cru PCLK_PWM>; 609 clock-names = "pwm"; 610 pinctrl-names = "active"; 611 pinctrl-0 = <&pwm2_pin>; 612 status = "disabled"; 613 }; 614 615 pwm3: pwm@110b0030 { 616 compatible = "rockchip,rk3288-pwm"; 617 reg = <0x110b0030 0x10>; 618 interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>; 619 #pwm-cells = <3>; 620 clocks = <&cru PCLK_PWM>; 621 clock-names = "pwm"; 622 pinctrl-names = "active"; 623 pinctrl-0 = <&pwm3_pin>; 624 status = "disabled"; 625 }; 626 627 timer: timer@110c0000 { 628 compatible = "rockchip,rk3288-timer"; 629 reg = <0x110c0000 0x20>; 630 interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>; 631 clocks = <&xin24m>, <&cru PCLK_TIMER>; 632 clock-names = "timer", "pclk"; 633 }; 634 635 cru: clock-controller@110e0000 { 636 compatible = "rockchip,rk3228-cru"; 637 reg = <0x110e0000 0x1000>; 638 rockchip,grf = <&grf>; 639 #clock-cells = <1>; 640 #reset-cells = <1>; 641 assigned-clocks = 642 <&cru PLL_GPLL>, <&cru ARMCLK>, 643 <&cru PLL_CPLL>, <&cru ACLK_PERI>, 644 <&cru HCLK_PERI>, <&cru PCLK_PERI>, 645 <&cru ACLK_CPU>, <&cru HCLK_CPU>, 646 <&cru PCLK_CPU>, <&cru ACLK_VOP>; 647 assigned-clock-rates = 648 <1200000000>, <816000000>, 649 <500000000>, <150000000>, 650 <150000000>, <75000000>, 651 <150000000>, <150000000>, 652 <75000000>, <400000000>; 653 }; 654 655 thermal_zones: thermal-zones { 656 soc_thermal: soc-thermal { 657 polling-delay-passive = <100>; /* milliseconds */ 658 polling-delay = <5000>; /* milliseconds */ 659 sustainable-power = <1200>; /* milliwatts */ 660 661 thermal-sensors = <&tsadc 0>; 662 663 trips { 664 threshold: trip-point@0 { 665 temperature = <70000>; /* millicelsius */ 666 hysteresis = <2000>; /* millicelsius */ 667 type = "passive"; 668 }; 669 target: trip-point@1 { 670 temperature = <85000>; /* millicelsius */ 671 hysteresis = <2000>; /* millicelsius */ 672 type = "passive"; 673 }; 674 soc_crit: soc-crit { 675 temperature = <115000>; /* millicelsius */ 676 hysteresis = <2000>; /* millicelsius */ 677 type = "critical"; 678 }; 679 }; 680 681 cooling-maps { 682 map0 { 683 trip = <&target>; 684 cooling-device = 685 <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 686 contribution = <1024>; 687 }; 688 map1 { 689 trip = <&target>; 690 cooling-device = 691 <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 692 contribution = <1024>; 693 }; 694 map2 { 695 trip = <&target>; 696 cooling-device = 697 <&dmc THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 698 contribution = <1024>; 699 }; 700 map3 { 701 trip = <&target>; 702 cooling-device = 703 <&rkvdec THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 704 contribution = <1024>; 705 }; 706 }; 707 }; 708 }; 709 710 tsadc: tsadc@11150000 { 711 compatible = "rockchip,rk3228-tsadc"; 712 reg = <0x11150000 0x100>; 713 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>; 714 clocks = <&cru SCLK_TSADC>, <&cru PCLK_TSADC>; 715 clock-names = "tsadc", "apb_pclk"; 716 assigned-clocks = <&cru SCLK_TSADC>; 717 assigned-clock-rates = <32768>; 718 resets = <&cru SRST_TSADC>; 719 reset-names = "tsadc-apb"; 720 pinctrl-names = "gpio", "otpout"; 721 pinctrl-0 = <&otp_gpio>; 722 pinctrl-1 = <&otp_out>; 723 #thermal-sensor-cells = <0>; 724 rockchip,hw-tshut-temp = <120000>; 725 status = "disabled"; 726 }; 727 728 codec: codec@12010000 { 729 compatible = "rockchip,rk3228-codec"; 730 reg = <0x12010000 0x1000>; 731 clocks = <&cru SCLK_I2S_OUT>, <&cru PCLK_ACODECPHY>, <&cru SCLK_I2S1>; 732 clock-names = "mclk", "pclk", "sclk"; 733 spk-en-gpio = <&gpio1 RK_PA3 GPIO_ACTIVE_HIGH>; 734 status = "disabled"; 735 }; 736 737 hdmi_phy: hdmi-phy@12030000 { 738 compatible = "rockchip,rk3228-hdmi-phy"; 739 reg = <0x12030000 0x10000>; 740 #phy-cells = <0>; 741 clocks = <&cru PCLK_HDMI_PHY>, <&xin24m>; 742 clock-names = "sysclk", "refclk"; 743 #clock-cells = <0>; 744 clock-output-names = "hdmiphy_phy"; 745 nvmem-cells = <&hdmi_phy_flag>; 746 nvmem-cell-names = "hdmi_phy_flag"; 747 rockchip,phy-table = 748 <190000000 0xaa 0x00 0x44 0x44 0x00 0x00 0x00 0x00 0x00 749 0x00 0x00 0x00 0x00 0x00>; 750 status = "disabled"; 751 }; 752 753 gpu: gpu@0x20001000 { 754 compatible = "arm,mali400"; 755 reg = <0x20001000 0x200>, 756 <0x20000000 0x100>, 757 <0x20003000 0x100>, 758 <0x20008000 0x1100>, 759 <0x20004000 0x100>, 760 <0x2000A000 0x1100>, 761 <0x20005000 0x100>; 762 763 reg-names = "Mali_L2", 764 "Mali_GP", 765 "Mali_GP_MMU", 766 "Mali_PP0", 767 "Mali_PP0_MMU", 768 "Mali_PP1", 769 "Mali_PP1_MMU"; 770 771 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>, 772 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>, 773 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, 774 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>, 775 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, 776 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; 777 778 interrupt-names = "Mali_GP_IRQ", 779 "Mali_GP_MMU_IRQ", 780 "Mali_PP0_IRQ", 781 "Mali_PP0_MMU_IRQ", 782 "Mali_PP1_IRQ", 783 "Mali_PP1_MMU_IRQ"; 784 clocks = <&cru ACLK_GPU>; 785 #cooling-cells = <2>; /* min followed by max */ 786 clock-names = "clk_mali"; 787 operating-points-v2 = <&gpu_opp_table>; 788 status = "disabled"; 789 790 gpu_power_model: power_model { 791 compatible = "arm,mali-simple-power-model"; 792 voltage = <900>; 793 frequency = <500>; 794 static-power = <300>; 795 dynamic-power = <396>; 796 ts = <32000 4700 (-80) 2>; 797 thermal-zone = "soc-thermal"; 798 }; 799 }; 800 801 gpu_opp_table: opp-table2 { 802 compatible = "operating-points-v2"; 803 804 rockchip,leakage-voltage-sel = < 805 1 5 0 806 6 254 1 807 >; 808 nvmem-cells = <&logic_leakage>; 809 nvmem-cell-names = "gpu_leakage"; 810 811 opp-200000000 { 812 opp-hz = /bits/ 64 <200000000>; 813 opp-microvolt = <1050000>; 814 opp-microvolt-L0 = <1050000>; 815 opp-microvolt-L1 = <1000000>; 816 }; 817 opp-300000000 { 818 opp-hz = /bits/ 64 <300000000>; 819 opp-microvolt = <1050000>; 820 opp-microvolt-L0 = <1050000>; 821 opp-microvolt-L1 = <1000000>; 822 }; 823 opp-400000000 { 824 opp-hz = /bits/ 64 <400000000>; 825 opp-microvolt = <1125000>; 826 opp-microvolt-L0 = <1125000>; 827 opp-microvolt-L1 = <1100000>; 828 }; 829 }; 830 831 vpu_service: vpu-service@20020000 { 832 compatible = "rockchip,vpu_service"; 833 reg = <0x20020000 0x800>; 834 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>, 835 <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 836 interrupt-names = "irq_dec", "irq_enc"; 837 resets = <&cru SRST_VPU_A>, <&cru SRST_VPU_H>; 838 reset-names = "video_a", "video_h"; 839 clocks = <&cru ACLK_VPU>, <&cru HCLK_VPU>; 840 clock-names = "aclk_vcodec", "hclk_vcodec"; 841 power-domains = <&power RK3228_PD_VPU>; 842 rockchip,grf = <&grf>; 843 iommus = <&vpu_mmu>; 844 allocator = <1>; 845 status = "disabled"; 846 }; 847 848 vpu_mmu: iommu@20020800 { 849 compatible = "rockchip,iommu"; 850 reg = <0x20020800 0x40>; 851 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 852 interrupt-names = "vpu_mmu"; 853 clock-names = "aclk", "iface"; 854 clocks = <&cru ACLK_VPU>, <&cru HCLK_VPU>; 855 power-domains = <&power RK3228_PD_VPU>; 856 #iommu-cells = <0>; 857 status = "disabled"; 858 }; 859 860 rkvdec: rkvdec@20030000 { 861 compatible = "rockchip,rkvdec"; 862 reg = <0x20030000 0x400>; 863 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; 864 interrupt-names = "irq_dec"; 865 clocks = <&cru ACLK_RKVDEC>, <&cru HCLK_RKVDEC>, 866 <&cru SCLK_VDEC_CABAC>, <&cru SCLK_VDEC_CORE>; 867 clock-names = "aclk_vcodec", "hclk_vcodec", "clk_cabac", 868 "clk_core"; 869 resets = <&cru SRST_RKVDEC_A>, <&cru SRST_RKVDEC_H>, 870 <&cru SRST_RKVDEC_NOC_A>, <&cru SRST_RKVDEC_NOC_H>, 871 <&cru SRST_RKVDEC_CABAC>, <&cru SRST_RKVDEC_CORE>; 872 reset-names = "video_a", "video_h", "niu_a", "niu_h", 873 "video_cabac", "video_core"; 874 power-domains = <&power RK3228_PD_RKVDEC>; 875 operating-points-v2 = <&rkvdec_opp_table>; 876 #cooling-cells = <2>; 877 rockchip,grf = <&grf>; 878 iommus = <&rkvdec_mmu>; 879 allocator = <1>; 880 status = "disabled"; 881 882 vcodec_power_model: vcodec_power_model { 883 compatible = "vcodec_power_model"; 884 dynamic-power-coefficient = <120>; 885 static-power-coefficient = <200>; 886 ts = <32000 4700 (-80) 2>; 887 thermal-zone = "soc-thermal"; 888 }; 889 }; 890 891 rkvdec_opp_table: rkvdec-opp-table { 892 compatible = "operating-points-v2"; 893 894 rockchip,leakage-voltage-sel = < 895 1 5 0 896 6 254 1 897 >; 898 nvmem-cells = <&logic_leakage>; 899 nvmem-cell-names = "rkvdec_leakage"; 900 901 opp-100000000 { 902 opp-hz = /bits/ 64 <100000000>; 903 opp-microvolt = <1050000>; 904 opp-microvolt-L0 = <1050000>; 905 opp-microvolt-L1 = <1000000>; 906 }; 907 opp-200000000 { 908 opp-hz = /bits/ 64 <200000000>; 909 opp-microvolt = <1050000>; 910 opp-microvolt-L0 = <1050000>; 911 opp-microvolt-L1 = <1000000>; 912 }; 913 opp-500000000 { 914 opp-hz = /bits/ 64 <500000000>; 915 opp-microvolt = <1050000>; 916 opp-microvolt-L0 = <1050000>; 917 opp-microvolt-L1 = <1000000>; 918 }; 919 }; 920 921 rkvdec_mmu: iommu@20030480 { 922 compatible = "rockchip,iommu"; 923 reg = <0x20030480 0x40>, <0x200304c0 0x40>; 924 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>; 925 interrupt-names = "rkvdec_mmu"; 926 clocks = <&cru ACLK_RKVDEC>, <&cru HCLK_RKVDEC>; 927 clock-names = "aclk", "iface"; 928 power-domains = <&power RK3228_PD_RKVDEC>; 929 #iommu-cells = <0>; 930 status = "disabled"; 931 }; 932 933 vop: vop@20050000 { 934 compatible = "rockchip,rk322x-vop"; 935 reg = <0x20050000 0x1ffc>; 936 reg-names = "regs"; 937 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; 938 clocks = <&cru ACLK_VOP>, <&cru DCLK_VOP>, <&cru HCLK_VOP>; 939 clock-names = "aclk_vop", "dclk_vop", "hclk_vop"; 940 resets = <&cru SRST_VOP_A>, <&cru SRST_VOP_H>, <&cru SRST_VOP_D>; 941 reset-names = "axi", "ahb", "dclk"; 942 iommus = <&vop_mmu>; 943 status = "disabled"; 944 945 vop_out: port { 946 #address-cells = <1>; 947 #size-cells = <0>; 948 949 vop_out_hdmi: endpoint@0 { 950 reg = <0>; 951 remote-endpoint = <&hdmi_in_vop>; 952 }; 953 954 vop_out_tve: endpoint@1 { 955 reg = <1>; 956 remote-endpoint = <&tve_in_vop>; 957 }; 958 }; 959 }; 960 961 vop_mmu: iommu@20050300 { 962 compatible = "rockchip,iommu"; 963 reg = <0x20053f00 0x100>; 964 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; 965 interrupt-names = "vop_mmu"; 966 clocks = <&cru ACLK_VOP>, <&cru HCLK_VOP>; 967 clock-names = "aclk", "iface"; 968 #iommu-cells = <0>; 969 status = "disabled"; 970 }; 971 972 rk_rga: rk_rga@20060000 { 973 compatible = "rockchip,rga2"; 974 reg = <0x20060000 0x1000>; 975 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; 976 clocks = <&cru ACLK_RGA>, <&cru HCLK_RGA>, <&cru SCLK_RGA>; 977 clock-names = "aclk_rga", "hclk_rga", "clk_rga"; 978 dma-coherent; 979 status = "disabled"; 980 }; 981 982 iep: iep@20070000 { 983 compatible = "rockchip,iep"; 984 iommu_enabled = <1>; 985 iommus = <&iep_mmu>; 986 reg = <0x20070000 0x800>; 987 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; 988 clocks = <&cru ACLK_IEP>, <&cru HCLK_IEP>; 989 clock-names = "aclk_iep", "hclk_iep"; 990 version = <3>; 991 allocator = <1>; 992 status = "disabled"; 993 }; 994 995 iep_mmu: iommu@20070800 { 996 compatible = "rockchip,iommu"; 997 reg = <0x20070800 0x40>; 998 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; 999 interrupt-names = "iep_mmu"; 1000 #iommu-cells = <0>; 1001 status = "disabled"; 1002 }; 1003 1004 display_subsystem: display-subsystem { 1005 compatible = "rockchip,display-subsystem"; 1006 ports = <&vop_out>; 1007 }; 1008 1009 hdmi: hdmi@200a0000 { 1010 compatible = "rockchip,rk3228-dw-hdmi"; 1011 reg = <0x200a0000 0x20000>; 1012 reg-io-width = <4>; 1013 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>, 1014 <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>; 1015 clocks = <&cru SCLK_HDMI_HDCP>, <&cru PCLK_HDMI_CTRL>, 1016 <&cru SCLK_HDMI_CEC>; 1017 clock-names = "isfr", "iahb", "cec"; 1018 pinctrl-names = "default"; 1019 pinctrl-0 = <&hdmii2c_xfer &hdmi_hpd &hdmi_cec>; 1020 resets = <&cru SRST_HDMI_P>; 1021 reset-names = "hdmi"; 1022 phys = <&hdmi_phy>; 1023 phy-names = "hdmi_phy"; 1024 rockchip,grf = <&grf>; 1025 status = "disabled"; 1026 1027 ports { 1028 hdmi_in: port { 1029 #address-cells = <1>; 1030 #size-cells = <0>; 1031 hdmi_in_vop: endpoint@0 { 1032 reg = <0>; 1033 remote-endpoint = <&vop_out_hdmi>; 1034 }; 1035 }; 1036 }; 1037 }; 1038 1039 tve: tve@20053e00 { 1040 compatible = "rockchip,rk3328-tve"; 1041 reg = <0x20053e00 0x100>, 1042 <0x12020000 0x10000>; 1043 rockchip,saturation = <0x00305b46>; 1044 rockchip,brightcontrast = <0x00009900>; 1045 rockchip,adjtiming = <0xd6c00880>; 1046 rockchip,lumafilter0 = <0x02ff0001>; 1047 rockchip,lumafilter1 = <0xf40200fe>; 1048 rockchip,lumafilter2 = <0xf332d910>; 1049 rockchip,daclevel = <0x15>; 1050 rockchip,dac1level = <0x7>; 1051 nvmem-cells = <&tve_dac>; 1052 nvmem-cell-names = "tve_dac_adj"; 1053 status = "disabled"; 1054 1055 ports { 1056 tve_in: port { 1057 #address-cells = <1>; 1058 #size-cells = <0>; 1059 tve_in_vop: endpoint@0 { 1060 reg = <0>; 1061 remote-endpoint = <&vop_out_tve>; 1062 }; 1063 }; 1064 }; 1065 }; 1066 1067 sdmmc: dwmmc@30000000 { 1068 compatible = "rockchip,rk3228-dw-mshc", "rockchip,rk3288-dw-mshc"; 1069 reg = <0x30000000 0x4000>; 1070 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 1071 clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>, 1072 <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>; 1073 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; 1074 fifo-depth = <0x100>; 1075 pinctrl-names = "default"; 1076 pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_bus4>; 1077 status = "disabled"; 1078 }; 1079 1080 sdio: dwmmc@30010000 { 1081 compatible = "rockchip,rk3228-dw-mshc", "rockchip,rk3288-dw-mshc"; 1082 reg = <0x30010000 0x4000>; 1083 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 1084 clocks = <&cru HCLK_SDIO>, <&cru SCLK_SDIO>, 1085 <&cru SCLK_SDIO_DRV>, <&cru SCLK_SDIO_SAMPLE>; 1086 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; 1087 fifo-depth = <0x100>; 1088 pinctrl-names = "default"; 1089 pinctrl-0 = <&sdio_clk &sdio_cmd &sdio_bus4>; 1090 status = "disabled"; 1091 }; 1092 1093 emmc: dwmmc@30020000 { 1094 compatible = "rockchip,rk3228-dw-mshc", "rockchip,rk3288-dw-mshc"; 1095 reg = <0x30020000 0x4000>; 1096 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 1097 clock-frequency = <37500000>; 1098 clock-freq-min-max = <400000 37500000>; 1099 clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>, 1100 <&cru SCLK_EMMC_DRV>, <&cru SCLK_EMMC_SAMPLE>; 1101 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; 1102 bus-width = <8>; 1103 default-sample-phase = <158>; 1104 num-slots = <1>; 1105 fifo-depth = <0x100>; 1106 pinctrl-names = "default"; 1107 pinctrl-0 = <&emmc_clk &emmc_cmd &emmc_bus8>; 1108 status = "disabled"; 1109 }; 1110 1111 nandc: nandc@30030000 { 1112 compatible = "rockchip,rk-nandc"; 1113 reg = <0x30030000 0x4000>; 1114 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>; 1115 nandc_id = <0>; 1116 clocks = <&cru SCLK_NANDC>, <&cru HCLK_NANDC>; 1117 clock-names = "clk_nandc", "hclk_nandc"; 1118 status = "disabled"; 1119 }; 1120 1121 usb_otg: usb@30040000 { 1122 compatible = "rockchip,rk322x-usb", "rockchip,rk3066-usb", 1123 "snps,dwc2"; 1124 reg = <0x30040000 0x40000>; 1125 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>; 1126 clocks = <&cru HCLK_OTG>; 1127 clock-names = "otg"; 1128 dr_mode = "otg"; 1129 g-np-tx-fifo-size = <16>; 1130 g-rx-fifo-size = <280>; 1131 g-tx-fifo-size = <256 128 128 64 32 16>; 1132 g-use-dma; 1133 phys = <&u2phy0_otg>; 1134 phy-names = "usb2-phy"; 1135 status = "disabled"; 1136 }; 1137 1138 usb_host0_ehci: usb@30080000 { 1139 compatible = "generic-ehci"; 1140 reg = <0x30080000 0x20000>; 1141 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>; 1142 clocks = <&cru HCLK_HOST0>, <&u2phy0>; 1143 clock-names = "usbhost", "utmi"; 1144 phys = <&u2phy0_host>; 1145 phy-names = "usb"; 1146 status = "disabled"; 1147 }; 1148 1149 usb_host0_ohci: usb@300a0000 { 1150 compatible = "generic-ohci"; 1151 reg = <0x300a0000 0x20000>; 1152 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>; 1153 clocks = <&cru HCLK_HOST0>, <&u2phy0>; 1154 clock-names = "usbhost", "utmi"; 1155 phys = <&u2phy0_host>; 1156 phy-names = "usb"; 1157 status = "disabled"; 1158 }; 1159 1160 usb_host1_ehci: usb@300c0000 { 1161 compatible = "generic-ehci"; 1162 reg = <0x300c0000 0x20000>; 1163 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>; 1164 clocks = <&cru HCLK_HOST1>, <&u2phy1>; 1165 clock-names = "usbhost", "utmi"; 1166 phys = <&u2phy1_host>; 1167 phy-names = "usb"; 1168 status = "disabled"; 1169 }; 1170 1171 usb_host1_ohci: usb@300e0000 { 1172 compatible = "generic-ohci"; 1173 reg = <0x300e0000 0x20000>; 1174 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>; 1175 clocks = <&cru HCLK_HOST1>, <&u2phy1>; 1176 clock-names = "usbhost", "utmi"; 1177 phys = <&u2phy1_host>; 1178 phy-names = "usb"; 1179 status = "disabled"; 1180 }; 1181 1182 usb_host2_ehci: usb@30100000 { 1183 compatible = "generic-ehci"; 1184 reg = <0x30100000 0x20000>; 1185 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>; 1186 clocks = <&cru HCLK_HOST2>, <&u2phy1>; 1187 phys = <&u2phy1_otg>; 1188 phy-names = "usb"; 1189 clock-names = "usbhost", "utmi"; 1190 status = "disabled"; 1191 }; 1192 1193 usb_host2_ohci: usb@30120000 { 1194 compatible = "generic-ohci"; 1195 reg = <0x30120000 0x20000>; 1196 interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>; 1197 clocks = <&cru HCLK_HOST2>, <&u2phy1>; 1198 clock-names = "usbhost", "utmi"; 1199 phys = <&u2phy1_otg>; 1200 phy-names = "usb"; 1201 status = "disabled"; 1202 }; 1203 1204 gmac: ethernet@30200000 { 1205 compatible = "rockchip,rk3228-gmac"; 1206 reg = <0x30200000 0x10000>; 1207 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>; 1208 interrupt-names = "macirq"; 1209 clocks = <&cru SCLK_MAC>, <&cru SCLK_MAC_RX>, 1210 <&cru SCLK_MAC_TX>, <&cru SCLK_MAC_REF>, 1211 <&cru SCLK_MAC_REFOUT>, <&cru ACLK_GMAC>, 1212 <&cru PCLK_GMAC>, <&cru SCLK_MAC_PHY>; 1213 clock-names = "stmmaceth", "mac_clk_rx", 1214 "mac_clk_tx", "clk_mac_ref", 1215 "clk_mac_refout", "aclk_mac", 1216 "pclk_mac", "clk_macphy"; 1217 resets = <&cru SRST_GMAC>, <&cru SRST_MACPHY>; 1218 reset-names = "stmmaceth", "mac-phy"; 1219 rockchip,grf = <&grf>; 1220 status = "disabled"; 1221 }; 1222 1223 qos_vpu: qos@31040000 { 1224 compatible = "syscon"; 1225 reg = <0x31040000 0x20>; 1226 }; 1227 1228 qos_rkvdec_r: qos@31070000 { 1229 compatible = "syscon"; 1230 reg = <0x31070000 0x20>; 1231 }; 1232 1233 qos_rkvdec_w: qos@31070080 { 1234 compatible = "syscon"; 1235 reg = <0x31070080 0x20>; 1236 }; 1237 1238 gic: interrupt-controller@32010000 { 1239 compatible = "arm,gic-400"; 1240 interrupt-controller; 1241 #interrupt-cells = <3>; 1242 #address-cells = <0>; 1243 1244 reg = <0x32011000 0x1000>, 1245 <0x32012000 0x2000>, 1246 <0x32014000 0x2000>, 1247 <0x32016000 0x2000>; 1248 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 1249 }; 1250 1251 pinctrl: pinctrl { 1252 compatible = "rockchip,rk3228-pinctrl"; 1253 rockchip,grf = <&grf>; 1254 #address-cells = <1>; 1255 #size-cells = <1>; 1256 ranges; 1257 1258 gpio0: gpio0@11110000 { 1259 compatible = "rockchip,gpio-bank"; 1260 reg = <0x11110000 0x100>; 1261 interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>; 1262 clocks = <&cru PCLK_GPIO0>; 1263 1264 gpio-controller; 1265 #gpio-cells = <2>; 1266 1267 interrupt-controller; 1268 #interrupt-cells = <2>; 1269 }; 1270 1271 gpio1: gpio1@11120000 { 1272 compatible = "rockchip,gpio-bank"; 1273 reg = <0x11120000 0x100>; 1274 interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>; 1275 clocks = <&cru PCLK_GPIO1>; 1276 1277 gpio-controller; 1278 #gpio-cells = <2>; 1279 1280 interrupt-controller; 1281 #interrupt-cells = <2>; 1282 }; 1283 1284 gpio2: gpio2@11130000 { 1285 compatible = "rockchip,gpio-bank"; 1286 reg = <0x11130000 0x100>; 1287 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>; 1288 clocks = <&cru PCLK_GPIO2>; 1289 1290 gpio-controller; 1291 #gpio-cells = <2>; 1292 1293 interrupt-controller; 1294 #interrupt-cells = <2>; 1295 }; 1296 1297 gpio3: gpio3@11140000 { 1298 compatible = "rockchip,gpio-bank"; 1299 reg = <0x11140000 0x100>; 1300 interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>; 1301 clocks = <&cru PCLK_GPIO3>; 1302 1303 gpio-controller; 1304 #gpio-cells = <2>; 1305 1306 interrupt-controller; 1307 #interrupt-cells = <2>; 1308 }; 1309 1310 pcfg_pull_up: pcfg-pull-up { 1311 bias-pull-up; 1312 }; 1313 1314 pcfg_pull_down: pcfg-pull-down { 1315 bias-pull-down; 1316 }; 1317 1318 pcfg_pull_none: pcfg-pull-none { 1319 bias-disable; 1320 }; 1321 1322 pcfg_pull_none_drv_12ma: pcfg-pull-none-drv-12ma { 1323 drive-strength = <12>; 1324 }; 1325 1326 sdmmc { 1327 sdmmc_clk: sdmmc-clk { 1328 rockchip,pins = <1 RK_PC0 1 &pcfg_pull_none_drv_12ma>; 1329 }; 1330 1331 sdmmc_cmd: sdmmc-cmd { 1332 rockchip,pins = <1 RK_PB7 1 &pcfg_pull_none_drv_12ma>; 1333 }; 1334 1335 sdmmc_bus4: sdmmc-bus4 { 1336 rockchip,pins = <1 RK_PC2 1 &pcfg_pull_none_drv_12ma>, 1337 <1 RK_PC3 1 &pcfg_pull_none_drv_12ma>, 1338 <1 RK_PC4 1 &pcfg_pull_none_drv_12ma>, 1339 <1 RK_PC5 1 &pcfg_pull_none_drv_12ma>; 1340 }; 1341 }; 1342 1343 sdio { 1344 sdio_clk: sdio-clk { 1345 rockchip,pins = <3 RK_PA0 1 &pcfg_pull_none_drv_12ma>; 1346 }; 1347 1348 sdio_cmd: sdio-cmd { 1349 rockchip,pins = <3 RK_PA1 1 &pcfg_pull_none_drv_12ma>; 1350 }; 1351 1352 sdio_bus4: sdio-bus4 { 1353 rockchip,pins = <3 RK_PA2 1 &pcfg_pull_none_drv_12ma>, 1354 <3 RK_PA3 1 &pcfg_pull_none_drv_12ma>, 1355 <3 RK_PA4 1 &pcfg_pull_none_drv_12ma>, 1356 <3 RK_PA5 1 &pcfg_pull_none_drv_12ma>; 1357 }; 1358 }; 1359 1360 emmc { 1361 emmc_clk: emmc-clk { 1362 rockchip,pins = <2 RK_PA7 2 &pcfg_pull_none>; 1363 }; 1364 1365 emmc_cmd: emmc-cmd { 1366 rockchip,pins = <1 RK_PC6 2 &pcfg_pull_none>; 1367 }; 1368 1369 emmc_bus8: emmc-bus8 { 1370 rockchip,pins = <1 RK_PD0 2 &pcfg_pull_none>, 1371 <1 RK_PD1 2 &pcfg_pull_none>, 1372 <1 RK_PD2 2 &pcfg_pull_none>, 1373 <1 RK_PD3 2 &pcfg_pull_none>, 1374 <1 RK_PD4 2 &pcfg_pull_none>, 1375 <1 RK_PD5 2 &pcfg_pull_none>, 1376 <1 RK_PD6 2 &pcfg_pull_none>, 1377 <1 RK_PD7 2 &pcfg_pull_none>; 1378 }; 1379 }; 1380 1381 gmac { 1382 rgmii_pins: rgmii-pins { 1383 rockchip,pins = <2 RK_PB6 1 &pcfg_pull_none>, 1384 <2 RK_PB4 1 &pcfg_pull_none>, 1385 <2 RK_PD1 1 &pcfg_pull_none>, 1386 <2 RK_PC3 1 &pcfg_pull_none_drv_12ma>, 1387 <2 RK_PC2 1 &pcfg_pull_none_drv_12ma>, 1388 <2 RK_PC6 1 &pcfg_pull_none_drv_12ma>, 1389 <2 RK_PC7 1 &pcfg_pull_none_drv_12ma>, 1390 <2 RK_PB1 1 &pcfg_pull_none_drv_12ma>, 1391 <2 RK_PB5 1 &pcfg_pull_none_drv_12ma>, 1392 <2 RK_PC1 1 &pcfg_pull_none>, 1393 <2 RK_PC0 1 &pcfg_pull_none>, 1394 <2 RK_PC5 2 &pcfg_pull_none>, 1395 <2 RK_PC4 2 &pcfg_pull_none>, 1396 <2 RK_PB3 1 &pcfg_pull_none>, 1397 <2 RK_PB0 1 &pcfg_pull_none>; 1398 }; 1399 1400 rmii_pins: rmii-pins { 1401 rockchip,pins = <2 RK_PB6 1 &pcfg_pull_none>, 1402 <2 RK_PB4 1 &pcfg_pull_none>, 1403 <2 RK_PD1 1 &pcfg_pull_none>, 1404 <2 RK_PC3 1 &pcfg_pull_none_drv_12ma>, 1405 <2 RK_PC2 1 &pcfg_pull_none_drv_12ma>, 1406 <2 RK_PB5 1 &pcfg_pull_none_drv_12ma>, 1407 <2 RK_PC1 1 &pcfg_pull_none>, 1408 <2 RK_PC0 1 &pcfg_pull_none>, 1409 <2 RK_PB0 1 &pcfg_pull_none>, 1410 <2 RK_PB7 1 &pcfg_pull_none>; 1411 }; 1412 1413 phy_pins: phy-pins { 1414 rockchip,pins = <2 RK_PB6 2 &pcfg_pull_none>, 1415 <2 RK_PB0 2 &pcfg_pull_none>; 1416 }; 1417 }; 1418 1419 hdmi { 1420 hdmi_hpd: hdmi-hpd { 1421 rockchip,pins = <0 RK_PB7 1 &pcfg_pull_down>; 1422 }; 1423 1424 hdmii2c_xfer: hdmii2c-xfer { 1425 rockchip,pins = <0 RK_PA6 2 &pcfg_pull_none>, 1426 <0 RK_PA7 2 &pcfg_pull_none>; 1427 }; 1428 1429 hdmi_cec: hdmi-cec { 1430 rockchip,pins = <0 RK_PC4 1 &pcfg_pull_none>; 1431 }; 1432 }; 1433 1434 i2c0 { 1435 i2c0_xfer: i2c0-xfer { 1436 rockchip,pins = <0 RK_PA0 1 &pcfg_pull_none>, 1437 <0 RK_PA1 1 &pcfg_pull_none>; 1438 }; 1439 }; 1440 1441 i2c1 { 1442 i2c1_xfer: i2c1-xfer { 1443 rockchip,pins = <0 RK_PA2 1 &pcfg_pull_none>, 1444 <0 RK_PA3 1 &pcfg_pull_none>; 1445 }; 1446 }; 1447 1448 i2c2 { 1449 i2c2_xfer: i2c2-xfer { 1450 rockchip,pins = <2 RK_PC4 1 &pcfg_pull_none>, 1451 <2 RK_PC5 1 &pcfg_pull_none>; 1452 }; 1453 }; 1454 1455 i2c3 { 1456 i2c3_xfer: i2c3-xfer { 1457 rockchip,pins = <0 RK_PA6 1 &pcfg_pull_none>, 1458 <0 RK_PA7 1 &pcfg_pull_none>; 1459 }; 1460 }; 1461 1462 tsp { 1463 tsp_d0: tsp-d0 { 1464 rockchip,pins = <2 RK_PC3 2 &pcfg_pull_none>; 1465 }; 1466 tsp_d1: tsp-d1 { 1467 rockchip,pins = <2 RK_PC2 2 &pcfg_pull_none>; 1468 }; 1469 tsp_d2: tsp-d2 { 1470 rockchip,pins = <2 RK_PC1 2 &pcfg_pull_none>; 1471 }; 1472 tsp_d3: tsp-d3 { 1473 rockchip,pins = <2 RK_PC0 2 &pcfg_pull_none>; 1474 }; 1475 tsp_d4: tsp-d4 { 1476 rockchip,pins = <2 RK_PD1 2 &pcfg_pull_none>; 1477 }; 1478 tsp_d5: tsp-d5 { 1479 rockchip,pins = <2 RK_PD0 2 &pcfg_pull_none>; 1480 }; 1481 tsp_d6: tsp-d6 { 1482 rockchip,pins = <2 RK_PB7 2 &pcfg_pull_none>; 1483 }; 1484 tsp_d7: tsp-d7 { 1485 rockchip,pins = <2 RK_PB5 2 &pcfg_pull_none>; 1486 }; 1487 tsp_sync: tsp-sync { 1488 rockchip,pins = <2 RK_PB4 2 &pcfg_pull_none>; 1489 }; 1490 tsp_clk: tsp-clk { 1491 rockchip,pins = <2 RK_PB3 2 &pcfg_pull_none>; 1492 }; 1493 tsp_fail: tsp-fail { 1494 rockchip,pins = <2 RK_PB2 2 &pcfg_pull_none>; 1495 }; 1496 tsp_valid: tsp-valid { 1497 rockchip,pins = <2 RK_PB1 2 &pcfg_pull_none>; 1498 }; 1499 }; 1500 1501 spi-0 { 1502 spi0_clk: spi0-clk { 1503 rockchip,pins = <0 RK_PB1 2 &pcfg_pull_up>; 1504 }; 1505 spi0_cs0: spi0-cs0 { 1506 rockchip,pins = <0 RK_PB6 2 &pcfg_pull_up>; 1507 }; 1508 spi0_tx: spi0-tx { 1509 rockchip,pins = <0 RK_PB3 2 &pcfg_pull_up>; 1510 }; 1511 spi0_rx: spi0-rx { 1512 rockchip,pins = <0 RK_PB5 2 &pcfg_pull_up>; 1513 }; 1514 spi0_cs1: spi0-cs1 { 1515 rockchip,pins = <1 RK_PB4 1 &pcfg_pull_up>; 1516 }; 1517 }; 1518 1519 spi-1 { 1520 spi1_clk: spi1-clk { 1521 rockchip,pins = <0 RK_PC7 2 &pcfg_pull_up>; 1522 }; 1523 spi1_cs0: spi1-cs0 { 1524 rockchip,pins = <2 RK_PA2 2 &pcfg_pull_up>; 1525 }; 1526 spi1_rx: spi1-rx { 1527 rockchip,pins = <2 RK_PA0 2 &pcfg_pull_up>; 1528 }; 1529 spi1_tx: spi1-tx { 1530 rockchip,pins = <2 RK_PA1 2 &pcfg_pull_up>; 1531 }; 1532 spi1_cs1: spi1-cs1 { 1533 rockchip,pins = <2 RK_PA3 2 &pcfg_pull_up>; 1534 }; 1535 }; 1536 1537 i2s1 { 1538 i2s1_bus: i2s1-bus { 1539 rockchip,pins = <0 RK_PB0 1 &pcfg_pull_none>, 1540 <0 RK_PB1 1 &pcfg_pull_none>, 1541 <0 RK_PB3 1 &pcfg_pull_none>, 1542 <0 RK_PB4 1 &pcfg_pull_none>, 1543 <0 RK_PB5 1 &pcfg_pull_none>, 1544 <0 RK_PB6 1 &pcfg_pull_none>, 1545 <1 RK_PA2 2 &pcfg_pull_none>, 1546 <1 RK_PA4 2 &pcfg_pull_none>, 1547 <1 RK_PA5 2 &pcfg_pull_none>; 1548 }; 1549 }; 1550 1551 pwm0 { 1552 pwm0_pin: pwm0-pin { 1553 rockchip,pins = <3 RK_PC5 1 &pcfg_pull_none>; 1554 }; 1555 1556 pwm0_pin_pull_down: pwm0-pin-pull-down { 1557 rockchip,pins = <3 RK_PC5 1 &pcfg_pull_down>; 1558 }; 1559 1560 pwm0_pin_pull_down: pwm0-pin-pull-down { 1561 rockchip,pins = <3 RK_PC5 1 &pcfg_pull_down>; 1562 }; 1563 }; 1564 1565 pwm1 { 1566 pwm1_pin: pwm1-pin { 1567 rockchip,pins = <0 RK_PD6 2 &pcfg_pull_none>; 1568 }; 1569 1570 pwm1_pin_pull_down: pwm1-pin-pull-down { 1571 rockchip,pins = <0 RK_PD6 2 &pcfg_pull_down>; 1572 }; 1573 1574 pwm1_pin_pull_down: pwm1-pin-pull-down { 1575 rockchip,pins = <0 RK_PD6 2 &pcfg_pull_down>; 1576 }; 1577 }; 1578 1579 pwm2 { 1580 pwm2_pin: pwm2-pin { 1581 rockchip,pins = <1 RK_PB4 2 &pcfg_pull_none>; 1582 }; 1583 1584 pwm2_pin_pull_down: pwm2-pin-pull-down { 1585 rockchip,pins = <1 RK_PB4 2 &pcfg_pull_down>; 1586 }; 1587 1588 pwm2_pin_pull_down: pwm2-pin-pull-down { 1589 rockchip,pins = <1 RK_PB4 2 &pcfg_pull_down>; 1590 }; 1591 }; 1592 1593 pwm3 { 1594 pwm3_pin: pwm3-pin { 1595 rockchip,pins = <1 RK_PB3 2 &pcfg_pull_none>; 1596 }; 1597 1598 pwm3_pin_pull_down: pwm3-pin-pull-down { 1599 rockchip,pins = <1 RK_PB3 2 &pcfg_pull_down>; 1600 }; 1601 1602 pwm3_pin_pull_down: pwm3-pin-pull-down { 1603 rockchip,pins = <1 RK_PB3 2 &pcfg_pull_down>; 1604 }; 1605 }; 1606 1607 spdif { 1608 spdif_tx: spdif-tx { 1609 rockchip,pins = <3 RK_PD7 2 &pcfg_pull_none>; 1610 }; 1611 }; 1612 1613 tsadc { 1614 otp_gpio: otp-gpio { 1615 rockchip,pins = <0 RK_PD0 RK_FUNC_GPIO &pcfg_pull_none>; 1616 }; 1617 1618 otp_out: otp-out { 1619 rockchip,pins = <0 RK_PD0 2 &pcfg_pull_none>; 1620 }; 1621 }; 1622 1623 uart0 { 1624 uart0_xfer: uart0-xfer { 1625 rockchip,pins = <2 RK_PD2 1 &pcfg_pull_none>, 1626 <2 RK_PD3 1 &pcfg_pull_none>; 1627 }; 1628 1629 uart0_cts: uart0-cts { 1630 rockchip,pins = <2 RK_PD5 1 &pcfg_pull_none>; 1631 }; 1632 1633 uart0_rts: uart0-rts { 1634 rockchip,pins = <0 RK_PC1 1 &pcfg_pull_none>; 1635 }; 1636 }; 1637 1638 uart1 { 1639 uart1_xfer: uart1-xfer { 1640 rockchip,pins = <1 RK_PB1 1 &pcfg_pull_none>, 1641 <1 RK_PB2 1 &pcfg_pull_none>; 1642 }; 1643 1644 uart1_cts: uart1-cts { 1645 rockchip,pins = <1 RK_PB0 1 &pcfg_pull_none>; 1646 }; 1647 1648 uart1_rts: uart1-rts { 1649 rockchip,pins = <1 RK_PB3 1 &pcfg_pull_none>; 1650 }; 1651 }; 1652 1653 uart1-1 { 1654 uart11_xfer: uart11-xfer { 1655 rockchip,pins = <3 RK_PB6 1 &pcfg_pull_up>, 1656 <3 RK_PB5 1 &pcfg_pull_none>; 1657 }; 1658 1659 uart11_cts: uart11-cts { 1660 rockchip,pins = <3 RK_PA7 1 &pcfg_pull_none>; 1661 }; 1662 1663 uart11_rts: uart11-rts { 1664 rockchip,pins = <3 RK_PA6 1 &pcfg_pull_none>; 1665 }; 1666 1667 uart11_rts_gpio: uart11-rts-gpio { 1668 rockchip,pins = <3 RK_PA6 RK_FUNC_GPIO &pcfg_pull_none>; 1669 }; 1670 }; 1671 1672 uart2 { 1673 uart2_xfer: uart2-xfer { 1674 rockchip,pins = <1 RK_PC2 2 &pcfg_pull_up>, 1675 <1 RK_PC3 2 &pcfg_pull_none>; 1676 }; 1677 1678 uart2_cts: uart2-cts { 1679 rockchip,pins = <0 RK_PD1 1 &pcfg_pull_none>; 1680 }; 1681 1682 uart2_rts: uart2-rts { 1683 rockchip,pins = <0 RK_PD0 1 &pcfg_pull_none>; 1684 }; 1685 }; 1686 1687 uart2-1 { 1688 uart21_xfer: uart21-xfer { 1689 rockchip,pins = <1 RK_PB2 2 &pcfg_pull_up>, 1690 <1 RK_PB1 2 &pcfg_pull_none>; 1691 }; 1692 }; 1693 }; 1694 1695 psci { 1696 compatible = "arm,psci-1.0"; 1697 method = "smc"; 1698 }; 1699 1700 rockchip_suspend: rockchip-suspend { 1701 compatible = "rockchip,pm-rk322x"; 1702 status = "disabled"; 1703 rockchip,virtual-poweroff = <0>; 1704 rockchip,sleep-mode-config = < 1705 (0 1706 |RKPM_CTR_GTCLKS 1707 |RKPM_CTR_IDLESRAM_MD 1708 ) 1709 >; 1710 }; 1711}; 1712