1*4882a593Smuzhiyun /* 2*4882a593Smuzhiyun * Copyright (C) 2011 by Vladimir Zapolskiy <vz@mleia.com> 3*4882a593Smuzhiyun * 4*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+ 5*4882a593Smuzhiyun */ 6*4882a593Smuzhiyun 7*4882a593Smuzhiyun #ifndef _LPC32XX_CPU_H 8*4882a593Smuzhiyun #define _LPC32XX_CPU_H 9*4882a593Smuzhiyun 10*4882a593Smuzhiyun /* LPC32XX Memory map */ 11*4882a593Smuzhiyun 12*4882a593Smuzhiyun /* AHB physical base addresses */ 13*4882a593Smuzhiyun #define SLC_NAND_BASE 0x20020000 /* SLC NAND Flash registers base */ 14*4882a593Smuzhiyun #define SSP0_BASE 0x20084000 /* SSP0 registers base */ 15*4882a593Smuzhiyun #define SD_CARD_BASE 0x20098000 /* SD card interface registers base */ 16*4882a593Smuzhiyun #define MLC_NAND_BASE 0x200A8000 /* MLC NAND Flash registers base */ 17*4882a593Smuzhiyun #define DMA_BASE 0x31000000 /* DMA controller registers base */ 18*4882a593Smuzhiyun #define USB_BASE 0x31020000 /* USB registers base */ 19*4882a593Smuzhiyun #define LCD_BASE 0x31040000 /* LCD registers base */ 20*4882a593Smuzhiyun #define ETHERNET_BASE 0x31060000 /* Ethernet registers base */ 21*4882a593Smuzhiyun #define EMC_BASE 0x31080000 /* EMC configuration registers base */ 22*4882a593Smuzhiyun 23*4882a593Smuzhiyun /* FAB peripherals base addresses */ 24*4882a593Smuzhiyun #define CLK_PM_BASE 0x40004000 /* System control registers base */ 25*4882a593Smuzhiyun #define HS_UART1_BASE 0x40014000 /* High speed UART 1 registers base */ 26*4882a593Smuzhiyun #define HS_UART2_BASE 0x40018000 /* High speed UART 2 registers base */ 27*4882a593Smuzhiyun #define HS_UART7_BASE 0x4001C000 /* High speed UART 7 registers base */ 28*4882a593Smuzhiyun #define RTC_BASE 0x40024000 /* RTC registers base */ 29*4882a593Smuzhiyun #define GPIO_BASE 0x40028000 /* GPIO registers base */ 30*4882a593Smuzhiyun #define MUX_BASE 0x40028000 /* MUX registers base */ 31*4882a593Smuzhiyun #define WDT_BASE 0x4003C000 /* Watchdog timer registers base */ 32*4882a593Smuzhiyun #define TIMER0_BASE 0x40044000 /* Timer0 registers base */ 33*4882a593Smuzhiyun #define TIMER1_BASE 0x4004C000 /* Timer1 registers base */ 34*4882a593Smuzhiyun #define UART_CTRL_BASE 0x40054000 /* UART control regsisters base */ 35*4882a593Smuzhiyun 36*4882a593Smuzhiyun /* APB peripherals base addresses */ 37*4882a593Smuzhiyun #define UART3_BASE 0x40080000 /* UART 3 registers base */ 38*4882a593Smuzhiyun #define UART4_BASE 0x40088000 /* UART 4 registers base */ 39*4882a593Smuzhiyun #define UART5_BASE 0x40090000 /* UART 5 registers base */ 40*4882a593Smuzhiyun #define UART6_BASE 0x40098000 /* UART 6 registers base */ 41*4882a593Smuzhiyun #define I2C1_BASE 0x400A0000 /* I2C 1 registers base */ 42*4882a593Smuzhiyun #define I2C2_BASE 0x400A8000 /* I2C 2 registers base */ 43*4882a593Smuzhiyun 44*4882a593Smuzhiyun /* External SDRAM Memory Bank base addresses */ 45*4882a593Smuzhiyun #define EMC_DYCS0_BASE 0x80000000 /* SDRAM DYCS0 base address */ 46*4882a593Smuzhiyun #define EMC_DYCS1_BASE 0xA0000000 /* SDRAM DYCS1 base address */ 47*4882a593Smuzhiyun 48*4882a593Smuzhiyun /* External Static Memory Bank base addresses */ 49*4882a593Smuzhiyun #define EMC_CS0_BASE 0xE0000000 50*4882a593Smuzhiyun #define EMC_CS1_BASE 0xE1000000 51*4882a593Smuzhiyun #define EMC_CS2_BASE 0xE2000000 52*4882a593Smuzhiyun #define EMC_CS3_BASE 0xE3000000 53*4882a593Smuzhiyun 54*4882a593Smuzhiyun #endif /* _LPC32XX_CPU_H */ 55