1 /******************************************************************************
2 *
3 * Copyright(c) 2016 - 2017 Realtek Corporation.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of version 2 of the GNU General Public License as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 *****************************************************************************/
15
16 #include "mp_precomp.h"
17 #include "../phydm_precomp.h"
18
19 #if (RTL8821C_SUPPORT == 1)
20 #if (PHYDM_FW_API_ENABLE_8821C == 1)
21 /* ======================================================================== */
22 /* These following functions can be used for PHY DM only*/
23
24 u32 rega24_8821c;
25 u32 rega28_8821c;
26 u32 regaac_8821c;
27
28 enum channel_width bw_8821c;
29 u8 central_ch_8821c;
30
31 __iram_odm_func__
phydm_igi_toggle_8821c(struct dm_struct * dm)32 void phydm_igi_toggle_8821c(struct dm_struct *dm)
33 {
34 u32 igi = 0x20;
35
36 igi = odm_get_bb_reg(dm, R_0xc50, 0x7f);
37 odm_set_bb_reg(dm, R_0xc50, 0x7f, (igi - 2));
38 odm_set_bb_reg(dm, R_0xc50, 0x7f, igi);
39 }
40
41 __iram_odm_func__
phydm_cck_rssi_8821c(struct dm_struct * dm,u8 lna_idx,u8 vga_idx)42 s8 phydm_cck_rssi_8821c(struct dm_struct *dm, u8 lna_idx, u8 vga_idx)
43 {
44 s8 rx_pwr_all = 0;
45 s8 lna_gain = 0;
46 /*only use lna2/3/5/7*/
47 s8 lna_gain_table_0[8] = {22, 8, -6, -22, -31, -40, -46, -52};
48 /*only use lna4/8/C/F*/
49 s8 lna_gain_table_1[16] = {10, 6, 2, -2, -6, -10, -14, -17,
50 -20, -24, -28, -31, -34, -37, -40, -44};
51
52 if (dm->cck_agc_report_type == 0)
53 lna_gain = lna_gain_table_0[lna_idx];
54 else
55 lna_gain = lna_gain_table_1[lna_idx];
56
57 rx_pwr_all = lna_gain - (2 * vga_idx);
58
59 return rx_pwr_all;
60 }
61
62 __iram_odm_func__
63 boolean
phydm_rfe_8821c(struct dm_struct * dm,u8 channel)64 phydm_rfe_8821c(struct dm_struct *dm, u8 channel)
65 {
66 #if 0
67 /* Efuse is not wrote now */
68 /* Need to check RFE type finally */
69 /*if (dm->rfe_type == 1) {*/
70 if (channel <= 14) {
71 /* signal source */
72 odm_set_bb_reg(dm, R_0xcb0, (MASKBYTE2 | MASKLWORD), 0x704570);
73 odm_set_bb_reg(dm, R_0xeb0, (MASKBYTE2 | MASKLWORD), 0x704570);
74 odm_set_bb_reg(dm, R_0xcb4, MASKBYTE1, 0x45);
75 odm_set_bb_reg(dm, R_0xeb4, MASKBYTE1, 0x45);
76 } else if (channel > 35) {
77 odm_set_bb_reg(dm, R_0xcb0, (MASKBYTE2 | MASKLWORD), 0x174517);
78 odm_set_bb_reg(dm, R_0xeb0, (MASKBYTE2 | MASKLWORD), 0x174517);
79 odm_set_bb_reg(dm, R_0xcb4, MASKBYTE1, 0x45);
80 odm_set_bb_reg(dm, R_0xeb4, MASKBYTE1, 0x45);
81 } else
82 return false;
83
84 /* chip top mux */
85 odm_set_bb_reg(dm, R_0x64, BIT(29) | BIT(28), 0x3);
86 odm_set_bb_reg(dm, R_0x4c, BIT(26) | BIT(25), 0x0);
87 odm_set_bb_reg(dm, R_0x40, BIT(2), 0x1);
88
89 /* from s0 or s1 */
90 odm_set_bb_reg(dm, R_0x1990, (BIT(5) | BIT(4) | BIT(3) | BIT(2) | BIT(1) | BIT(0)), 0x30);
91 odm_set_bb_reg(dm, R_0x1990, (BIT(11) | BIT(10)), 0x3);
92
93 /* input or output */
94 odm_set_bb_reg(dm, R_0x974, (BIT(5) | BIT(4) | BIT(3) | BIT(2) | BIT(1) | BIT(0)), 0x3f);
95 odm_set_bb_reg(dm, R_0x974, (BIT(11) | BIT(10)), 0x3);
96
97 /* delay 400ns for PAPE */
98 odm_set_bb_reg(dm, R_0x810, MASKBYTE3 | BIT(20) | BIT(21) | BIT(22) | BIT(23), 0x211);
99
100 /* antenna switch table */
101 odm_set_bb_reg(dm, R_0xca0, MASKLWORD, 0xa555);
102 odm_set_bb_reg(dm, R_0xea0, MASKLWORD, 0xa555);
103
104 /* inverse or not */
105 odm_set_bb_reg(dm, R_0xcbc, (BIT(5) | BIT(4) | BIT(3) | BIT(2) | BIT(1) | BIT(0)), 0x0);
106 odm_set_bb_reg(dm, R_0xcbc, (BIT(11) | BIT(10)), 0x0);
107 odm_set_bb_reg(dm, R_0xebc, (BIT(5) | BIT(4) | BIT(3) | BIT(2) | BIT(1) | BIT(0)), 0x0);
108 odm_set_bb_reg(dm, R_0xebc, (BIT(11) | BIT(10)), 0x0);
109 /*}*/
110 #endif
111 return true;
112 }
113
114 __iram_odm_func__
phydm_ccapar_8821c(struct dm_struct * dm)115 void phydm_ccapar_8821c(struct dm_struct *dm)
116 {
117 #if 0
118 u32 cca_ifem[9][4] = {
119 /*20M*/
120 {0x75D97010, 0x75D97010, 0x75D97010, 0x75D97010}, /*Reg82C*/
121 {0x00000000, 0x00000000, 0x00000000, 0x00000000}, /*Reg830*/
122 {0x00000000, 0x00000000, 0x00000000, 0x00000000}, /*Reg838*/
123 /*40M*/
124 {0x75D97010, 0x75D97010, 0x75D97010, 0x75D97010}, /*Reg82C*/
125 {0x00000000, 0x79a0ea28, 0x00000000, 0x79a0ea28}, /*Reg830*/
126 {0x87765541, 0x87766341, 0x87765541, 0x87766341}, /*Reg838*/
127 /*80M*/
128 {0x75D97010, 0x75D97010, 0x75D97010, 0x75D97010}, /*Reg82C*/
129 {0x00000000, 0x00000000, 0x00000000, 0x00000000}, /*Reg830*/
130 {0x00000000, 0x87746641, 0x00000000, 0x87746641}
131 }; /*Reg838*/
132
133 u32 cca_efem[9][4] = {
134 /*20M*/
135 {0x75A76010, 0x75A76010, 0x75A76010, 0x75A75010}, /*Reg82C*/
136 {0x00000000, 0x00000000, 0x00000000, 0x00000000}, /*Reg830*/
137 {0x87766651, 0x87766431, 0x87766451, 0x87766431}, /*Reg838*/
138 /*40M*/
139 {0x75A75010, 0x75A75010, 0x75A75010, 0x75A75010}, /*Reg82C*/
140 {0x00000000, 0x00000000, 0x00000000, 0x00000000}, /*Reg830*/
141 {0x87766431, 0x87766431, 0x87766431, 0x87766431}, /*Reg838*/
142 /*80M*/
143 {0x75BA7010, 0x75BA7010, 0x75BA7010, 0x75BA7010}, /*Reg82C*/
144 {0x00000000, 0x00000000, 0x00000000, 0x00000000}, /*Reg830*/
145 {0x87766431, 0x87766431, 0x87766431, 0x87766431}
146 }; /*Reg838*/
147
148 u8 row, col;
149 u32 reg82c, reg830, reg838;
150
151 if (dm->cut_version != ODM_CUT_B)
152 return;
153
154 if (bw_8821c == CHANNEL_WIDTH_20)
155 row = 0;
156 else if (bw_8821c == CHANNEL_WIDTH_40)
157 row = 3;
158 else
159 row = 6;
160
161 if (central_ch_8821c <= 14) {
162 if (dm->rx_ant_status == BB_PATH_A || dm->rx_ant_status == BB_PATH_B)
163 col = 0;
164 else
165 col = 1;
166 } else {
167 if (dm->rx_ant_status == BB_PATH_A || dm->rx_ant_status == BB_PATH_B)
168 col = 2;
169 else
170 col = 3;
171 }
172
173 if (dm->rfe_type == 0) {/*iFEM*/
174 reg82c = (cca_ifem[row][col] != 0) ? cca_ifem[row][col] : reg82c_8821c;
175 reg830 = (cca_ifem[row + 1][col] != 0) ? cca_ifem[row + 1][col] : reg830_8821c;
176 reg838 = (cca_ifem[row + 2][col] != 0) ? cca_ifem[row + 2][col] : reg838_8821c;
177 } else {/*eFEM*/
178 reg82c = (cca_efem[row][col] != 0) ? cca_efem[row][col] : reg82c_8821c;
179 reg830 = (cca_efem[row + 1][col] != 0) ? cca_efem[row + 1][col] : reg830_8821c;
180 reg838 = (cca_efem[row + 2][col] != 0) ? cca_efem[row + 2][col] : reg838_8821c;
181 }
182
183 odm_set_bb_reg(dm, R_0x82c, MASKDWORD, reg82c);
184 odm_set_bb_reg(dm, R_0x830, MASKDWORD, reg830);
185 odm_set_bb_reg(dm, R_0x838, MASKDWORD, reg838);
186 #endif
187 }
188
189 __iram_odm_func__
phydm_ccapar_by_bw_8821c(struct dm_struct * dm,enum channel_width bandwidth)190 void phydm_ccapar_by_bw_8821c(struct dm_struct *dm,
191 enum channel_width bandwidth)
192 {
193 #if 0
194 u32 reg82c;
195
196
197 if (dm->cut_version != ODM_CUT_A)
198 return;
199
200 /* A-cut */
201 reg82c = odm_get_bb_reg(dm, R_0x82c, MASKDWORD);
202
203 if (bandwidth == CHANNEL_WIDTH_20) {
204 /* 82c[15:12] = 4 */
205 /* 82c[27:24] = 6 */
206
207 reg82c &= (~(0x0f00f000));
208 reg82c |= ((0x4) << 12);
209 reg82c |= ((0x6) << 24);
210 } else if (bandwidth == CHANNEL_WIDTH_40) {
211 /* 82c[19:16] = 9 */
212 /* 82c[27:24] = 6 */
213
214 reg82c &= (~(0x0f0f0000));
215 reg82c |= ((0x9) << 16);
216 reg82c |= ((0x6) << 24);
217 } else if (bandwidth == CHANNEL_WIDTH_80) {
218 /* 82c[15:12] 7 */
219 /* 82c[19:16] b */
220 /* 82c[23:20] d */
221 /* 82c[27:24] 3 */
222
223 reg82c &= (~(0x0ffff000));
224 reg82c |= ((0xdb7) << 12);
225 reg82c |= ((0x3) << 24);
226 }
227
228 odm_set_bb_reg(dm, R_0x82c, MASKDWORD, reg82c);
229 #endif
230 }
231
232 __iram_odm_func__
phydm_ccapar_by_rxpath_8821c(struct dm_struct * dm)233 void phydm_ccapar_by_rxpath_8821c(struct dm_struct *dm)
234 {
235 #if 0
236 if (dm->cut_version != ODM_CUT_A)
237 return;
238
239 if (dm->rx_ant_status == BB_PATH_A || dm->rx_ant_status == BB_PATH_B) {
240 /* 838[7:4] = 8 */
241 /* 838[11:8] = 7 */
242 /* 838[15:12] = 6 */
243 /* 838[19:16] = 7 */
244 /* 838[23:20] = 7 */
245 /* 838[27:24] = 7 */
246 odm_set_bb_reg(dm, R_0x838, 0x0ffffff0, 0x777678);
247 } else {
248 /* 838[7:4] = 3 */
249 /* 838[11:8] = 3 */
250 /* 838[15:12] = 6 */
251 /* 838[19:16] = 6 */
252 /* 838[23:20] = 7 */
253 /* 838[27:24] = 7 */
254 odm_set_bb_reg(dm, R_0x838, 0x0ffffff0, 0x776633);
255 }
256 #endif
257 }
258
259 __iram_odm_func__
phydm_rxdfirpar_by_bw_8821c(struct dm_struct * dm,enum channel_width bandwidth)260 void phydm_rxdfirpar_by_bw_8821c(struct dm_struct *dm,
261 enum channel_width bandwidth)
262 {
263 if (bandwidth == CHANNEL_WIDTH_40) {
264 /* RX DFIR for BW40 */
265 odm_set_bb_reg(dm, R_0x948, BIT(29) | BIT(28), 0x2);
266 odm_set_bb_reg(dm, R_0x94c, BIT(29) | BIT(28), 0x2);
267 odm_set_bb_reg(dm, R_0xc20, BIT(31), 0x0);
268 odm_set_bb_reg(dm, R_0x8f0, BIT(31), 0x0);
269 } else if (bandwidth == CHANNEL_WIDTH_80) {
270 /* RX DFIR for BW80 */
271 odm_set_bb_reg(dm, R_0x948, BIT(29) | BIT(28), 0x2);
272 odm_set_bb_reg(dm, R_0x94c, BIT(29) | BIT(28), 0x1);
273 odm_set_bb_reg(dm, R_0xc20, BIT(31), 0x0);
274 odm_set_bb_reg(dm, R_0x8f0, BIT(31), 0x1);
275 } else {
276 /* RX DFIR for BW20, BW10 and BW5*/
277 odm_set_bb_reg(dm, R_0x948, BIT(29) | BIT(28), 0x2);
278 odm_set_bb_reg(dm, R_0x94c, BIT(29) | BIT(28), 0x2);
279 odm_set_bb_reg(dm, R_0xc20, BIT(31), 0x1);
280 odm_set_bb_reg(dm, R_0x8f0, BIT(31), 0x0);
281 }
282 /* PHYDM_DBG(dm, ODM_PHY_CONFIG, "phydm_rxdfirpar_by_bw_8821c\n");*/
283 }
284
285 __iram_odm_func__
286 boolean
phydm_write_txagc_1byte_8821c(struct dm_struct * dm,u32 power_index,enum rf_path path,u8 hw_rate)287 phydm_write_txagc_1byte_8821c(struct dm_struct *dm, u32 power_index,
288 enum rf_path path, u8 hw_rate)
289 {
290 #if (PHYDM_FW_API_FUNC_ENABLE_8821C == 1)
291 u32 offset_txagc[2] = {0x1d00, 0x1d80};
292 u8 rate_idx = (hw_rate & 0xfc), i;
293 u8 rate_offset = (hw_rate & 0x3);
294 u32 txagc_content = 0x0;
295
296 /* For debug command only!!!! */
297
298 /* Error handling */
299 if (path > RF_PATH_A || hw_rate > 0x53) {
300 PHYDM_DBG(dm, ODM_PHY_CONFIG, "[%s]: unsupported path (%d)\n",
301 __func__, path);
302 return false;
303 }
304
305 #if 1
306 /* For HW limitation, We can't write TXAGC once a byte. */
307 for (i = 0; i < 4; i++) {
308 if (i != rate_offset)
309 txagc_content = txagc_content | (config_phydm_read_txagc_8821c(dm, path, rate_idx + i) << (i << 3));
310 else
311 txagc_content = txagc_content | ((power_index & 0x3f) << (i << 3));
312 }
313 odm_set_bb_reg(dm, (offset_txagc[path] + rate_idx), MASKDWORD, txagc_content);
314 #else
315 odm_write_1byte(dm, (offset_txagc[path] + hw_rate), (power_index & 0x3f));
316 #endif
317
318 PHYDM_DBG(dm, ODM_PHY_CONFIG,
319 "[%s]: path-%d rate index 0x%x (0x%x) = 0x%x\n", __func__,
320 path, hw_rate, (offset_txagc[path] + hw_rate), power_index);
321 return true;
322 #else
323 return false;
324 #endif
325 }
326
327 __iram_odm_func__
phydm_init_hw_info_by_rfe_type_8821c(struct dm_struct * dm)328 void phydm_init_hw_info_by_rfe_type_8821c(struct dm_struct *dm)
329 {
330 #if (PHYDM_FW_API_FUNC_ENABLE_8821C == 1)
331 dm->is_init_hw_info_by_rfe = false;
332 /*
333 * Let original variable rfe_type to be rfe_type_8821c.
334 * Varible rfe_type as symbol is used to identify PHY parameter.
335 */
336 dm->rfe_type = dm->rfe_type_expand >> 3;
337
338 /*2.4G default rf set with wlg or btg*/
339 if (dm->rfe_type_expand == 2 || dm->rfe_type_expand == 4 || dm->rfe_type_expand == 7) {
340 dm->default_rf_set_8821c = SWITCH_TO_BTG;
341 } else if (dm->rfe_type_expand == 0 || dm->rfe_type_expand == 1 ||
342 dm->rfe_type_expand == 3 || dm->rfe_type_expand == 5 ||
343 dm->rfe_type_expand == 6) {
344 dm->default_rf_set_8821c = SWITCH_TO_WLG;
345 } else if (dm->rfe_type_expand == 0x22 || dm->rfe_type_expand == 0x24 ||
346 dm->rfe_type_expand == 0x27 || dm->rfe_type_expand == 0x2a ||
347 dm->rfe_type_expand == 0x2c || dm->rfe_type_expand == 0x2f) {
348 dm->default_rf_set_8821c = SWITCH_TO_BTG;
349 odm_cmn_info_init(dm, ODM_CMNINFO_PACKAGE_TYPE, 1);
350 } else if (dm->rfe_type_expand == 0x20 || dm->rfe_type_expand == 0x21 ||
351 dm->rfe_type_expand == 0x23 || dm->rfe_type_expand == 0x25 ||
352 dm->rfe_type_expand == 0x26 || dm->rfe_type_expand == 0x28 ||
353 dm->rfe_type_expand == 0x29 || dm->rfe_type_expand == 0x2b ||
354 dm->rfe_type_expand == 0x2d || dm->rfe_type_expand == 0x2e) {
355 dm->default_rf_set_8821c = SWITCH_TO_WLG;
356 odm_cmn_info_init(dm, ODM_CMNINFO_PACKAGE_TYPE, 1);
357 }
358
359 if (dm->rfe_type_expand == 3 || dm->rfe_type_expand == 4 ||
360 dm->rfe_type_expand == 0x23 || dm->rfe_type_expand == 0x24 ||
361 dm->rfe_type_expand == 0x2b || dm->rfe_type_expand == 0x2c)
362 dm->default_ant_num_8821c = SWITCH_TO_ANT2;
363 else
364 dm->default_ant_num_8821c = SWITCH_TO_ANT1;
365
366 if (dm->package_type == 1 && dm->rfe_type_expand <= 0x2f &&
367 dm->rfe_type_expand >= 0x28)
368 odm_set_bb_reg(dm, R_0xcb4, MASKDWORD, 0x00000073);
369 else if (dm->rfe_type_expand == 4)
370 odm_set_bb_reg(dm, R_0xcb4, MASKDWORD, 0x20000077);
371 else
372 odm_set_bb_reg(dm, R_0xcb4, MASKDWORD, 0x10000077);
373
374 dm->is_init_hw_info_by_rfe = true;
375 PHYDM_DBG(dm, ODM_PHY_CONFIG, "%s: RFE type (%d), rf set (%s)\n",
376 __FUNCTION__, dm->rfe_type_expand,
377 dm->default_rf_set_8821c == 0 ? "BTG" : "WLG");
378 #endif
379 }
380
381 __iram_odm_func__
phydm_set_gnt_state_8821c(struct dm_struct * dm,boolean gnt_wl_state,boolean gnt_bt_state)382 void phydm_set_gnt_state_8821c(struct dm_struct *dm, boolean gnt_wl_state,
383 boolean gnt_bt_state)
384 {
385 #if (PHYDM_FW_API_FUNC_ENABLE_8821C == 1)
386 u32 gnt_val = 0;
387
388 odm_set_bb_reg(dm, R_0x70, BIT(26), 0x1);
389
390 if (gnt_wl_state)
391 gnt_val = 0x3300;
392 else
393 gnt_val = 0x1100;
394
395 if (gnt_bt_state)
396 gnt_val = gnt_val | 0xcc00;
397 else
398 gnt_val = gnt_val | 0x4400;
399
400 odm_set_bb_reg(dm, R_0x1704, MASKLWORD, gnt_val);
401 ODM_delay_us(50); /*waiting before access 0x1700 */
402 odm_set_bb_reg(dm, R_0x1700, MASKDWORD, 0xc00f0038);
403 #endif
404 }
405
406 __iram_odm_func__
407 void
phydm_dynamic_spur_det_eliminate_8821c(struct dm_struct * dm)408 phydm_dynamic_spur_det_eliminate_8821c(struct dm_struct *dm)
409 {
410 #if (PHYDM_FW_API_FUNC_ENABLE_8821C == 1)
411
412 u32 freq_5g[FREQ_PT_5G_NUM_8821C] = {0x3e0, 0x20, 0x3a0};
413 u32 freq_5g_n1[FREQ_PT_5G_NUM_8821C] = {0};
414 u32 freq_5g_p1[FREQ_PT_5G_NUM_8821C] = {0};
415 u32 freq_pt_5g_final = 0;
416 u32 max_ret_psd_final = 0;
417 u32 max_ret_psd_2nd[PSD_SMP_NUM_8821C] = {0};
418 u32 psd_set[PSD_VAL_NUM_8821C] = {0};
419 u32 rank_psd_index_in[PSD_VAL_NUM_8821C] = {0};
420 u32 rank_psd_index_out[PSD_VAL_NUM_8821C] = {0};
421 u32 rank_sample_index_in[PSD_SMP_NUM_8821C] = {0};
422 u32 rank_sample_index_out[PSD_SMP_NUM_8821C] = {0};
423 u16 threshold_nbi = 0x11a;
424 u8 j = 0, k = 0;
425 u8 idx = 0;
426 boolean s_donbi_a = false;
427
428 /*PSD parameters init*/
429 odm_set_bb_reg(dm, R_0x910, 0xfffc00, 0x3f);
430
431 /* Reset NBI everytime after changing channel/BW/band */
432 phydm_nbi_enable(dm, FUNC_DISABLE);
433
434 /* 5G Channel Setting > 20M: 153; 40M: 151; 80M: 155 */
435 switch (*dm->channel) {
436 case 153:
437 idx = 0;
438 break;
439 case 151:
440 idx = 1;
441 break;
442 case 155:
443 idx = 2;
444 break;
445 default:
446 idx = 16;
447 break;
448 }
449
450 if (idx > 13) {
451 PHYDM_DBG(dm, ODM_PHY_CONFIG, "Not support dym spur det\n");
452 return;
453 }
454
455 PHYDM_DBG(dm, ODM_PHY_CONFIG, "[%s] idx = %d, BW = %d, Channel = %d\n",
456 __func__, idx, *dm->band_width, *dm->channel);
457
458 for (k = 0; k < FREQ_PT_5G_NUM_8821C; k++) {
459 freq_5g_n1[k] = freq_5g[k] - 1;
460 freq_5g_p1[k] = freq_5g[k] + 1;
461 }
462
463 for (k = 0; k < PSD_SMP_NUM_8821C; k++) {
464 if (k == 0)
465 freq_pt_5g_final = freq_5g_n1[idx];
466 else if (k == 1)
467 freq_pt_5g_final = freq_5g[idx];
468 else if (k == 2)
469 freq_pt_5g_final = freq_5g_p1[idx];
470
471 odm_set_bb_reg(dm, R_0x910, 0x3ff, freq_pt_5g_final);
472
473 for (j = 0; j < PSD_VAL_NUM_8821C; j++) {
474 /*stop TRX*/
475 if (phydm_stop_ic_trx(dm, PHYDM_SET) == PHYDM_SET_FAIL)
476 return;
477
478 ODM_delay_us(10);
479
480 /*Stop 3-wires*/
481 phydm_stop_3_wire(dm, PHYDM_SET);
482
483 /* Start PSD */
484 odm_set_bb_reg(dm, R_0x910, BIT(22), 0x1);
485
486 ODM_delay_us(500);
487
488 psd_set[j] = odm_get_bb_reg(dm, R_0xf44, 0xffffff);
489 psd_set[j] = psd_set[j] >> 5;
490
491 /* turn off PSD */
492 odm_set_bb_reg(dm, R_0x910, BIT(22), 0x0);
493
494 /*Start 3-wires*/
495 phydm_stop_3_wire(dm, PHYDM_REVERT);
496
497 ODM_delay_us(10);
498
499 phydm_stop_ic_trx(dm, PHYDM_REVERT);
500
501 phydm_igi_toggle_8821c(dm);
502 }
503
504 phydm_seq_sorting(dm, psd_set, rank_psd_index_in,
505 rank_psd_index_out, PSD_VAL_NUM_8821C);
506 max_ret_psd_2nd[k] = psd_set[0];
507 }
508
509 phydm_seq_sorting(dm, max_ret_psd_2nd, rank_sample_index_in,
510 rank_sample_index_out, PSD_SMP_NUM_8821C);
511 max_ret_psd_final = max_ret_psd_2nd[0];
512
513 if (max_ret_psd_final >= threshold_nbi)
514 s_donbi_a = true;
515 else
516 s_donbi_a = false;
517
518 PHYDM_DBG(dm, ODM_PHY_CONFIG, "[%s] max_ret_psd_final = %d\n",
519 __func__, max_ret_psd_final);
520
521 if (!s_donbi_a)
522 return;
523
524 if (*dm->band_width == CHANNEL_WIDTH_20 && *dm->channel == 153)
525 phydm_nbi_setting(dm, FUNC_ENABLE, 153, 20, 5760,
526 PHYDM_DONT_CARE);
527 else if (*dm->band_width == CHANNEL_WIDTH_40 && *dm->channel == 151)
528 phydm_nbi_setting(dm, FUNC_ENABLE, 151, 40, 5760,
529 PHYDM_DONT_CARE);
530 else if (*dm->band_width == CHANNEL_WIDTH_80 && *dm->channel == 155)
531 phydm_nbi_setting(dm, FUNC_ENABLE, 155, 80, 5760,
532 PHYDM_DONT_CARE);
533
534 #endif /*PHYDM_SPUR_CANCELL_ENABLE_8821C == 1*/
535 }
536 /* ======================================================================== */
537
538 /* ======================================================================== */
539 /* These following functions can be used by driver*/
540
541 __iram_odm_func__
config_phydm_read_rf_reg_8821c(struct dm_struct * dm,enum rf_path path,u32 reg_addr,u32 bit_mask)542 u32 config_phydm_read_rf_reg_8821c(struct dm_struct *dm, enum rf_path path,
543 u32 reg_addr, u32 bit_mask)
544 {
545 u32 readback_value, direct_addr;
546 u32 offset_read_rf[2] = {0x2800, 0x2c00};
547
548 /* Error handling.*/
549 if (path > RF_PATH_A) {
550 PHYDM_DBG(dm, ODM_PHY_CONFIG, "[%s]: unsupported path (%d)\n",
551 __func__, path);
552 return INVALID_RF_DATA;
553 }
554
555 /* Calculate offset */
556 reg_addr &= 0xff;
557 direct_addr = offset_read_rf[path] + (reg_addr << 2);
558
559 /* RF register only has 20bits */
560 bit_mask &= RFREGOFFSETMASK;
561
562 /* Read RF register directly */
563 readback_value = odm_get_bb_reg(dm, direct_addr, bit_mask);
564 PHYDM_DBG(dm, ODM_PHY_CONFIG,
565 "[%s]: RF-%d 0x%x = 0x%x, bit mask = 0x%x\n", __func__, path,
566 reg_addr, readback_value, bit_mask);
567 return readback_value;
568 }
569
570 __iram_odm_func__
571 boolean
config_phydm_write_rf_reg_8821c(struct dm_struct * dm,enum rf_path path,u32 reg_addr,u32 bit_mask,u32 data)572 config_phydm_write_rf_reg_8821c(struct dm_struct *dm, enum rf_path path,
573 u32 reg_addr, u32 bit_mask, u32 data)
574 {
575 u32 data_and_addr = 0, data_original = 0;
576 u32 offset_write_rf[2] = {0xc90, 0xe90};
577 u8 bit_shift;
578
579 /* Error handling.*/
580 if (path > RF_PATH_A) {
581 PHYDM_DBG(dm, ODM_PHY_CONFIG, "[%s]: unsupported path (%d)\n",
582 __func__, path);
583 return false;
584 }
585
586 /* Read RF register content first */
587 reg_addr &= 0xff;
588 bit_mask = bit_mask & RFREGOFFSETMASK;
589
590 if (bit_mask != RFREGOFFSETMASK) {
591 data_original = config_phydm_read_rf_reg_8821c(dm, path, reg_addr, RFREGOFFSETMASK);
592
593 /* Error handling. RF is disabled */
594 if (config_phydm_read_rf_check_8821c(data_original) == false) {
595 PHYDM_DBG(dm, ODM_PHY_CONFIG,
596 "[%s]: Write fail, RF is disable\n",
597 __func__);
598 return false;
599 }
600
601 /* check bit mask */
602 if (bit_mask != 0xfffff) {
603 for (bit_shift = 0; bit_shift <= 19; bit_shift++) {
604 if (((bit_mask >> bit_shift) & 0x1) == 1)
605 break;
606 }
607 data = ((data_original) & (~bit_mask)) | (data << bit_shift);
608 }
609 }
610
611 /* Put write addr in [27:20] and write data in [19:00] */
612 data_and_addr = ((reg_addr << 20) | (data & 0x000fffff)) & 0x0fffffff;
613
614 /* Write operation */
615 odm_set_bb_reg(dm, offset_write_rf[path], MASKDWORD, data_and_addr);
616 PHYDM_DBG(dm, ODM_PHY_CONFIG,
617 "[%s]: RF-%d 0x%x = 0x%x (original: 0x%x), bit mask = 0x%x\n",
618 __func__, path, reg_addr, data, data_original, bit_mask);
619
620 #if (defined(CONFIG_RUN_IN_DRV))
621 if (dm->support_interface == ODM_ITRF_PCIE)
622 ODM_delay_us(13);
623 #elif (defined(CONFIG_RUN_IN_FW))
624 ODM_delay_us(13);
625 #endif
626
627 return true;
628 }
629
630 __iram_odm_func__
631 boolean
config_phydm_write_txagc_8821c(struct dm_struct * dm,u32 power_index,enum rf_path path,u8 hw_rate)632 config_phydm_write_txagc_8821c(struct dm_struct *dm, u32 power_index,
633 enum rf_path path, u8 hw_rate)
634 {
635 #if (PHYDM_FW_API_FUNC_ENABLE_8821C == 1)
636 u32 offset_txagc[2] = {0x1d00, 0x1d80};
637 u8 rate_idx = (hw_rate & 0xfc);
638
639 /* Input need to be HW rate index, not driver rate index!!!! */
640
641 if (dm->is_disable_phy_api) {
642 PHYDM_DBG(dm, ODM_PHY_CONFIG,
643 "[%s]: disable PHY API for debug!!\n", __func__);
644 return true;
645 }
646
647 /* Error handling */
648 if (path > RF_PATH_A || hw_rate > 0x53) {
649 PHYDM_DBG(dm, ODM_PHY_CONFIG, "[%s]: unsupported path (%d)\n",
650 __func__, path);
651 return false;
652 }
653
654 /* driver need to construct a 4-byte power index */
655 odm_set_bb_reg(dm, (offset_txagc[path] + rate_idx), MASKDWORD, power_index);
656
657 PHYDM_DBG(dm, ODM_PHY_CONFIG,
658 "[%s]: path-%d rate index 0x%x (0x%x) = 0x%x\n", __func__,
659 path, hw_rate, (offset_txagc[path] + hw_rate), power_index);
660 return true;
661 #else
662 return false;
663 #endif
664 }
665
666 __iram_odm_func__
config_phydm_read_txagc_8821c(struct dm_struct * dm,enum rf_path path,u8 hw_rate)667 u8 config_phydm_read_txagc_8821c(struct dm_struct *dm, enum rf_path path,
668 u8 hw_rate)
669 {
670 #if (PHYDM_FW_API_FUNC_ENABLE_8821C == 1)
671 u8 read_back_data;
672
673 /* Input need to be HW rate index, not driver rate index!!!! */
674
675 /* Error handling */
676 if (path > RF_PATH_A || hw_rate > 0x53) {
677 PHYDM_DBG(dm, ODM_PHY_CONFIG, "[%s]: unsupported path (%d)\n",
678 __func__, path);
679 return INVALID_TXAGC_DATA;
680 }
681
682 /* Disable TX AGC report */
683 odm_set_bb_reg(dm, R_0x1998, BIT(16), 0x0); /* need to check */
684
685 /* Set data rate index (bit0~6) and path index (bit7) */
686 odm_set_bb_reg(dm, R_0x1998, MASKBYTE0, (hw_rate | (path << 7)));
687
688 /* Enable TXAGC report */
689 odm_set_bb_reg(dm, R_0x1998, BIT(16), 0x1);
690
691 /* Read TX AGC report */
692 read_back_data = (u8)odm_get_bb_reg(dm, R_0xd30, 0x7f0000);
693
694 /* Driver have to disable TXAGC report after reading TXAGC (ref. user guide v11) */
695 odm_set_bb_reg(dm, R_0x1998, BIT(16), 0x0);
696
697 PHYDM_DBG(dm, ODM_PHY_CONFIG, "[%s]: path-%d rate index 0x%x = 0x%x\n",
698 __func__, path, hw_rate, read_back_data);
699 return read_back_data;
700 #else
701 return 0;
702 #endif
703 }
704
705 __iram_odm_func__
706 boolean
config_phydm_switch_band_8821c(struct dm_struct * dm,u8 central_ch)707 config_phydm_switch_band_8821c(struct dm_struct *dm, u8 central_ch)
708 {
709 u32 rf_reg18;
710 boolean rf_reg_status = true;
711
712 PHYDM_DBG(dm, ODM_PHY_CONFIG, "[%s]======================>\n",
713 __func__);
714
715 if (dm->is_disable_phy_api) {
716 PHYDM_DBG(dm, ODM_PHY_CONFIG,
717 "[%s]: disable PHY API for debug!!\n", __func__);
718 return true;
719 }
720
721 rf_reg18 = config_phydm_read_rf_reg_8821c(dm, RF_PATH_A, 0x18, RFREGOFFSETMASK);
722 rf_reg_status = rf_reg_status & config_phydm_read_rf_check_8821c(rf_reg18);
723
724 if (central_ch <= 14) {
725 /* 2.4G */
726
727 /* Enable CCK block */
728 odm_set_bb_reg(dm, R_0x808, BIT(28), 0x1);
729
730 /* Disable MAC CCK check */
731 odm_set_bb_reg(dm, R_0x454, BIT(7), 0x0);
732
733 /* Disable BB CCK check */
734 odm_set_bb_reg(dm, R_0xa80, BIT(18), 0x0);
735
736 /*CCA Mask*/
737 odm_set_bb_reg(dm, R_0x814, 0x0000FC00, 15); /*default value*/
738
739 /* RF band */
740 rf_reg18 = (rf_reg18 & (~(BIT(16) | BIT(9) | BIT(8))));
741 rf_reg18 = (rf_reg18 & (~(MASKBYTE0)));
742 rf_reg18 = (rf_reg18 | central_ch);
743 #if (PHYDM_FW_API_FUNC_ENABLE_8821C == 1)
744 /* Switch WLG/BTG*/
745 if (dm->default_rf_set_8821c == SWITCH_TO_BTG)
746 config_phydm_switch_rf_set_8821c(dm, SWITCH_TO_BTG);
747 else if (dm->default_rf_set_8821c == SWITCH_TO_WLG)
748 config_phydm_switch_rf_set_8821c(dm, SWITCH_TO_WLG);
749 #endif
750 /*RF TXA_TANK LUT mode*/
751 odm_set_rf_reg(dm, RF_PATH_A, RF_0xdf, BIT(6), 0x1);
752
753 /*RF TXA_PA_TANK*/
754 odm_set_rf_reg(dm, RF_PATH_A, RF_0x64, 0x0000f, 0xf);
755
756 } else if (central_ch > 35) {
757 /* 5G */
758
759 /* Enable BB CCK check */
760 odm_set_bb_reg(dm, R_0xa80, BIT(18), 0x1);
761
762 /* Enable CCK check */
763 odm_set_bb_reg(dm, R_0x454, BIT(7), 0x1);
764
765 /* Disable CCK block */
766 odm_set_bb_reg(dm, R_0x808, BIT(28), 0x0);
767
768 /*CCA Mask*/
769 odm_set_bb_reg(dm, R_0x814, 0x0000FC00, 15); /*default value*/
770 /*odm_set_bb_reg(dm, R_0x814, 0x0000FC00, 34); CCA mask = 13.6us*/
771
772 /* RF band */
773 rf_reg18 = (rf_reg18 & (~(BIT(16) | BIT(9) | BIT(8))));
774 rf_reg18 = (rf_reg18 | BIT(8) | BIT(16));
775 rf_reg18 = (rf_reg18 & (~(MASKBYTE0)));
776 rf_reg18 = (rf_reg18 | central_ch);
777 #if (PHYDM_FW_API_FUNC_ENABLE_8821C == 1)
778 /* Switch WLA */
779 config_phydm_switch_rf_set_8821c(dm, SWITCH_TO_WLA);
780 #endif
781 /*RF TXA_TANK LUT mode*/
782 odm_set_rf_reg(dm, RF_PATH_A, RF_0xdf, BIT(6), 0x0);
783
784 } else {
785 PHYDM_DBG(dm, ODM_PHY_CONFIG,
786 "[%s]: Fail to switch band (ch: %d)\n", __func__,
787 central_ch);
788 return false;
789 }
790
791 phydm_stop_ic_trx(dm, PHYDM_SET);
792 odm_set_rf_reg(dm, RF_PATH_A, RF_0x18, RFREGOFFSETMASK, rf_reg18);
793 phydm_stop_ic_trx(dm, PHYDM_REVERT);
794
795 if (phydm_rfe_8821c(dm, central_ch) == false)
796 return false;
797
798 if (!rf_reg_status) {
799 PHYDM_DBG(dm, ODM_PHY_CONFIG,
800 "[%s]: Fail to switch band (ch: %d), because writing RF register is fail\n",
801 __func__, central_ch);
802 return false;
803 }
804
805 PHYDM_DBG(dm, ODM_PHY_CONFIG, "[%s]: Success to switch band (ch: %d)\n",
806 __func__, central_ch);
807 return true;
808 }
809
810 __iram_odm_func__
811 boolean
config_phydm_switch_channel_8821c(struct dm_struct * dm,u8 central_ch)812 config_phydm_switch_channel_8821c(struct dm_struct *dm, u8 central_ch)
813 {
814 struct phydm_dig_struct *dig_t = &dm->dm_dig_table;
815 u32 rf_reg18, rf_reg_b8 = 0;
816 boolean rf_reg_status = true;
817
818 PHYDM_DBG(dm, ODM_PHY_CONFIG, "[%s]====================>\n", __func__);
819
820 if (dm->is_disable_phy_api) {
821 PHYDM_DBG(dm, ODM_PHY_CONFIG,
822 "[%s]: disable PHY API for debug!!\n", __func__);
823 return true;
824 }
825
826 central_ch_8821c = central_ch;
827 rf_reg18 = config_phydm_read_rf_reg_8821c(dm, RF_PATH_A, 0x18, RFREGOFFSETMASK);
828 rf_reg_status = rf_reg_status & config_phydm_read_rf_check_8821c(rf_reg18);
829
830 if (dm->cut_version == ODM_CUT_A) {
831 rf_reg_b8 = config_phydm_read_rf_reg_8821c(dm, RF_PATH_A, 0xb8, RFREGOFFSETMASK);
832 rf_reg_status = rf_reg_status & config_phydm_read_rf_check_8821c(rf_reg_b8);
833 }
834
835 /* Switch band and channel */
836 if (central_ch <= 14) {
837 /* 2.4G */
838
839 /* 1. RF band and channel*/
840 rf_reg18 = (rf_reg18 & (~(BIT(18) | BIT(17) | MASKBYTE0)));
841 rf_reg18 = (rf_reg18 | central_ch);
842
843 /* 2. AGC table selection */
844 odm_set_bb_reg(dm, R_0xc1c, 0x00000F00, 0x0);
845 dig_t->agc_table_idx = 0x0;
846
847 /* 3. Set central frequency for clock offset tracking */
848 odm_set_bb_reg(dm, R_0x860, 0x1ffe0000, 0x96a);
849
850 /* Fix A-cut LCK fail issue @ 5285MHz~5375MHz, 0xb8[19]=0x0 */
851 if (dm->cut_version == ODM_CUT_A)
852 rf_reg_b8 = rf_reg_b8 | BIT(19);
853
854 /* CCK TX filter parameters */
855 if (central_ch == 14) {
856 odm_set_bb_reg(dm, R_0xa24, MASKDWORD, 0x0000b81c);
857 odm_set_bb_reg(dm, R_0xa28, MASKLWORD, 0x0000);
858 odm_set_bb_reg(dm, R_0xaac, MASKDWORD, 0x00003667);
859 } else {
860 odm_set_bb_reg(dm, R_0xa24, MASKDWORD, rega24_8821c);
861 odm_set_bb_reg(dm, R_0xa28, MASKLWORD, (rega28_8821c & MASKLWORD));
862 odm_set_bb_reg(dm, R_0xaac, MASKDWORD, regaac_8821c);
863 }
864
865 } else if (central_ch > 35) {
866 /* 5G */
867
868 /* 1. RF band and channel*/
869 rf_reg18 = (rf_reg18 & (~(BIT(18) | BIT(17) | MASKBYTE0)));
870 rf_reg18 = (rf_reg18 | central_ch);
871
872 if (central_ch >= 36 && central_ch <= 64) {
873 ;
874 } else if ((central_ch >= 100) && (central_ch <= 140)) {
875 rf_reg18 = (rf_reg18 | BIT(17));
876 } else if (central_ch > 140) {
877 rf_reg18 = (rf_reg18 | BIT(18));
878 } else {
879 PHYDM_DBG(dm, ODM_PHY_CONFIG,
880 "[%s]: Fail to switch channel (RF18) (ch: %d)\n",
881 __func__, central_ch);
882 return false;
883 }
884
885 /* 2. AGC table selection */
886 if (central_ch >= 36 && central_ch <= 64) {
887 odm_set_bb_reg(dm, R_0xc1c, 0x00000F00, 0x1);
888 dig_t->agc_table_idx = 0x1;
889 } else if ((central_ch >= 100) && (central_ch <= 144)) {
890 odm_set_bb_reg(dm, R_0xc1c, 0x00000F00, 0x2);
891 dig_t->agc_table_idx = 0x2;
892 } else if (central_ch >= 149) {
893 odm_set_bb_reg(dm, R_0xc1c, 0x00000F00, 0x3);
894 dig_t->agc_table_idx = 0x3;
895 } else {
896 PHYDM_DBG(dm, ODM_PHY_CONFIG,
897 "[%s]: Fail to switch channel (AGC) (ch: %d)\n",
898 __func__, central_ch);
899 return false;
900 }
901
902 /* 3. Set central frequency for clock offset tracking */
903 if (central_ch >= 36 && central_ch <= 48) {
904 odm_set_bb_reg(dm, R_0x860, 0x1ffe0000, 0x494);
905 } else if ((central_ch >= 52) && (central_ch <= 64)) {
906 odm_set_bb_reg(dm, R_0x860, 0x1ffe0000, 0x453);
907 } else if ((central_ch >= 100) && (central_ch <= 116)) {
908 odm_set_bb_reg(dm, R_0x860, 0x1ffe0000, 0x452);
909 } else if ((central_ch >= 118) && (central_ch <= 177)) {
910 odm_set_bb_reg(dm, R_0x860, 0x1ffe0000, 0x412);
911 } else {
912 PHYDM_DBG(dm, ODM_PHY_CONFIG,
913 "[%s]: Fail to switch channel (fc_area) (ch: %d)\n",
914 __func__, central_ch);
915 return false;
916 }
917
918 /* Fix A-cut LCK fail issue @ 5285MHz~5375MHz, 0xb8[19]=0x0 */
919 if (dm->cut_version == ODM_CUT_A) {
920 if (central_ch >= 57 && central_ch <= 75)
921 rf_reg_b8 = rf_reg_b8 & (~BIT(19));
922 else
923 rf_reg_b8 = rf_reg_b8 | BIT(19);
924 }
925
926 #if (PHYDM_FW_API_FUNC_ENABLE_8821C == 1)
927 /*notch 5760 spur by CSI_MASK*/
928 if (central_ch == 153)
929 phydm_csi_mask_setting(dm, FUNC_ENABLE, (u32)central_ch, 20, 5760, PHYDM_DONT_CARE);
930 else if (central_ch == 151)
931 phydm_csi_mask_setting(dm, FUNC_ENABLE, (u32)central_ch, 40, 5760, PHYDM_DONT_CARE);
932 else if (central_ch == 155)
933 phydm_csi_mask_setting(dm, FUNC_ENABLE, (u32)central_ch, 80, 5760, PHYDM_DONT_CARE);
934 else
935 phydm_csi_mask_setting(dm, FUNC_DISABLE, (u32)central_ch, 80, 5760, PHYDM_DONT_CARE);
936 #endif
937
938 } else {
939 PHYDM_DBG(dm, ODM_PHY_CONFIG,
940 "[%s]: Fail to switch band (ch: %d)\n", __func__,
941 central_ch);
942 return false;
943 }
944
945 phydm_stop_ic_trx(dm, PHYDM_SET);
946 odm_set_rf_reg(dm, RF_PATH_A, RF_0x18, RFREGOFFSETMASK, rf_reg18);
947 phydm_stop_ic_trx(dm, PHYDM_REVERT);
948
949 if (dm->cut_version == ODM_CUT_A)
950 odm_set_rf_reg(dm, RF_PATH_A, RF_0xb8, RFREGOFFSETMASK, rf_reg_b8);
951
952 if (!rf_reg_status) {
953 PHYDM_DBG(dm, ODM_PHY_CONFIG,
954 "[%s]: Fail to switch channel (ch: %d), because writing RF register is fail\n",
955 __func__, central_ch);
956 return false;
957 }
958
959 /* Dynamic spur detection by PSD and NBI mask */
960 if (*dm->mp_mode)
961 phydm_dynamic_spur_det_eliminate_8821c(dm);
962
963 phydm_ccapar_8821c(dm);
964 PHYDM_DBG(dm, ODM_PHY_CONFIG,
965 "[%s]: Success to switch channel (ch: %d)\n", __func__,
966 central_ch);
967 return true;
968 }
969
970 __iram_odm_func__
971 boolean
config_phydm_switch_bandwidth_8821c(struct dm_struct * dm,u8 primary_ch_idx,enum channel_width bandwidth)972 config_phydm_switch_bandwidth_8821c(struct dm_struct *dm, u8 primary_ch_idx,
973 enum channel_width bandwidth)
974 {
975 struct phydm_api_stuc *api = &dm->api_table;
976 u32 rf_reg18;
977 boolean rf_reg_status = true;
978 u32 bb_reg8ac;
979
980 PHYDM_DBG(dm, ODM_PHY_CONFIG, "[%s]===================>\n", __func__);
981
982 if (dm->is_disable_phy_api) {
983 PHYDM_DBG(dm, ODM_PHY_CONFIG,
984 "[%s]: disable PHY API for debug!!\n", __func__);
985 return true;
986 }
987
988 /* Error handling */
989 if (bandwidth >= CHANNEL_WIDTH_MAX || (bandwidth == CHANNEL_WIDTH_40 && primary_ch_idx > 2) || (bandwidth == CHANNEL_WIDTH_80 && primary_ch_idx > 4)) {
990 PHYDM_DBG(dm, ODM_PHY_CONFIG,
991 "[%s]: Fail to switch bandwidth (bw: %d, primary ch: %d)\n",
992 __func__, bandwidth, primary_ch_idx);
993 return false;
994 }
995 /*Make protection*/
996 if (central_ch_8821c == 165 && !(*dm->mp_mode))
997 bandwidth = CHANNEL_WIDTH_20;
998
999 bw_8821c = bandwidth;
1000 api->pri_ch_idx = primary_ch_idx;
1001 rf_reg18 = config_phydm_read_rf_reg_8821c(dm, RF_PATH_A, 0x18, RFREGOFFSETMASK);
1002 rf_reg_status = rf_reg_status & config_phydm_read_rf_check_8821c(rf_reg18);
1003
1004 /* Switch bandwidth */
1005 switch (bandwidth) {
1006 case CHANNEL_WIDTH_20: {
1007 /* Small BW([7:6]) = 0, primary channel ([5:2]) = 0, rf mode([1:0]) = 20M */
1008 #if 0
1009 odm_set_bb_reg(dm, R_0x8ac, MASKBYTE0, CHANNEL_WIDTH_20);
1010
1011 /* ADC clock = 160M clock for BW20 */
1012 odm_set_bb_reg(dm, R_0x8ac, (BIT(9) | BIT(8)), 0x0);
1013 odm_set_bb_reg(dm, R_0x8ac, BIT(16), 0x1);
1014
1015 /* DAC clock = 160M clock for BW20 */
1016 odm_set_bb_reg(dm, R_0x8ac, (BIT(21) | BIT(20)), 0x0);
1017 odm_set_bb_reg(dm, R_0x8ac, BIT(28), 0x1);
1018 #endif
1019 bb_reg8ac = odm_get_bb_reg(dm, R_0x8ac, MASKDWORD);
1020 bb_reg8ac &= 0xffcffc00;
1021 bb_reg8ac |= 0x10010000;
1022 odm_set_bb_reg(dm, R_0x8ac, MASKDWORD, bb_reg8ac);
1023
1024 /* ADC buffer clock */
1025 odm_set_bb_reg(dm, R_0x8c4, BIT(30), 0x1);
1026
1027 /* RF bandwidth */
1028 rf_reg18 = (rf_reg18 | BIT(11) | BIT(10));
1029
1030 break;
1031 }
1032 case CHANNEL_WIDTH_40: {
1033 /* Small BW([7:6]) = 0, primary channel ([5:2]) = sub-channel, rf mode([1:0]) = 40M */
1034 /*odm_set_bb_reg(dm, R_0x8ac, MASKBYTE0, (((primary_ch_idx & 0xf) << 2) | CHANNEL_WIDTH_40));*/
1035
1036 /* CCK primary channel */
1037 if (primary_ch_idx == 1)
1038 odm_set_bb_reg(dm, R_0xa00, BIT(4), primary_ch_idx);
1039 else
1040 odm_set_bb_reg(dm, R_0xa00, BIT(4), 0);
1041 #if 0
1042 /* ADC clock = 160M clock for BW40 */
1043 odm_set_bb_reg(dm, R_0x8ac, (BIT(11) | BIT(10)), 0x0);
1044 odm_set_bb_reg(dm, R_0x8ac, BIT(17), 0x1);
1045
1046 /* DAC clock = 160M clock for BW20 */
1047 odm_set_bb_reg(dm, R_0x8ac, (BIT(23) | BIT(22)), 0x0);
1048 odm_set_bb_reg(dm, R_0x8ac, BIT(29), 0x1);
1049 #endif
1050 bb_reg8ac = odm_get_bb_reg(dm, R_0x8ac, MASKDWORD);
1051 bb_reg8ac &= 0xff3ff300;
1052 bb_reg8ac |= 0x20020000 | ((primary_ch_idx & 0xf) << 2) | CHANNEL_WIDTH_40;
1053 odm_set_bb_reg(dm, R_0x8ac, MASKDWORD, bb_reg8ac);
1054
1055 /* ADC buffer clock */
1056 odm_set_bb_reg(dm, R_0x8c4, BIT(30), 0x1);
1057
1058 /* RF bandwidth */
1059 rf_reg18 = (rf_reg18 & (~(BIT(11) | BIT(10))));
1060 rf_reg18 = (rf_reg18 | BIT(11));
1061
1062 break;
1063 }
1064 case CHANNEL_WIDTH_80: {
1065 /* Small BW([7:6]) = 0, primary channel ([5:2]) = sub-channel, rf mode([1:0]) = 80M */
1066 #if 0
1067 odm_set_bb_reg(dm, R_0x8ac, MASKBYTE0, (((primary_ch_idx & 0xf) << 2) | CHANNEL_WIDTH_80));
1068
1069 /* ADC clock = 160M clock for BW80 */
1070 odm_set_bb_reg(dm, R_0x8ac, (BIT(13) | BIT(12)), 0x0);
1071 odm_set_bb_reg(dm, R_0x8ac, BIT(18), 0x1);
1072
1073 /* DAC clock = 160M clock for BW20 */
1074 odm_set_bb_reg(dm, R_0x8ac, (BIT(25) | BIT(24)), 0x0);
1075 odm_set_bb_reg(dm, R_0x8ac, BIT(30), 0x1);
1076 #endif
1077 bb_reg8ac = odm_get_bb_reg(dm, R_0x8ac, MASKDWORD);
1078 bb_reg8ac &= 0xfcffcf00;
1079 bb_reg8ac |= 0x40040000 | ((primary_ch_idx & 0xf) << 2) | CHANNEL_WIDTH_80;
1080 odm_set_bb_reg(dm, R_0x8ac, MASKDWORD, bb_reg8ac);
1081
1082 /* ADC buffer clock */
1083 odm_set_bb_reg(dm, R_0x8c4, BIT(30), 0x1);
1084
1085 /* RF bandwidth */
1086 rf_reg18 = (rf_reg18 & (~(BIT(11) | BIT(10))));
1087 rf_reg18 = (rf_reg18 | BIT(10));
1088
1089 break;
1090 }
1091 case CHANNEL_WIDTH_5: {
1092 /* Small BW([7:6]) = 1, primary channel ([5:2]) = 0, rf mode([1:0]) = 20M */
1093 #if 0
1094 odm_set_bb_reg(dm, R_0x8ac, MASKBYTE0, (BIT(6) | CHANNEL_WIDTH_20));
1095
1096 /* ADC clock = 40M clock */
1097 odm_set_bb_reg(dm, R_0x8ac, (BIT(9) | BIT(8)), 0x2);
1098 odm_set_bb_reg(dm, R_0x8ac, BIT(16), 0x0);
1099
1100 /* DAC clock = 160M clock for BW20 */
1101 odm_set_bb_reg(dm, R_0x8ac, (BIT(21) | BIT(20)), 0x2);
1102 odm_set_bb_reg(dm, R_0x8ac, BIT(28), 0x0);
1103 #endif
1104 bb_reg8ac = odm_get_bb_reg(dm, R_0x8ac, MASKDWORD);
1105 bb_reg8ac &= 0xefcefc00;
1106 bb_reg8ac |= (0x2 << 20) | (0x2 << 8) | BIT(6);
1107 odm_set_bb_reg(dm, R_0x8ac, MASKDWORD, bb_reg8ac);
1108
1109 /* ADC buffer clock */
1110 odm_set_bb_reg(dm, R_0x8c4, BIT(30), 0x0);
1111 odm_set_bb_reg(dm, R_0x8c8, BIT(31), 0x1);
1112
1113 /* RF bandwidth */
1114 rf_reg18 = (rf_reg18 | BIT(11) | BIT(10));
1115
1116 break;
1117 }
1118 case CHANNEL_WIDTH_10: {
1119 /* Small BW([7:6]) = 1, primary channel ([5:2]) = 0, rf mode([1:0]) = 20M */
1120 #if 0
1121 odm_set_bb_reg(dm, R_0x8ac, MASKBYTE0, (BIT(7) | CHANNEL_WIDTH_20));
1122
1123 /* ADC clock = 80M clock */
1124 odm_set_bb_reg(dm, R_0x8ac, (BIT(9) | BIT(8)), 0x3);
1125 odm_set_bb_reg(dm, R_0x8ac, BIT(16), 0x0);
1126
1127 /* DAC clock = 160M clock for BW20 */
1128 odm_set_bb_reg(dm, R_0x8ac, (BIT(21) | BIT(20)), 0x3);
1129 odm_set_bb_reg(dm, R_0x8ac, BIT(28), 0x0);
1130 #endif
1131 bb_reg8ac = odm_get_bb_reg(dm, R_0x8ac, MASKDWORD);
1132 bb_reg8ac &= 0xefcefc00;
1133 bb_reg8ac |= (0x3 << 20) | (0x3 << 8) | BIT(7);
1134 odm_set_bb_reg(dm, R_0x8ac, MASKDWORD, bb_reg8ac);
1135
1136 /* ADC buffer clock */
1137 odm_set_bb_reg(dm, R_0x8c4, BIT(30), 0x0);
1138 odm_set_bb_reg(dm, R_0x8c8, BIT(31), 0x1);
1139
1140 /* RF bandwidth */
1141 rf_reg18 = (rf_reg18 | BIT(11) | BIT(10));
1142
1143 break;
1144 }
1145 default:
1146 PHYDM_DBG(dm, ODM_PHY_CONFIG,
1147 "[%s]: Fail to switch bandwidth (bw: %d, primary ch: %d)\n",
1148 __func__, bandwidth, primary_ch_idx);
1149 }
1150
1151 /* Write RF register */
1152 phydm_stop_ic_trx(dm, PHYDM_SET);
1153 odm_set_rf_reg(dm, RF_PATH_A, RF_0x18, RFREGOFFSETMASK, rf_reg18);
1154 phydm_stop_ic_trx(dm, PHYDM_REVERT);
1155
1156 if (!rf_reg_status) {
1157 PHYDM_DBG(dm, ODM_PHY_CONFIG,
1158 "[%s]: Fail to switch bandwidth (bw: %d, primary ch: %d), because writing RF register is fail\n",
1159 __func__, bandwidth, primary_ch_idx);
1160 return false;
1161 }
1162
1163 /* Modify RX DFIR parameters */
1164 phydm_rxdfirpar_by_bw_8821c(dm, bandwidth);
1165
1166 /* Modify CCA parameters */
1167 phydm_ccapar_by_bw_8821c(dm, bandwidth);
1168 phydm_ccapar_8821c(dm);
1169
1170 /* Toggle RX path to avoid RX dead zone issue */
1171 /*odm_set_bb_reg(dm, R_0x808, MASKBYTE0, 0x0);*/
1172 /*odm_set_bb_reg(dm, R_0x808, MASKBYTE0, 0x11);*/
1173
1174 /* Dynamic spur detection by PSD and NBI mask */
1175 if (*dm->mp_mode)
1176 phydm_dynamic_spur_det_eliminate_8821c(dm);
1177
1178 /*fix bw setting*/
1179 #ifdef CONFIG_BW_INDICATION
1180 if (!(*dm->mp_mode))
1181 phydm_bw_fixed_setting(dm);
1182 #endif
1183
1184 PHYDM_DBG(dm, ODM_PHY_CONFIG,
1185 "[%s]: Success to switch bandwidth (bw: %d, primary ch: %d)\n",
1186 __func__, bandwidth, primary_ch_idx);
1187 return true;
1188 }
1189
1190 __iram_odm_func__
1191 boolean
config_phydm_switch_channel_bw_8821c(struct dm_struct * dm,u8 central_ch,u8 primary_ch_idx,enum channel_width bandwidth)1192 config_phydm_switch_channel_bw_8821c(struct dm_struct *dm, u8 central_ch,
1193 u8 primary_ch_idx,
1194 enum channel_width bandwidth)
1195 {
1196 /* Switch band */
1197 if (config_phydm_switch_band_8821c(dm, central_ch) == false)
1198 return false;
1199
1200 /* Switch channel */
1201 if (config_phydm_switch_channel_8821c(dm, central_ch) == false)
1202 return false;
1203
1204 /* Switch bandwidth */
1205 if (config_phydm_switch_bandwidth_8821c(dm, primary_ch_idx, bandwidth) == false)
1206 return false;
1207
1208 return true;
1209 }
1210
1211 __iram_odm_func__
1212 boolean
config_phydm_trx_mode_8821c(struct dm_struct * dm,enum bb_path tx_path,enum bb_path rx_path,boolean is_tx2_path)1213 config_phydm_trx_mode_8821c(struct dm_struct *dm, enum bb_path tx_path,
1214 enum bb_path rx_path, boolean is_tx2_path)
1215 {
1216 return true;
1217 }
1218
1219 __iram_odm_func__
1220 boolean
config_phydm_parameter_init_8821c(struct dm_struct * dm,enum odm_parameter_init type)1221 config_phydm_parameter_init_8821c(struct dm_struct *dm,
1222 enum odm_parameter_init type)
1223 {
1224 if (type == ODM_PRE_SETTING) {
1225 odm_set_bb_reg(dm, R_0x808, (BIT(28) | BIT(29)), 0x0);
1226 PHYDM_DBG(dm, ODM_PHY_CONFIG,
1227 "[%s]: Pre setting: disable OFDM and CCK block\n",
1228 __func__);
1229 } else if (type == ODM_POST_SETTING) {
1230 odm_set_bb_reg(dm, R_0x808, (BIT(28) | BIT(29)), 0x3);
1231 PHYDM_DBG(dm, ODM_PHY_CONFIG,
1232 "[%s]: Post setting: enable OFDM and CCK block\n",
1233 __func__);
1234 rega24_8821c = odm_get_bb_reg(dm, R_0xa24, MASKDWORD);
1235 rega28_8821c = odm_get_bb_reg(dm, R_0xa28, MASKDWORD);
1236 regaac_8821c = odm_get_bb_reg(dm, R_0xaac, MASKDWORD);
1237 } else {
1238 PHYDM_DBG(dm, ODM_PHY_CONFIG, "[%s]: Wrong type!!\n", __func__);
1239 return false;
1240 }
1241
1242 return true;
1243 }
1244
1245 __iram_odm_func__
config_phydm_switch_rf_set_8821c(struct dm_struct * dm,u8 rf_set)1246 void config_phydm_switch_rf_set_8821c(struct dm_struct *dm, u8 rf_set)
1247 {
1248 #if (PHYDM_FW_API_FUNC_ENABLE_8821C == 1)
1249 #if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
1250 void *adapter = dm->adapter;
1251 PMGNT_INFO mgnt_info = &(((PADAPTER)(adapter))->MgntInfo);
1252 #endif
1253
1254 u32 bb_reg32;
1255
1256 odm_set_bb_reg(dm, R_0x1080, BIT(16), 0x1);
1257 odm_set_bb_reg(dm, R_0x00, BIT(26), 0x1);
1258 /*odm_set_mac_reg(dm, R_0x70, BIT(26), 0x1);*/
1259 /*odm_set_mac_reg(dm, R_0x1704, MASKLWORD, 0x4000);*/
1260 /*odm_set_mac_reg(dm, R_0x1700, (BIT(31) | BIT(30)), 0x3); */
1261
1262 bb_reg32 = odm_get_bb_reg(dm, R_0xcb8, MASKDWORD);
1263 switch (rf_set) {
1264 case SWITCH_TO_BTG:
1265
1266 dm->current_rf_set_8821c = SWITCH_TO_BTG;
1267
1268 bb_reg32 = (bb_reg32 | BIT(16));
1269 bb_reg32 &= (~(BIT(18) | BIT(20) | BIT(21) | BIT(22) | BIT(23)));
1270 odm_set_bb_reg(dm, R_0xa84, MASKBYTE2, 0xe);
1271 odm_set_bb_reg(dm, R_0xa80, MASKLWORD, 0xfc84);
1272
1273 #if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
1274 if (*dm->mp_mode && mgnt_info->RegPHYParaFromFolder == 0)
1275 #else
1276 if (*dm->mp_mode)
1277 #endif
1278 {
1279 odm_set_bb_reg(dm, R_0xaa8, 0x1f0000, 0x14);
1280 odm_config_bb_with_header_file(dm, CONFIG_BB_AGC_TAB_DIFF);
1281 /*Toggle initial gain twice for valid gain table*/
1282 odm_set_bb_reg(dm, ODM_REG(IGI_A, dm), ODM_BIT(IGI, dm), 0x22);
1283 odm_set_bb_reg(dm, ODM_REG(IGI_A, dm), ODM_BIT(IGI, dm), 0x20);
1284 }
1285 break;
1286 case SWITCH_TO_WLG:
1287
1288 dm->current_rf_set_8821c = SWITCH_TO_WLG;
1289
1290 bb_reg32 = (bb_reg32 | BIT(20) | BIT(21) | BIT(22));
1291 bb_reg32 &= (~(BIT(16) | BIT(18) | BIT(23)));
1292 odm_set_bb_reg(dm, R_0xa84, MASKBYTE2, 0x12);
1293 odm_set_bb_reg(dm, R_0xa80, MASKLWORD, 0x7532);
1294
1295 #if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
1296 if (*dm->mp_mode && mgnt_info->RegPHYParaFromFolder == 0)
1297 #else
1298 if (*dm->mp_mode)
1299 #endif
1300 {
1301 odm_set_bb_reg(dm, R_0xaa8, 0x1f0000, 0x13);
1302 odm_config_bb_with_header_file(dm, CONFIG_BB_AGC_TAB_DIFF);
1303 /*Toggle initial gain twice for valid gain table*/
1304 odm_set_bb_reg(dm, ODM_REG(IGI_A, dm), ODM_BIT(IGI, dm), 0x22);
1305 odm_set_bb_reg(dm, ODM_REG(IGI_A, dm), ODM_BIT(IGI, dm), 0x20);
1306 }
1307 break;
1308 case SWITCH_TO_WLA:
1309
1310 dm->current_rf_set_8821c = SWITCH_TO_WLA;
1311
1312 bb_reg32 = (bb_reg32 | BIT(20) | BIT(22) | BIT(23));
1313 bb_reg32 &= (~(BIT(16) | BIT(18) | BIT(21)));
1314
1315 break;
1316 case SWITCH_TO_BT:
1317
1318 dm->current_rf_set_8821c = SWITCH_TO_BT;
1319
1320 break;
1321 default:
1322 break;
1323 }
1324
1325 odm_set_bb_reg(dm, R_0xcb8, MASKDWORD, bb_reg32);
1326 #endif
1327 }
1328
1329 __iram_odm_func__
config_phydm_set_ant_path(struct dm_struct * dm,u8 rf_set,u8 ant_num)1330 void config_phydm_set_ant_path(struct dm_struct *dm, u8 rf_set, u8 ant_num)
1331 {
1332 #if (PHYDM_FW_API_FUNC_ENABLE_8821C == 1)
1333 boolean switch_polarity_inverse = false;
1334 u8 regval_0xcb7 = 0;
1335
1336 dm->current_ant_num_8821c = ant_num;
1337 config_phydm_switch_rf_set_8821c(dm, rf_set);
1338
1339 if (rf_set == SWITCH_TO_BT)
1340 phydm_set_gnt_state_8821c(dm, false, true); /* GNT_WL=0, GNT_BT=1 for BT test */
1341 else
1342 phydm_set_gnt_state_8821c(dm, true, false); /* GNT_WL=1, GNT_BT=0 for WL test */
1343
1344 /*switch does not exist*/
1345 if (dm->rfe_type_expand == 0x5 || dm->rfe_type_expand == 0x6 ||
1346 dm->rfe_type_expand == 0x25 || dm->rfe_type_expand == 0x26 ||
1347 dm->rfe_type_expand == 0x2a || dm->rfe_type_expand == 0x2d ||
1348 dm->rfe_type_expand == 0x2e)
1349 return;
1350
1351 if (dm->current_ant_num_8821c) /*Ant1 = 0, Ant2 = 1*/
1352 switch_polarity_inverse = !switch_polarity_inverse;
1353
1354 if (rf_set == SWITCH_TO_WLG)
1355 switch_polarity_inverse = !switch_polarity_inverse;
1356
1357 /*set antenna control by WL 0xcb4[29:28]*/
1358 odm_set_bb_reg(dm, R_0x4c, BIT(24) | BIT(23), 0x2);
1359
1360 /*set RFE_ctrl8 and RFE_ctrl9 as antenna control pins by software*/
1361 odm_set_bb_reg(dm, R_0xcb4, 0x000000ff, 0x77);
1362
1363 /*0xcb4[29:28] = 2b'01 for no switch_polatiry_inverse, DPDT_SEL_N =1, DPDT_SEL_P =0*/
1364 regval_0xcb7 = (!switch_polarity_inverse ? 0x1 : 0x2);
1365
1366 odm_set_bb_reg(dm, R_0xcb4, 0x30000000, regval_0xcb7);
1367 #endif
1368 }
1369
1370 __iram_odm_func__
query_phydm_trx_capability_8821c(struct dm_struct * dm)1371 u32 query_phydm_trx_capability_8821c(struct dm_struct *dm)
1372 {
1373 #if (PHYDM_FW_API_FUNC_ENABLE_8821C == 1)
1374 u32 value32 = 0x00000000;
1375
1376 PHYDM_DBG(dm, ODM_PHY_CONFIG, "[%s]: trx_capability = 0x%x\n", __func__,
1377 value32);
1378 return value32;
1379 #else
1380 return 0;
1381 #endif
1382 }
1383
1384 __iram_odm_func__
query_phydm_stbc_capability_8821c(struct dm_struct * dm)1385 u32 query_phydm_stbc_capability_8821c(struct dm_struct *dm)
1386 {
1387 #if (PHYDM_FW_API_FUNC_ENABLE_8821C == 1)
1388 u32 value32 = 0x00010001;
1389
1390 PHYDM_DBG(dm, ODM_PHY_CONFIG, "[%s]: stbc_capability = 0x%x\n",
1391 __func__, value32);
1392 return value32;
1393 #else
1394 return 0;
1395 #endif
1396 }
1397
1398 __iram_odm_func__
query_phydm_ldpc_capability_8821c(struct dm_struct * dm)1399 u32 query_phydm_ldpc_capability_8821c(struct dm_struct *dm)
1400 {
1401 #if (PHYDM_FW_API_FUNC_ENABLE_8821C == 1)
1402 u32 value32 = 0x01000100;
1403
1404 PHYDM_DBG(dm, ODM_PHY_CONFIG, "[%s]: ldpc_capability = 0x%x\n",
1405 __func__, value32);
1406 return value32;
1407 #else
1408 return 0;
1409 #endif
1410 }
1411
1412 __iram_odm_func__
query_phydm_txbf_parameters_8821c(struct dm_struct * dm)1413 u32 query_phydm_txbf_parameters_8821c(struct dm_struct *dm)
1414 {
1415 #if (PHYDM_FW_API_FUNC_ENABLE_8821C == 1)
1416 u32 value32 = 0x00030003;
1417
1418 PHYDM_DBG(dm, ODM_PHY_CONFIG, "[%s]: txbf_parameters = 0x%x\n",
1419 __func__, value32);
1420 return value32;
1421 #else
1422 return 0;
1423 #endif
1424 }
1425
1426 __iram_odm_func__
query_phydm_txbf_capability_8821c(struct dm_struct * dm)1427 u32 query_phydm_txbf_capability_8821c(struct dm_struct *dm)
1428 {
1429 #if (PHYDM_FW_API_FUNC_ENABLE_8821C == 1)
1430 u32 value32 = 0x01010001;
1431
1432 PHYDM_DBG(dm, ODM_PHY_CONFIG, "[%s]: txbf_capability = 0x%x\n",
1433 __func__, value32);
1434 return value32;
1435 #else
1436 return 0;
1437 #endif
1438 }
1439
1440 __iram_odm_func__
query_phydm_default_rf_set_8821c(struct dm_struct * dm)1441 u8 query_phydm_default_rf_set_8821c(struct dm_struct *dm)
1442 {
1443 #if (PHYDM_FW_API_FUNC_ENABLE_8821C == 1)
1444 return dm->default_rf_set_8821c;
1445 #else
1446 return 0;
1447 #endif
1448 }
1449
1450 __iram_odm_func__
query_phydm_current_rf_set_8821c(struct dm_struct * dm)1451 u8 query_phydm_current_rf_set_8821c(struct dm_struct *dm)
1452 {
1453 #if (PHYDM_FW_API_FUNC_ENABLE_8821C == 1)
1454 return dm->current_rf_set_8821c;
1455 #else
1456 return 0;
1457 #endif
1458 }
1459
1460 __iram_odm_func__
query_phydm_rfetype_8821c(struct dm_struct * dm)1461 u8 query_phydm_rfetype_8821c(struct dm_struct *dm)
1462 {
1463 #if (PHYDM_FW_API_FUNC_ENABLE_8821C == 1)
1464 return dm->rfe_type_expand;
1465 #else
1466 return 0;
1467 #endif
1468 }
1469
1470 __iram_odm_func__
query_phydm_current_ant_num_8821c(struct dm_struct * dm)1471 u8 query_phydm_current_ant_num_8821c(struct dm_struct *dm)
1472 {
1473 #if (PHYDM_FW_API_FUNC_ENABLE_8821C == 1)
1474 u32 regval_0xcb4 = odm_get_bb_reg(dm, R_0xcb4, BIT(29) | BIT(28));
1475
1476 if (dm->current_rf_set_8821c == SWITCH_TO_BTG || dm->current_rf_set_8821c == SWITCH_TO_WLA || dm->current_rf_set_8821c == SWITCH_TO_BT) {
1477 if (regval_0xcb4 == 1)
1478 dm->current_ant_num_8821c = SWITCH_TO_ANT1;
1479 else if (regval_0xcb4 == 2)
1480 dm->current_ant_num_8821c = SWITCH_TO_ANT2;
1481 else if (regval_0xcb4 == 1)
1482 dm->current_ant_num_8821c = SWITCH_TO_ANT2;
1483 else if (regval_0xcb4 == 2)
1484 dm->current_ant_num_8821c = SWITCH_TO_ANT1;
1485 }
1486
1487 return dm->current_ant_num_8821c;
1488 #else
1489 return 0;
1490 #endif
1491 }
1492
1493 __iram_odm_func__
query_phydm_ant_num_map_8821c(struct dm_struct * dm)1494 u8 query_phydm_ant_num_map_8821c(struct dm_struct *dm)
1495 {
1496 #if (PHYDM_FW_API_FUNC_ENABLE_8821C == 1)
1497 u8 mapping_table = 0;
1498
1499 /* mapping table meaning
1500 * 1: choose ant1 or ant2
1501 * 2: only ant1
1502 * 3: only ant2
1503 * 4: cannot choose
1504 */
1505
1506 if (dm->rfe_type_expand == 0 || dm->rfe_type_expand == 7 || dm->rfe_type_expand == 0x20 ||
1507 dm->rfe_type_expand == 0x27 || dm->rfe_type_expand == 0x28 || dm->rfe_type_expand == 0x2f)
1508 mapping_table = 1;
1509 else if (dm->rfe_type_expand == 1 || dm->rfe_type_expand == 2 || dm->rfe_type_expand == 0x21 ||
1510 dm->rfe_type_expand == 0x22 || dm->rfe_type_expand == 0x29 || dm->rfe_type_expand == 0x2a)
1511 mapping_table = 2;
1512 else if (dm->rfe_type_expand == 3 || dm->rfe_type_expand == 4 || dm->rfe_type_expand == 0x23 ||
1513 dm->rfe_type_expand == 0x24 || dm->rfe_type_expand == 0x2b || dm->rfe_type_expand == 0x2c)
1514 mapping_table = 3;
1515 else if (dm->rfe_type_expand == 5 || dm->rfe_type_expand == 6 || dm->rfe_type_expand == 0x25 ||
1516 dm->rfe_type_expand == 0x26 || dm->rfe_type_expand == 0x2d || dm->rfe_type_expand == 0x2e)
1517 mapping_table = 4;
1518
1519 return mapping_table;
1520 #else
1521 return 0;
1522 #endif
1523 }
1524
1525 /* ======================================================================== */
1526 #endif /*PHYDM_FW_API_ENABLE_8821C == 1*/
1527 #endif /* RTL8821C_SUPPORT == 1 */
1528