1*4882a593SmuzhiyunNXP LPC32xx SoC NAND SLC controller 2*4882a593Smuzhiyun 3*4882a593SmuzhiyunRequired properties: 4*4882a593Smuzhiyun- compatible: "nxp,lpc3220-slc" 5*4882a593Smuzhiyun- reg: Address and size of the controller 6*4882a593Smuzhiyun- nand-on-flash-bbt: Use bad block table on flash 7*4882a593Smuzhiyun- gpios: GPIO specification for NAND write protect 8*4882a593Smuzhiyun 9*4882a593SmuzhiyunThe following required properties are very controller specific. See the LPC32xx 10*4882a593SmuzhiyunUser Manual: 11*4882a593Smuzhiyun- nxp,wdr-clks: Delay before Ready signal is tested on write (W_RDY) 12*4882a593Smuzhiyun- nxp,rdr-clks: Delay before Ready signal is tested on read (R_RDY) 13*4882a593Smuzhiyun(The following values are specified in Hz, to make them independent of actual 14*4882a593Smuzhiyunclock speed:) 15*4882a593Smuzhiyun- nxp,wwidth: Write pulse width (W_WIDTH) 16*4882a593Smuzhiyun- nxp,whold: Write hold time (W_HOLD) 17*4882a593Smuzhiyun- nxp,wsetup: Write setup time (W_SETUP) 18*4882a593Smuzhiyun- nxp,rwidth: Read pulse width (R_WIDTH) 19*4882a593Smuzhiyun- nxp,rhold: Read hold time (R_HOLD) 20*4882a593Smuzhiyun- nxp,rsetup: Read setup time (R_SETUP) 21*4882a593Smuzhiyun 22*4882a593SmuzhiyunOptional subnodes: 23*4882a593Smuzhiyun- Partitions, see Documentation/devicetree/bindings/mtd/partition.txt 24*4882a593Smuzhiyun 25*4882a593SmuzhiyunExample: 26*4882a593Smuzhiyun 27*4882a593Smuzhiyun slc: flash@20020000 { 28*4882a593Smuzhiyun compatible = "nxp,lpc3220-slc"; 29*4882a593Smuzhiyun reg = <0x20020000 0x1000>; 30*4882a593Smuzhiyun #address-cells = <1>; 31*4882a593Smuzhiyun #size-cells = <1>; 32*4882a593Smuzhiyun 33*4882a593Smuzhiyun nxp,wdr-clks = <14>; 34*4882a593Smuzhiyun nxp,wwidth = <40000000>; 35*4882a593Smuzhiyun nxp,whold = <100000000>; 36*4882a593Smuzhiyun nxp,wsetup = <100000000>; 37*4882a593Smuzhiyun nxp,rdr-clks = <14>; 38*4882a593Smuzhiyun nxp,rwidth = <40000000>; 39*4882a593Smuzhiyun nxp,rhold = <66666666>; 40*4882a593Smuzhiyun nxp,rsetup = <100000000>; 41*4882a593Smuzhiyun nand-on-flash-bbt; 42*4882a593Smuzhiyun gpios = <&gpio 5 19 1>; /* GPO_P3 19, active low */ 43*4882a593Smuzhiyun 44*4882a593Smuzhiyun mtd0@00000000 { 45*4882a593Smuzhiyun label = "phy3250-boot"; 46*4882a593Smuzhiyun reg = <0x00000000 0x00064000>; 47*4882a593Smuzhiyun read-only; 48*4882a593Smuzhiyun }; 49*4882a593Smuzhiyun 50*4882a593Smuzhiyun ... 51*4882a593Smuzhiyun 52*4882a593Smuzhiyun }; 53