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/OK3568_Linux_fs/u-boot/arch/arm/mach-socfpga/include/mach/
H A Dclock_manager_gen5.h136 #define CLKMGR_CTRL_SAFEMODE BIT(0)
137 #define CLKMGR_CTRL_SAFEMODE_OFFSET 0
147 #define CLKMGR_BYPASS_MAINPLL BIT(0)
148 #define CLKMGR_BYPASS_MAINPLL_OFFSET 0
157 #define CLKMGR_STAT_BUSY BIT(0)
160 #define CLKMGR_MAINPLLGRP_VCO_BGPWRDN BIT(0)
161 #define CLKMGR_MAINPLLGRP_VCO_BGPWRDN_OFFSET 0
163 #define CLKMGR_MAINPLLGRP_VCO_DENOM_MASK 0x003f0000
167 #define CLKMGR_MAINPLLGRP_VCO_NUMER_MASK 0x0000fff8
168 #define CLKMGR_MAINPLLGRP_VCO_OUTRESETALL_MASK 0x01000000
[all …]
/OK3568_Linux_fs/u-boot/arch/powerpc/include/asm/
H A Dfsl_dma.h17 #define FSL_DMA_MR_CS 0x00000001 /* Channel start */
18 #define FSL_DMA_MR_CC 0x00000002 /* Channel continue */
19 #define FSL_DMA_MR_CTM 0x00000004 /* Channel xfer mode */
20 #define FSL_DMA_MR_CTM_DIRECT 0x00000004 /* Direct channel xfer mode */
21 #define FSL_DMA_MR_EOTIE 0x00000080 /* End-of-transfer interrupt en */
22 #define FSL_DMA_MR_PRC_MASK 0x00000c00 /* PCI read command */
23 #define FSL_DMA_MR_SAHE 0x00001000 /* Source addr hold enable */
24 #define FSL_DMA_MR_DAHE 0x00002000 /* Dest addr hold enable */
25 #define FSL_DMA_MR_SAHTS_MASK 0x0000c000 /* Source addr hold xfer size */
26 #define FSL_DMA_MR_DAHTS_MASK 0x00030000 /* Dest addr hold xfer size */
[all …]
/OK3568_Linux_fs/kernel/drivers/gpu/drm/nouveau/nvkm/engine/gr/
H A Dgk110.c38 { 0x40415c, 1, 0x04, 0x00000000 },
39 { 0x404170, 1, 0x04, 0x00000000 },
40 { 0x4041b4, 1, 0x04, 0x00000000 },
46 { 0x405844, 1, 0x04, 0x00ffffff },
47 { 0x405850, 1, 0x04, 0x00000000 },
48 { 0x405900, 1, 0x04, 0x0000ff00 },
49 { 0x405908, 1, 0x04, 0x00000000 },
50 { 0x405928, 2, 0x04, 0x00000000 },
56 { 0x407010, 1, 0x04, 0x00000000 },
57 { 0x407040, 1, 0x04, 0x80440424 },
[all …]
/OK3568_Linux_fs/kernel/arch/nds32/kernel/
H A Dmodule.c13 GFP_KERNEL, PAGE_KERNEL, 0, NUMA_NO_NODE, in module_alloc()
14 __builtin_return_address(0)); in module_alloc()
26 return 0; in module_frob_arch_sections()
33 unsigned int tmp = 0, tmp2 = 0; in do_reloc16()
35 __asm__ __volatile__("\tlhi.bi\t%0, [%2], 0\n" in do_reloc16()
37 "\twsbh\t%0, %1\n" in do_reloc16()
38 "1:\n":"=r"(tmp):"0"(tmp), "r"(loc), "r"(swap) in do_reloc16()
51 "\twsbh\t%0, %1\n" in do_reloc16()
53 "\tshi.bi\t%0, [%2], 0\n":"=r"(tmp):"0"(tmp), in do_reloc16()
62 unsigned int tmp = 0, tmp2 = 0; in do_reloc32()
[all …]
/OK3568_Linux_fs/kernel/sound/drivers/vx/
H A Dvx_uer.c27 rmh.Cmd[0] |= CMD_MODIFY_CLOCK_S_BIT; in vx_modify_board_clock()
39 rmh.Cmd[0] |= 1 << 0; /* reference: AUDIO 0 */ in vx_modify_board_inputs()
46 * returns 0 or 1.
56 val = (vx_inb(chip, RUER) >> 7) & 0x01; in vx_read_one_cbit()
60 val = (vx_inl(chip, RUER) >> 7) & 0x01; in vx_read_one_cbit()
69 * @val: bit value, 0 or 1
73 val = !!val; /* 0 or 1 */ in vx_write_one_cbit()
76 vx_outb(chip, CSUER, 0); /* write */ in vx_write_one_cbit()
79 vx_outl(chip, CSUER, 0); /* write */ in vx_write_one_cbit()
89 * returns the frequency of UER, or 0 if not sync,
[all …]
H A Dvx_cmd.h86 #define CODE_OP_PIPE_TIME 0x004e0000
87 #define CODE_OP_START_STREAM 0x00800000
88 #define CODE_OP_PAUSE_STREAM 0x00810000
89 #define CODE_OP_OUT_STREAM_LEVEL 0x00820000
90 #define CODE_OP_UPDATE_R_BUFFERS 0x00840000
91 #define CODE_OP_OUT_STREAM1_LEVEL_CURVE 0x00850000
92 #define CODE_OP_OUT_STREAM2_LEVEL_CURVE 0x00930000
93 #define CODE_OP_OUT_STREAM_FORMAT 0x00860000
94 #define CODE_OP_STREAM_TIME 0x008f0000
95 #define CODE_OP_OUT_STREAM_EXTRAPARAMETER 0x00910000
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/OK3568_Linux_fs/kernel/Documentation/devicetree/bindings/watchdog/
H A Dsnps,dw-wdt.yaml52 default: [0x0001000 0x0002000 0x0004000 0x0008000
53 0x0010000 0x0020000 0x0040000 0x0080000
54 0x0100000 0x0200000 0x0400000 0x0800000
55 0x1000000 0x2000000 0x4000000 0x8000000]
70 reg = <0xffd02000 0x1000>;
71 interrupts = <0 171 4>;
79 reg = <0xffd02000 0x1000>;
80 interrupts = <0 171 4>;
83 snps,watchdog-tops = <0x000000FF 0x000001FF 0x000003FF
84 0x000007FF 0x0000FFFF 0x0001FFFF
[all …]
/OK3568_Linux_fs/kernel/arch/arm/include/asm/
H A Dv7m.h5 #define V7M_SCS_ICTR IOMEM(0xe000e004)
6 #define V7M_SCS_ICTR_INTLINESNUM_MASK 0x0000000f
8 #define BASEADDR_V7M_SCB IOMEM(0xe000ed00)
10 #define V7M_SCB_CPUID 0x00
12 #define V7M_SCB_ICSR 0x04
17 #define V7M_SCB_VTOR 0x08
19 #define V7M_SCB_AIRCR 0x0c
20 #define V7M_SCB_AIRCR_VECTKEY (0x05fa << 16)
23 #define V7M_SCB_SCR 0x10
26 #define V7M_SCB_CCR 0x14
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/OK3568_Linux_fs/kernel/drivers/gpu/drm/via/
H A Dvia_3d_reg.h27 #define HC_REG_BASE 0x0400
29 #define HC_REG_TRANS_SPACE 0x0040
31 #define HC_ParaN_MASK 0xffffffff
32 #define HC_Para_MASK 0x00ffffff
33 #define HC_SubA_MASK 0xff000000
37 #define HC_REG_TRANS_SET 0x003c
38 #define HC_ParaSubType_MASK 0xff000000
39 #define HC_ParaType_MASK 0x00ff0000
40 #define HC_ParaOS_MASK 0x0000ff00
41 #define HC_ParaAdr_MASK 0x000000ff
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/OK3568_Linux_fs/kernel/drivers/gpu/drm/nouveau/include/nvhw/class/
H A Dcl907d.h27 #define NV907D_CORE_NOTIFIER_3_CAPABILITIES_4 0x00000004
28 #define NV907D_CORE_NOTIFIER_3_CAPABILITIES_4_DONE 0:0
29 #define NV907D_CORE_NOTIFIER_3_CAPABILITIES_4_DONE_FALSE 0x00000000
30 #define NV907D_CORE_NOTIFIER_3_CAPABILITIES_4_DONE_TRUE 0x00000001
31 #define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20 0x00000014
32 #define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_SINGLE_LVDS18 0:0
33 #define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_SINGLE_LVDS18_FALSE 0x00000000
34 #define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_SINGLE_LVDS18_TRUE 0x00000001
36 #define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_SINGLE_LVDS24_FALSE 0x00000000
37 #define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_SINGLE_LVDS24_TRUE 0x00000001
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/OK3568_Linux_fs/kernel/drivers/net/wireless/mediatek/mt76/mt76x2/
H A Dinit.c57 (FIELD_PREP(MT_PROT_CFG_RATE, 0x3) | \ in mt76_write_mac_initvals()
59 FIELD_PREP(MT_PROT_CFG_TXOP_ALLOW, 0x3f) | \ in mt76_write_mac_initvals()
63 (FIELD_PREP(MT_PROT_CFG_RATE, 0x2004) | \ in mt76_write_mac_initvals()
65 FIELD_PREP(MT_PROT_CFG_TXOP_ALLOW, 0x3f) | \ in mt76_write_mac_initvals()
69 (FIELD_PREP(MT_PROT_CFG_RATE, 0x2004) | \ in mt76_write_mac_initvals()
72 FIELD_PREP(MT_PROT_CFG_TXOP_ALLOW, 0x17)) in mt76_write_mac_initvals()
75 (FIELD_PREP(MT_PROT_CFG_RATE, 0x2084) | \ in mt76_write_mac_initvals()
78 FIELD_PREP(MT_PROT_CFG_TXOP_ALLOW, 0x3f)) in mt76_write_mac_initvals()
82 { MT_PBF_SYS_CTRL, 0x00080c00 }, in mt76_write_mac_initvals()
83 { MT_PBF_CFG, 0x1efebcff }, in mt76_write_mac_initvals()
[all …]
/OK3568_Linux_fs/u-boot/drivers/usb/eth/
H A Dlan7x.h11 #define USB_VENDOR_REQUEST_WRITE_REGISTER 0xA0
12 #define USB_VENDOR_REQUEST_READ_REGISTER 0xA1
13 #define USB_VENDOR_REQUEST_GET_STATS 0xA2
17 #define TX_CMD_A_LEN_MASK 0x000FFFFF
21 #define RX_CMD_A_LEN_MASK 0x00003FFF
24 #define ID_REV 0x00
25 #define ID_REV_CHIP_ID_MASK 0xFFFF0000
26 #define ID_REV_CHIP_ID_7500 0x7500
27 #define ID_REV_CHIP_ID_7800 0x7800
28 #define ID_REV_CHIP_ID_7850 0x7850
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/OK3568_Linux_fs/kernel/arch/mips/include/asm/mach-au1x00/
H A Dau1100_mmc.h52 #define SD0_BASE 0xB0600000
53 #define SD1_BASE 0xB0680000
59 #define SD_TXPORT (0x0000)
60 #define SD_RXPORT (0x0004)
61 #define SD_CONFIG (0x0008)
62 #define SD_ENABLE (0x000C)
63 #define SD_CONFIG2 (0x0010)
64 #define SD_BLKSIZE (0x0014)
65 #define SD_STATUS (0x0018)
66 #define SD_DEBUG (0x001C)
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/OK3568_Linux_fs/kernel/sound/pci/pcxhr/
H A Dpcxhr_core.h26 #define PCXHR_DSP_TIME_MASK 0x00ffffff
27 #define PCXHR_DSP_TIME_INVALID 0x10000000
47 CMD_SEND_IRQA, /* cmd_len = 1 stat_len = 0 */
51 CMD_MODIFY_CLOCK, /* cmd_len = 3 stat_len = 0 */
52 CMD_RESYNC_AUDIO_INPUTS, /* cmd_len = 1 stat_len = 0 */
54 CMD_SET_TIMER_INTERRUPT, /* cmd_len = 1 stat_len = 0 */
55 CMD_RES_PIPE, /* cmd_len >=2 stat_len = 0 */
56 CMD_FREE_PIPE, /* cmd_len = 1 stat_len = 0 */
57 CMD_CONF_PIPE, /* cmd_len = 2 stat_len = 0 */
58 CMD_STOP_PIPE, /* cmd_len = 1 stat_len = 0 */
[all …]
/OK3568_Linux_fs/u-boot/tools/
H A Dvybridimage.c17 * NAND page 0 boot header
24 }; /* 0x00000000 - 0x000001ff */
25 uint8_t sw_ecc[512]; /* 0x00000200 - 0x000003ff */
26 uint32_t padding[65280]; /* 0x00000400 - 0x0003ffff */
27 uint8_t ivt_prefix[1024]; /* 0x00040000 - 0x000403ff */
43 uint8_t bit0 = (byte & (1 << 0)) ? 1 : 0; in vybridimage_sw_ecc()
44 uint8_t bit1 = (byte & (1 << 1)) ? 1 : 0; in vybridimage_sw_ecc()
45 uint8_t bit2 = (byte & (1 << 2)) ? 1 : 0; in vybridimage_sw_ecc()
46 uint8_t bit3 = (byte & (1 << 3)) ? 1 : 0; in vybridimage_sw_ecc()
47 uint8_t bit4 = (byte & (1 << 4)) ? 1 : 0; in vybridimage_sw_ecc()
[all …]
/OK3568_Linux_fs/kernel/drivers/gpu/drm/amd/amdkfd/
H A Dcwsr_trap_handler.h24 0xbf820001, 0xbf820121,
25 0xb8f4f802, 0x89748674,
26 0xb8f5f803, 0x8675ff75,
27 0x00000400, 0xbf850017,
28 0xc00a1e37, 0x00000000,
29 0xbf8c007f, 0x87777978,
30 0xbf840005, 0x8f728374,
31 0xb972e0c2, 0xbf800002,
32 0xb9740002, 0xbe801d78,
33 0xb8f5f803, 0x8675ff75,
[all …]
/OK3568_Linux_fs/external/rkwifibt/drivers/rtl8852bs/phl/hal_g6/phy/rf/halrf_8852b/
H A Dhalrf_tssi_8852b.c28 for (i = 0; i < reg_num; i++) { in _tssi_backup_bb_registers_8852b()
31 RF_DBG(rf, DBG_RF_TX_PWR_TRACK, "[TSSI] Backup BB 0x%x = 0x%x\n", in _tssi_backup_bb_registers_8852b()
46 for (i = 0; i < reg_num; i++) { in _tssi_reload_bb_registers_8852b()
49 RF_DBG(rf, DBG_RF_TX_PWR_TRACK, "[TSSI] Reload BB 0x%x = 0x%x\n", in _tssi_reload_bb_registers_8852b()
67 channelIndex = 0; in _halrf_ch_to_idx()
76 if (idx >= 0 && idx <= 13) in _halrf_idx_to_ch()
78 else if (idx >= (0 + 14) && idx <= (14 + 14)) in _halrf_idx_to_ch()
85 channelIndex = 0; in _halrf_idx_to_ch()
94 struct rf_pmac_tx_info tx_info = {0}; in _halrf_tssi_hw_tx_8852b()
103 tx_info.txagc_cw = 0; in _halrf_tssi_hw_tx_8852b()
[all …]
/OK3568_Linux_fs/external/rkwifibt/drivers/rtl8852be/phl/hal_g6/phy/rf/halrf_8852b/
H A Dhalrf_tssi_8852b.c28 for (i = 0; i < reg_num; i++) { in _tssi_backup_bb_registers_8852b()
31 RF_DBG(rf, DBG_RF_TX_PWR_TRACK, "[TSSI] Backup BB 0x%x = 0x%x\n", in _tssi_backup_bb_registers_8852b()
46 for (i = 0; i < reg_num; i++) { in _tssi_reload_bb_registers_8852b()
49 RF_DBG(rf, DBG_RF_TX_PWR_TRACK, "[TSSI] Reload BB 0x%x = 0x%x\n", in _tssi_reload_bb_registers_8852b()
67 channelIndex = 0; in _halrf_ch_to_idx()
76 if (idx >= 0 && idx <= 13) in _halrf_idx_to_ch()
78 else if (idx >= (0 + 14) && idx <= (14 + 14)) in _halrf_idx_to_ch()
85 channelIndex = 0; in _halrf_idx_to_ch()
94 struct rf_pmac_tx_info tx_info = {0}; in _halrf_tssi_hw_tx_8852b()
103 tx_info.txagc_cw = 0; in _halrf_tssi_hw_tx_8852b()
[all …]
/OK3568_Linux_fs/kernel/drivers/net/wireless/mediatek/mt76/mt76x0/
H A Dinitvals_init.h15 { MT_BCN_OFFSET(0), 0xf8f0e8e0 },
16 { MT_BCN_OFFSET(1), 0x6f77d0c8 },
17 { MT_LEGACY_BASIC_RATE, 0x0000013f },
18 { MT_HT_BASIC_RATE, 0x00008003 },
19 { MT_MAC_SYS_CTRL, 0x00000000 },
20 { MT_RX_FILTR_CFG, 0x00017f97 },
21 { MT_BKOFF_SLOT_CFG, 0x00000209 },
22 { MT_TX_SW_CFG0, 0x00000000 },
23 { MT_TX_SW_CFG1, 0x00080606 },
24 { MT_TX_LINK_CFG, 0x00001020 },
[all …]
/OK3568_Linux_fs/kernel/arch/sh/boards/mach-migor/
H A Dlcd_qvga.c27 * Index 0: "Device Code Read" returns 0x1505.
32 gpio_set_value(GPIO_PTH2, 0); in reset_lcd_module()
44 tmp1 = (data<<1 | 0x00000001) & 0x000001FF; in adjust_reg18()
45 tmp2 = (data<<2 | 0x00000200) & 0x0003FE00; in adjust_reg18()
72 return ((data >> 1) & 0xff) | ((data >> 2) & 0xff00); in read_reg16()
81 for (i = 0; i < no_data; i += 2) in migor_lcd_qvga_seq()
86 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
90 0x0060, 0x2700, 0x0008, 0x0808, 0x0090, 0x001A, 0x0007, 0x0001,
91 0x0017, 0x0001, 0x0019, 0x0000, 0x0010, 0x17B0, 0x0011, 0x0116,
92 0x0012, 0x0198, 0x0013, 0x1400, 0x0029, 0x000C, 0x0012, 0x01B8,
[all …]
/OK3568_Linux_fs/kernel/include/video/
H A Dtgafb.h20 #define TGA_TYPE_8PLANE 0
28 #define TGA_ROM_OFFSET 0x0000000
29 #define TGA_REGS_OFFSET 0x0100000
30 #define TGA_8PLANE_FB_OFFSET 0x0200000
31 #define TGA_24PLANE_FB_OFFSET 0x0804000
32 #define TGA_24PLUSZ_FB_OFFSET 0x1004000
34 #define TGA_FOREGROUND_REG 0x0020
35 #define TGA_BACKGROUND_REG 0x0024
36 #define TGA_PLANEMASK_REG 0x0028
37 #define TGA_PIXELMASK_ONESHOT_REG 0x002c
[all …]
/OK3568_Linux_fs/kernel/drivers/gpu/drm/amd/include/asic_reg/athub/
H A Dathub_2_0_0_default.h26 #define mmATC_ATS_CNTL_DEFAULT 0x009a0c00
27 #define mmATC_ATS_STATUS_DEFAULT 0x00000000
28 #define mmATC_ATS_FAULT_CNTL_DEFAULT 0x000001ff
29 #define mmATC_ATS_FAULT_STATUS_INFO_DEFAULT 0x00000000
30 #define mmATC_ATS_FAULT_STATUS_ADDR_DEFAULT 0x00000000
31 #define mmATC_ATS_DEFAULT_PAGE_LOW_DEFAULT 0x00000000
32 #define mmATC_TRANS_FAULT_RSPCNTRL_DEFAULT 0xffffffff
33 #define mmATC_ATS_FAULT_STATUS_INFO2_DEFAULT 0x00000000
34 #define mmATHUB_MISC_CNTL_DEFAULT 0x001c0200
35 #define mmATC_VMID_PASID_MAPPING_UPDATE_STATUS_DEFAULT 0x00000000
[all …]
/OK3568_Linux_fs/u-boot/drivers/ata/
H A Ddwc_ahsata_priv.h23 #define SATA_HOST_CAP_S64A 0x80000000
24 #define SATA_HOST_CAP_SNCQ 0x40000000
25 #define SATA_HOST_CAP_SSNTF 0x20000000
26 #define SATA_HOST_CAP_SMPS 0x10000000
27 #define SATA_HOST_CAP_SSS 0x08000000
28 #define SATA_HOST_CAP_SALP 0x04000000
29 #define SATA_HOST_CAP_SAL 0x02000000
30 #define SATA_HOST_CAP_SCLO 0x01000000
31 #define SATA_HOST_CAP_ISS_MASK 0x00f00000
33 #define SATA_HOST_CAP_SNZO 0x00080000
[all …]
/OK3568_Linux_fs/kernel/drivers/mfd/
H A Drk630-spi.c16 #define RK630_CMD_WRITE 0x00000011
17 #define RK630_CMD_WRITE_REG0 0x00010011
18 #define RK630_CMD_WRITE_REG1 0x00020011
19 #define RK630_CMD_WRITE_CTRL0 0x00030011
20 #define RK630_CMD_READ 0x00000077
21 #define RK630_CMD_READ_BEGIN 0x000000AA
22 #define RK630_CMD_QUERY 0x000000FF
23 #define RK630_CMD_QUERY_REG2 0x000001FF
24 #define RK630_CMD_QUICK_WRITE 0x00030011
25 #define RK630_OP_STATE_ID_MASK (0xffff0000)
[all …]
/OK3568_Linux_fs/kernel/drivers/clk/
H A Dclk-xgene.c17 #define N_DIV_RD(src) ((src) & 0x000001ff)
18 #define SC_N_DIV_RD(src) ((src) & 0x0000007f)
19 #define SC_OUTDIV2(src) (((src) & 0x00000100) >> 8)
22 #define CLKR_RD(src) (((src) & 0x07000000)>>24)
23 #define CLKOD_RD(src) (((src) & 0x00300000)>>20)
24 #define REGSPEC_RESET_F1_MASK 0x00010000
25 #define CLKF_RD(src) (((src) & 0x000001ff))
43 PLL_TYPE_PCP = 0,
67 return data & REGSPEC_RESET_F1_MASK ? 0 : 1; in xgene_clk_pll_is_enabled()
141 init.num_parents = parent_name ? 1 : 0; in xgene_register_clk_pll()
[all …]

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