1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0 */ 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * Common defines for v7m cpus 4*4882a593Smuzhiyun */ 5*4882a593Smuzhiyun #define V7M_SCS_ICTR IOMEM(0xe000e004) 6*4882a593Smuzhiyun #define V7M_SCS_ICTR_INTLINESNUM_MASK 0x0000000f 7*4882a593Smuzhiyun 8*4882a593Smuzhiyun #define BASEADDR_V7M_SCB IOMEM(0xe000ed00) 9*4882a593Smuzhiyun 10*4882a593Smuzhiyun #define V7M_SCB_CPUID 0x00 11*4882a593Smuzhiyun 12*4882a593Smuzhiyun #define V7M_SCB_ICSR 0x04 13*4882a593Smuzhiyun #define V7M_SCB_ICSR_PENDSVSET (1 << 28) 14*4882a593Smuzhiyun #define V7M_SCB_ICSR_PENDSVCLR (1 << 27) 15*4882a593Smuzhiyun #define V7M_SCB_ICSR_RETTOBASE (1 << 11) 16*4882a593Smuzhiyun 17*4882a593Smuzhiyun #define V7M_SCB_VTOR 0x08 18*4882a593Smuzhiyun 19*4882a593Smuzhiyun #define V7M_SCB_AIRCR 0x0c 20*4882a593Smuzhiyun #define V7M_SCB_AIRCR_VECTKEY (0x05fa << 16) 21*4882a593Smuzhiyun #define V7M_SCB_AIRCR_SYSRESETREQ (1 << 2) 22*4882a593Smuzhiyun 23*4882a593Smuzhiyun #define V7M_SCB_SCR 0x10 24*4882a593Smuzhiyun #define V7M_SCB_SCR_SLEEPDEEP (1 << 2) 25*4882a593Smuzhiyun 26*4882a593Smuzhiyun #define V7M_SCB_CCR 0x14 27*4882a593Smuzhiyun #define V7M_SCB_CCR_STKALIGN (1 << 9) 28*4882a593Smuzhiyun #define V7M_SCB_CCR_DC (1 << 16) 29*4882a593Smuzhiyun #define V7M_SCB_CCR_IC (1 << 17) 30*4882a593Smuzhiyun #define V7M_SCB_CCR_BP (1 << 18) 31*4882a593Smuzhiyun 32*4882a593Smuzhiyun #define V7M_SCB_SHPR2 0x1c 33*4882a593Smuzhiyun #define V7M_SCB_SHPR3 0x20 34*4882a593Smuzhiyun 35*4882a593Smuzhiyun #define V7M_SCB_SHCSR 0x24 36*4882a593Smuzhiyun #define V7M_SCB_SHCSR_USGFAULTENA (1 << 18) 37*4882a593Smuzhiyun #define V7M_SCB_SHCSR_BUSFAULTENA (1 << 17) 38*4882a593Smuzhiyun #define V7M_SCB_SHCSR_MEMFAULTENA (1 << 16) 39*4882a593Smuzhiyun 40*4882a593Smuzhiyun #define V7M_xPSR_FRAMEPTRALIGN 0x00000200 41*4882a593Smuzhiyun #define V7M_xPSR_EXCEPTIONNO 0x000001ff 42*4882a593Smuzhiyun 43*4882a593Smuzhiyun /* 44*4882a593Smuzhiyun * When branching to an address that has bits [31:28] == 0xf an exception return 45*4882a593Smuzhiyun * occurs. Bits [27:5] are reserved (SBOP). If the processor implements the FP 46*4882a593Smuzhiyun * extension Bit [4] defines if the exception frame has space allocated for FP 47*4882a593Smuzhiyun * state information, SBOP otherwise. Bit [3] defines the mode that is returned 48*4882a593Smuzhiyun * to (0 -> handler mode; 1 -> thread mode). Bit [2] defines which sp is used 49*4882a593Smuzhiyun * (0 -> msp; 1 -> psp). Bits [1:0] are fixed to 0b01. 50*4882a593Smuzhiyun */ 51*4882a593Smuzhiyun #define EXC_RET_STACK_MASK 0x00000004 52*4882a593Smuzhiyun #define EXC_RET_THREADMODE_PROCESSSTACK (3 << 2) 53*4882a593Smuzhiyun 54*4882a593Smuzhiyun /* Cache related definitions */ 55*4882a593Smuzhiyun 56*4882a593Smuzhiyun #define V7M_SCB_CLIDR 0x78 /* Cache Level ID register */ 57*4882a593Smuzhiyun #define V7M_SCB_CTR 0x7c /* Cache Type register */ 58*4882a593Smuzhiyun #define V7M_SCB_CCSIDR 0x80 /* Cache size ID register */ 59*4882a593Smuzhiyun #define V7M_SCB_CSSELR 0x84 /* Cache size selection register */ 60*4882a593Smuzhiyun 61*4882a593Smuzhiyun /* Memory-mapped MPU registers for M-class */ 62*4882a593Smuzhiyun #define MPU_TYPE 0x90 63*4882a593Smuzhiyun #define MPU_CTRL 0x94 64*4882a593Smuzhiyun #define MPU_CTRL_ENABLE 1 65*4882a593Smuzhiyun #define MPU_CTRL_PRIVDEFENA (1 << 2) 66*4882a593Smuzhiyun 67*4882a593Smuzhiyun #define PMSAv7_RNR 0x98 68*4882a593Smuzhiyun #define PMSAv7_RBAR 0x9c 69*4882a593Smuzhiyun #define PMSAv7_RASR 0xa0 70*4882a593Smuzhiyun 71*4882a593Smuzhiyun #define PMSAv8_RNR 0x98 72*4882a593Smuzhiyun #define PMSAv8_RBAR 0x9c 73*4882a593Smuzhiyun #define PMSAv8_RLAR 0xa0 74*4882a593Smuzhiyun #define PMSAv8_RBAR_A(n) (PMSAv8_RBAR + 8*(n)) 75*4882a593Smuzhiyun #define PMSAv8_RLAR_A(n) (PMSAv8_RLAR + 8*(n)) 76*4882a593Smuzhiyun #define PMSAv8_MAIR0 0xc0 77*4882a593Smuzhiyun #define PMSAv8_MAIR1 0xc4 78*4882a593Smuzhiyun 79*4882a593Smuzhiyun /* Cache opeartions */ 80*4882a593Smuzhiyun #define V7M_SCB_ICIALLU 0x250 /* I-cache invalidate all to PoU */ 81*4882a593Smuzhiyun #define V7M_SCB_ICIMVAU 0x258 /* I-cache invalidate by MVA to PoU */ 82*4882a593Smuzhiyun #define V7M_SCB_DCIMVAC 0x25c /* D-cache invalidate by MVA to PoC */ 83*4882a593Smuzhiyun #define V7M_SCB_DCISW 0x260 /* D-cache invalidate by set-way */ 84*4882a593Smuzhiyun #define V7M_SCB_DCCMVAU 0x264 /* D-cache clean by MVA to PoU */ 85*4882a593Smuzhiyun #define V7M_SCB_DCCMVAC 0x268 /* D-cache clean by MVA to PoC */ 86*4882a593Smuzhiyun #define V7M_SCB_DCCSW 0x26c /* D-cache clean by set-way */ 87*4882a593Smuzhiyun #define V7M_SCB_DCCIMVAC 0x270 /* D-cache clean and invalidate by MVA to PoC */ 88*4882a593Smuzhiyun #define V7M_SCB_DCCISW 0x274 /* D-cache clean and invalidate by set-way */ 89*4882a593Smuzhiyun #define V7M_SCB_BPIALL 0x278 /* D-cache clean and invalidate by set-way */ 90*4882a593Smuzhiyun 91*4882a593Smuzhiyun #ifndef __ASSEMBLY__ 92*4882a593Smuzhiyun 93*4882a593Smuzhiyun enum reboot_mode; 94*4882a593Smuzhiyun 95*4882a593Smuzhiyun void armv7m_restart(enum reboot_mode mode, const char *cmd); 96*4882a593Smuzhiyun 97*4882a593Smuzhiyun #endif /* __ASSEMBLY__ */ 98