1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun * Copyright (c) 2020 Rockchip Electronics Co. Ltd.
4*4882a593Smuzhiyun *
5*4882a593Smuzhiyun * Author: Algea Cao <algea.cao@rock-chips.com>
6*4882a593Smuzhiyun */
7*4882a593Smuzhiyun
8*4882a593Smuzhiyun #include <linux/device.h>
9*4882a593Smuzhiyun #include <linux/err.h>
10*4882a593Smuzhiyun #include <linux/input.h>
11*4882a593Smuzhiyun #include <linux/module.h>
12*4882a593Smuzhiyun #include <linux/of.h>
13*4882a593Smuzhiyun #include <linux/mfd/rk630.h>
14*4882a593Smuzhiyun #include <linux/spi/spi.h>
15*4882a593Smuzhiyun
16*4882a593Smuzhiyun #define RK630_CMD_WRITE 0x00000011
17*4882a593Smuzhiyun #define RK630_CMD_WRITE_REG0 0x00010011
18*4882a593Smuzhiyun #define RK630_CMD_WRITE_REG1 0x00020011
19*4882a593Smuzhiyun #define RK630_CMD_WRITE_CTRL0 0x00030011
20*4882a593Smuzhiyun #define RK630_CMD_READ 0x00000077
21*4882a593Smuzhiyun #define RK630_CMD_READ_BEGIN 0x000000AA
22*4882a593Smuzhiyun #define RK630_CMD_QUERY 0x000000FF
23*4882a593Smuzhiyun #define RK630_CMD_QUERY_REG2 0x000001FF
24*4882a593Smuzhiyun #define RK630_CMD_QUICK_WRITE 0x00030011
25*4882a593Smuzhiyun #define RK630_OP_STATE_ID_MASK (0xffff0000)
26*4882a593Smuzhiyun #define RK630_OP_STATE_ID (0X16080000)
27*4882a593Smuzhiyun #define RK630_OP_STATE_MASK (0x0000ffff)
28*4882a593Smuzhiyun #define RK630_OP_STATE_WRITE_ERROR (0x01 << 0)
29*4882a593Smuzhiyun #define RK630_OP_STATE_WRITE_OVERFLOW (0x01 << 1)
30*4882a593Smuzhiyun #define RK630_OP_STATE_WRITE_UNFINISHED (0x01 << 2)
31*4882a593Smuzhiyun #define RK630_OP_STATE_READ_ERROR (0x01 << 8)
32*4882a593Smuzhiyun #define RK630_OP_STATE_READ_UNDERFLOW (0x01 << 9)
33*4882a593Smuzhiyun #define RK630_OP_STATE_PRE_READ_ERROR (0x01 << 10)
34*4882a593Smuzhiyun #define RK630_MAX_OP_BYTES (60000)
35*4882a593Smuzhiyun
rk630_spi_ctrl_init(struct spi_device * spi)36*4882a593Smuzhiyun static int rk630_spi_ctrl_init(struct spi_device *spi)
37*4882a593Smuzhiyun {
38*4882a593Smuzhiyun u32 write_cmd = RK630_CMD_WRITE_CTRL0;
39*4882a593Smuzhiyun u32 buf = 0x00000008;
40*4882a593Smuzhiyun struct spi_transfer write_cmd_packet = {
41*4882a593Smuzhiyun .tx_buf = &write_cmd,
42*4882a593Smuzhiyun .len = 4,
43*4882a593Smuzhiyun };
44*4882a593Smuzhiyun struct spi_transfer data_packet = {
45*4882a593Smuzhiyun .tx_buf = &buf,
46*4882a593Smuzhiyun .len = 4,
47*4882a593Smuzhiyun };
48*4882a593Smuzhiyun struct spi_message m;
49*4882a593Smuzhiyun
50*4882a593Smuzhiyun spi_message_init(&m);
51*4882a593Smuzhiyun spi_message_add_tail(&write_cmd_packet, &m);
52*4882a593Smuzhiyun spi_message_add_tail(&data_packet, &m);
53*4882a593Smuzhiyun return spi_sync(spi, &m);
54*4882a593Smuzhiyun }
55*4882a593Smuzhiyun
rk630_spi_write(struct spi_device * spi,u32 addr,const u32 * data,size_t data_len)56*4882a593Smuzhiyun static int rk630_spi_write(struct spi_device *spi,
57*4882a593Smuzhiyun u32 addr, const u32 *data, size_t data_len)
58*4882a593Smuzhiyun {
59*4882a593Smuzhiyun int ret = 0;
60*4882a593Smuzhiyun u32 write_cmd = RK630_CMD_WRITE;
61*4882a593Smuzhiyun
62*4882a593Smuzhiyun struct spi_transfer write_cmd_packet = {
63*4882a593Smuzhiyun .tx_buf = &write_cmd,
64*4882a593Smuzhiyun .len = sizeof(write_cmd),
65*4882a593Smuzhiyun };
66*4882a593Smuzhiyun struct spi_transfer addr_packet = {
67*4882a593Smuzhiyun .tx_buf = &addr,
68*4882a593Smuzhiyun .len = sizeof(addr),
69*4882a593Smuzhiyun };
70*4882a593Smuzhiyun struct spi_transfer data_packet = {
71*4882a593Smuzhiyun .tx_buf = data,
72*4882a593Smuzhiyun .len = data_len,
73*4882a593Smuzhiyun };
74*4882a593Smuzhiyun struct spi_message m;
75*4882a593Smuzhiyun
76*4882a593Smuzhiyun spi_message_init(&m);
77*4882a593Smuzhiyun spi_message_add_tail(&write_cmd_packet, &m);
78*4882a593Smuzhiyun spi_message_add_tail(&addr_packet, &m);
79*4882a593Smuzhiyun spi_message_add_tail(&data_packet, &m);
80*4882a593Smuzhiyun ret = spi_sync(spi, &m);
81*4882a593Smuzhiyun
82*4882a593Smuzhiyun return ret;
83*4882a593Smuzhiyun }
84*4882a593Smuzhiyun
rk630_regmap_write(void * context,const void * data,size_t count)85*4882a593Smuzhiyun static int rk630_regmap_write(void *context, const void *data, size_t count)
86*4882a593Smuzhiyun {
87*4882a593Smuzhiyun struct device *dev = context;
88*4882a593Smuzhiyun struct spi_device *spi = to_spi_device(dev);
89*4882a593Smuzhiyun u32 buf[count];
90*4882a593Smuzhiyun
91*4882a593Smuzhiyun if (count < 8) {
92*4882a593Smuzhiyun dev_err(&spi->dev, "regmap write err!\n");
93*4882a593Smuzhiyun return -EINVAL;
94*4882a593Smuzhiyun }
95*4882a593Smuzhiyun
96*4882a593Smuzhiyun memcpy(buf, data, count);
97*4882a593Smuzhiyun
98*4882a593Smuzhiyun return rk630_spi_write(spi, buf[0], &buf[1], (count - 4));
99*4882a593Smuzhiyun }
100*4882a593Smuzhiyun
rk630_spi_read(struct spi_device * spi,u32 addr,u32 * data,size_t data_len)101*4882a593Smuzhiyun static int rk630_spi_read(struct spi_device *spi,
102*4882a593Smuzhiyun u32 addr, u32 *data, size_t data_len)
103*4882a593Smuzhiyun {
104*4882a593Smuzhiyun int ret;
105*4882a593Smuzhiyun u32 read_cmd = RK630_CMD_READ | (1 << 16);
106*4882a593Smuzhiyun u32 read_begin_cmd = RK630_CMD_READ_BEGIN;
107*4882a593Smuzhiyun u32 dummy = 0;
108*4882a593Smuzhiyun struct spi_transfer read_cmd_packet = {
109*4882a593Smuzhiyun .tx_buf = &read_cmd,
110*4882a593Smuzhiyun .len = sizeof(read_cmd),
111*4882a593Smuzhiyun };
112*4882a593Smuzhiyun struct spi_transfer addr_packet = {
113*4882a593Smuzhiyun .tx_buf = &addr,
114*4882a593Smuzhiyun .len = sizeof(addr),
115*4882a593Smuzhiyun };
116*4882a593Smuzhiyun struct spi_transfer read_dummy_packet = {
117*4882a593Smuzhiyun .tx_buf = &dummy,
118*4882a593Smuzhiyun .len = sizeof(dummy),
119*4882a593Smuzhiyun };
120*4882a593Smuzhiyun struct spi_transfer read_begin_cmd_packet = {
121*4882a593Smuzhiyun .tx_buf = &read_begin_cmd,
122*4882a593Smuzhiyun .len = sizeof(read_begin_cmd),
123*4882a593Smuzhiyun };
124*4882a593Smuzhiyun struct spi_transfer data_packet = {
125*4882a593Smuzhiyun .rx_buf = data,
126*4882a593Smuzhiyun .len = data_len,
127*4882a593Smuzhiyun };
128*4882a593Smuzhiyun struct spi_message m;
129*4882a593Smuzhiyun
130*4882a593Smuzhiyun spi_message_init(&m);
131*4882a593Smuzhiyun spi_message_add_tail(&read_cmd_packet, &m);
132*4882a593Smuzhiyun spi_message_add_tail(&addr_packet, &m);
133*4882a593Smuzhiyun spi_message_add_tail(&read_dummy_packet, &m);
134*4882a593Smuzhiyun spi_message_add_tail(&read_begin_cmd_packet, &m);
135*4882a593Smuzhiyun spi_message_add_tail(&data_packet, &m);
136*4882a593Smuzhiyun ret = spi_sync(spi, &m);
137*4882a593Smuzhiyun
138*4882a593Smuzhiyun return ret;
139*4882a593Smuzhiyun }
140*4882a593Smuzhiyun
rk630_regmap_read(void * context,const void * reg,size_t reg_size,void * val,size_t val_size)141*4882a593Smuzhiyun static int rk630_regmap_read(void *context,
142*4882a593Smuzhiyun const void *reg, size_t reg_size,
143*4882a593Smuzhiyun void *val, size_t val_size)
144*4882a593Smuzhiyun {
145*4882a593Smuzhiyun struct device *dev = context;
146*4882a593Smuzhiyun struct spi_device *spi = to_spi_device(dev);
147*4882a593Smuzhiyun u32 rx_buf[2] = { 0 };
148*4882a593Smuzhiyun int ret;
149*4882a593Smuzhiyun
150*4882a593Smuzhiyun if (reg_size != sizeof(u32) || val_size != sizeof(u32))
151*4882a593Smuzhiyun return -EINVAL;
152*4882a593Smuzhiyun
153*4882a593Smuzhiyun /* Copy address to read from into first element of SPI buffer. */
154*4882a593Smuzhiyun memcpy(rx_buf, reg, sizeof(u32));
155*4882a593Smuzhiyun ret = rk630_spi_read(spi, rx_buf[0], &rx_buf[1], val_size);
156*4882a593Smuzhiyun if (ret < 0) {
157*4882a593Smuzhiyun dev_err(&spi->dev, "rk630 spi read err\n");
158*4882a593Smuzhiyun return ret;
159*4882a593Smuzhiyun }
160*4882a593Smuzhiyun
161*4882a593Smuzhiyun memcpy(val, &rx_buf[1], val_size);
162*4882a593Smuzhiyun return 0;
163*4882a593Smuzhiyun }
164*4882a593Smuzhiyun
165*4882a593Smuzhiyun static struct regmap_bus rk630_regmap = {
166*4882a593Smuzhiyun .write = rk630_regmap_write,
167*4882a593Smuzhiyun .read = rk630_regmap_read,
168*4882a593Smuzhiyun .reg_format_endian_default = REGMAP_ENDIAN_NATIVE,
169*4882a593Smuzhiyun .val_format_endian_default = REGMAP_ENDIAN_NATIVE,
170*4882a593Smuzhiyun };
171*4882a593Smuzhiyun
172*4882a593Smuzhiyun static int
rk630_spi_probe(struct spi_device * spi)173*4882a593Smuzhiyun rk630_spi_probe(struct spi_device *spi)
174*4882a593Smuzhiyun {
175*4882a593Smuzhiyun struct device *dev = &spi->dev;
176*4882a593Smuzhiyun struct rk630 *rk630;
177*4882a593Smuzhiyun int ret;
178*4882a593Smuzhiyun
179*4882a593Smuzhiyun spi->bits_per_word = 8;
180*4882a593Smuzhiyun ret = spi_setup(spi);
181*4882a593Smuzhiyun if (ret < 0)
182*4882a593Smuzhiyun return ret;
183*4882a593Smuzhiyun
184*4882a593Smuzhiyun rk630 = devm_kzalloc(dev, sizeof(*rk630), GFP_KERNEL);
185*4882a593Smuzhiyun if (!rk630)
186*4882a593Smuzhiyun return -ENOMEM;
187*4882a593Smuzhiyun
188*4882a593Smuzhiyun rk630->dev = dev;
189*4882a593Smuzhiyun spi_set_drvdata(spi, rk630);
190*4882a593Smuzhiyun
191*4882a593Smuzhiyun rk630->grf = devm_regmap_init(&spi->dev, &rk630_regmap,
192*4882a593Smuzhiyun &spi->dev, &rk630_grf_regmap_config);
193*4882a593Smuzhiyun if (IS_ERR(rk630->grf)) {
194*4882a593Smuzhiyun ret = PTR_ERR(rk630->grf);
195*4882a593Smuzhiyun dev_err(dev, "failed to allocate grf register map: %d\n", ret);
196*4882a593Smuzhiyun return ret;
197*4882a593Smuzhiyun }
198*4882a593Smuzhiyun
199*4882a593Smuzhiyun rk630->cru = devm_regmap_init(&spi->dev, &rk630_regmap,
200*4882a593Smuzhiyun &spi->dev, &rk630_cru_regmap_config);
201*4882a593Smuzhiyun if (IS_ERR(rk630->cru)) {
202*4882a593Smuzhiyun ret = PTR_ERR(rk630->cru);
203*4882a593Smuzhiyun dev_err(dev, "failed to allocate cru register map: %d\n", ret);
204*4882a593Smuzhiyun return ret;
205*4882a593Smuzhiyun }
206*4882a593Smuzhiyun
207*4882a593Smuzhiyun rk630->tve = devm_regmap_init(&spi->dev, &rk630_regmap,
208*4882a593Smuzhiyun &spi->dev, &rk630_tve_regmap_config);
209*4882a593Smuzhiyun if (IS_ERR(rk630->tve)) {
210*4882a593Smuzhiyun ret = PTR_ERR(rk630->tve);
211*4882a593Smuzhiyun dev_err(rk630->dev, "Failed to initialize tve regmap: %d\n",
212*4882a593Smuzhiyun ret);
213*4882a593Smuzhiyun return ret;
214*4882a593Smuzhiyun }
215*4882a593Smuzhiyun
216*4882a593Smuzhiyun ret = rk630_core_probe(rk630);
217*4882a593Smuzhiyun if (ret)
218*4882a593Smuzhiyun return ret;
219*4882a593Smuzhiyun
220*4882a593Smuzhiyun rk630_spi_ctrl_init(spi);
221*4882a593Smuzhiyun
222*4882a593Smuzhiyun return 0;
223*4882a593Smuzhiyun }
224*4882a593Smuzhiyun
225*4882a593Smuzhiyun static const struct of_device_id rk630_spi_of_match[] = {
226*4882a593Smuzhiyun { .compatible = "rockchip,rk630", },
227*4882a593Smuzhiyun {}
228*4882a593Smuzhiyun };
229*4882a593Smuzhiyun MODULE_DEVICE_TABLE(of, rk630_spi_of_match);
230*4882a593Smuzhiyun
231*4882a593Smuzhiyun static const struct spi_device_id rk630_spi_id[] = {
232*4882a593Smuzhiyun { "rk630", 0 },
233*4882a593Smuzhiyun {}
234*4882a593Smuzhiyun };
235*4882a593Smuzhiyun MODULE_DEVICE_TABLE(spi, rk630_spi_id);
236*4882a593Smuzhiyun
237*4882a593Smuzhiyun static struct spi_driver rk630_spi_driver = {
238*4882a593Smuzhiyun .driver = {
239*4882a593Smuzhiyun .name = "rk630",
240*4882a593Smuzhiyun .of_match_table = of_match_ptr(rk630_spi_of_match),
241*4882a593Smuzhiyun },
242*4882a593Smuzhiyun .probe = rk630_spi_probe,
243*4882a593Smuzhiyun .id_table = rk630_spi_id,
244*4882a593Smuzhiyun };
245*4882a593Smuzhiyun module_spi_driver(rk630_spi_driver);
246*4882a593Smuzhiyun
247*4882a593Smuzhiyun MODULE_AUTHOR("Algea Cao <Algea.cao@rock-chips.com>");
248*4882a593Smuzhiyun MODULE_DESCRIPTION("Rockchip rk630 MFD SPI driver");
249*4882a593Smuzhiyun MODULE_LICENSE("GPL v2");
250