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Searched defs:pll (Results 1 – 25 of 76) sorted by relevance

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/rk3399_rockchip-uboot/arch/arm/cpu/arm926ejs/mx27/
H A Dgeneric.c27 static unsigned int imx_decode_pll(unsigned int pll, unsigned int f_ref) in imx_decode_pll()
47 struct pll_regs *pll = (struct pll_regs *)IMX_PLL_BASE; in clk_in_26m() local
59 struct pll_regs *pll = (struct pll_regs *)IMX_PLL_BASE; in imx_get_mpllclk() local
73 struct pll_regs *pll = (struct pll_regs *)IMX_PLL_BASE; in imx_get_armclk() local
88 struct pll_regs *pll = (struct pll_regs *)IMX_PLL_BASE; in imx_get_ahbclk() local
100 struct pll_regs *pll = (struct pll_regs *)IMX_PLL_BASE; in imx_get_spllclk() local
119 struct pll_regs *pll = (struct pll_regs *)IMX_PLL_BASE; in imx_get_perclk1() local
126 struct pll_regs *pll = (struct pll_regs *)IMX_PLL_BASE; in imx_get_perclk2() local
133 struct pll_regs *pll = (struct pll_regs *)IMX_PLL_BASE; in imx_get_perclk3() local
140 struct pll_regs *pll = (struct pll_regs *)IMX_PLL_BASE; in imx_get_perclk4() local
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H A Dtimer.c92 struct pll_regs *pll = (struct pll_regs *)IMX_PLL_BASE; in timer_init() local
/rk3399_rockchip-uboot/arch/m68k/cpu/mcf52x2/
H A Dspeed.c22 pll_t *pll = (pll_t *) MMAP_PLL; in get_clocks() local
58 pll_t *pll = (pll_t *)(MMAP_PLL); in get_clocks() local
/rk3399_rockchip-uboot/arch/m68k/cpu/mcf5445x/
H A Dspeed.c60 pll_t *pll = (pll_t *)MMAP_PLL; in clock_exit_limp() local
74 pll_t *pll = (pll_t *)MMAP_PLL; in setup_5441x_clocks() local
131 pll_t *pll = (pll_t *)MMAP_PLL; in setup_5445x_clocks() local
/rk3399_rockchip-uboot/drivers/clk/rockchip/
H A Dclk_pll.c272 rockchip_get_pll_settings(struct rockchip_pll_clock *pll, ulong rate) in rockchip_get_pll_settings()
291 static int rk3036_pll_set_rate(struct rockchip_pll_clock *pll, in rk3036_pll_set_rate()
370 static ulong rk3036_pll_get_rate(struct rockchip_pll_clock *pll, in rk3036_pll_get_rate()
444 static int rk3588_pll_set_rate(struct rockchip_pll_clock *pll, in rk3588_pll_set_rate()
561 static ulong rk3588_pll_get_rate(struct rockchip_pll_clock *pll, in rk3588_pll_get_rate()
620 ulong rockchip_pll_get_rate(struct rockchip_pll_clock *pll, in rockchip_pll_get_rate()
646 int rockchip_pll_set_rate(struct rockchip_pll_clock *pll, in rockchip_pll_set_rate()
/rk3399_rockchip-uboot/arch/m68k/cpu/mcf5227x/
H A Dspeed.c58 pll_t *pll = (pll_t *)MMAP_PLL; in clock_exit_limp() local
75 pll_t *pll = (pll_t *)MMAP_PLL; in get_clocks() local
H A Dcpu_init.c34 pll_t *pll = (pll_t *)MMAP_PLL; in cpu_init_f() local
/rk3399_rockchip-uboot/arch/arm/include/asm/arch-s32v234/
H A Dmc_cgm_regs.h71 #define PLLDIG_PLLDV(pll) ((MC_CGM0_BASE_ADDR + 0x00000028) + ((pll) * 0x80)) argument
95 #define PLLDIG_PLLFD(pll) ((MC_CGM0_BASE_ADDR + 0x00000030) + ((pll) * 0x80)) argument
101 #define PLLDIG_PLLCAL1(pll) ((MC_CGM0_BASE_ADDR + 0x00000038) + ((pll) * 0x80)) argument
111 #define DFS_DLLPRG1(pll) (DFS0_BASE_ADDR + 0x00000000 + ((pll) * 0x80)) argument
138 #define DFS_CTRL(pll) (DFS0_BASE_ADDR + 0x00000018 + ((pll) * 0x80)) argument
143 #define DFS_PORTSR(pll) (DFS0_BASE_ADDR + 0x0000000C +((pll) * 0x80)) argument
145 #define DFS_PORTRESET(pll) (DFS0_BASE_ADDR + 0x00000014 + ((pll) * 0x80)) argument
152 #define DFS_DVPORTn(pll,n) (DFS0_BASE_ADDR + ((pll) * 0x80) + (0x0000001C + ((n) * 0x4))) argument
/rk3399_rockchip-uboot/arch/arm/mach-keystone/include/mach/
H A Dclock_defs.h54 #define pllctl_reg(pll, reg) (&(pllctl_regs[pll]->reg)) argument
55 #define pllctl_reg_read(pll, reg) __raw_readl(pllctl_reg(pll, reg)) argument
56 #define pllctl_reg_write(pll, reg, val) __raw_writel(val, pllctl_reg(pll, reg)) argument
58 #define pllctl_reg_rmw(pll, reg, mask, val) \ argument
62 #define pllctl_reg_setbits(pll, reg, mask) \ argument
65 #define pllctl_reg_clrbits(pll, reg, mask) \ argument
/rk3399_rockchip-uboot/arch/m68k/cpu/mcf523x/
H A Dspeed.c24 pll_t *pll = (pll_t *)(MMAP_PLL); in get_clocks() local
/rk3399_rockchip-uboot/board/freescale/s32v234evb/
H A Dclock.c18 static int select_pll_source_clk(enum pll_type pll, u32 refclk_freq) in select_pll_source_clk()
82 static int program_pll(enum pll_type pll, u32 refclk_freq, u32 freq0, u32 freq1, in program_pll()
/rk3399_rockchip-uboot/arch/arm/mach-tegra/
H A Dclock.c93 struct clk_pll *pll = get_pll(clkid); in clock_ll_read_pll() local
117 struct clk_pll *pll = NULL; in clock_start_pll() local
266 struct clk_pll *pll = get_pll(clkid); in clock_set_pllout() local
535 struct clk_pll *pll; in clock_get_rate() local
592 struct clk_pll *pll; in clock_set_rate() local
675 struct clk_pll *pll = get_pll(CLOCK_ID_PERIPH); in clock_verify() local
H A Dcpu.c171 int pllx_set_rate(struct clk_pll_simple *pll , u32 divn, u32 divm, in pllx_set_rate()
232 struct clk_pll_simple *pll = &clkrst->crc_pll_simple[SIMPLE_PLLX]; in init_pllx() local
/rk3399_rockchip-uboot/arch/m68k/cpu/mcf532x/
H A Dspeed.c54 pll_t *pll = (pll_t *)(MMAP_PLL); in get_sys_clock() local
145 pll_t *pll = (pll_t *)(MMAP_PLL); in clock_pll() local
/rk3399_rockchip-uboot/arch/arm/mach-keystone/
H A Dclock.c222 int pll; in init_plls() local
280 static unsigned long pll_freq_get(int pll) in pll_freq_get()
/rk3399_rockchip-uboot/arch/mips/mach-ath79/ar933x/
H A Dclk.c35 u32 val, xtal, pll, div; in get_clocks() local
/rk3399_rockchip-uboot/arch/mips/mach-ath79/qca953x/
H A Dclk.c35 u32 val, ctrl, xtal, pll, div; in get_clocks() local
/rk3399_rockchip-uboot/arch/arm/mach-omap2/am33xx/
H A Demif4.c71 void config_ddr(unsigned int pll, const struct ctrl_ioregs *ioregs, in config_ddr()
/rk3399_rockchip-uboot/board/ti/ks2_evm/
H A Dboard_k2e.c75 struct pll_init_data *get_pll_init_data(int pll) in get_pll_init_data()
H A Dboard_k2l.c66 struct pll_init_data *get_pll_init_data(int pll) in get_pll_init_data()
H A Dboard_k2hk.c78 struct pll_init_data *get_pll_init_data(int pll) in get_pll_init_data()
/rk3399_rockchip-uboot/arch/arm/cpu/armv8/s32v234/
H A Dgeneric.c28 static uintptr_t get_pllfreq(u32 pll, u32 refclk_freq, u32 plldv, in get_pllfreq()
83 static uintptr_t decode_pll(enum pll_type pll, u32 refclk_freq, in decode_pll()
/rk3399_rockchip-uboot/arch/arm/cpu/armv7/iproc-common/
H A Darmpll.c42 uint32_t pll; in armpll_config() local
/rk3399_rockchip-uboot/drivers/clk/
H A Dclk_zynq.c173 enum zynq_clk pll; in zynq_clk_get_cpu_rate() local
243 enum zynq_clk pll; in zynq_clk_get_peripheral_rate() local
318 enum zynq_clk pll; in zynq_clk_set_peripheral_rate() local
/rk3399_rockchip-uboot/arch/arm/mach-imx/mx5/
H A Dclock.c161 static uint32_t decode_pll(struct mxc_pll_reg *pll, uint32_t infreq) in decode_pll()
552 static int calc_pll_params(u32 ref, u32 target, struct pll_param *pll) in calc_pll_params()
629 #define CHANGE_PLL_SETTINGS(pll, pd, fi, fn, fd) \ argument
649 struct mxc_pll_reg *pll = mxc_plls[index]; in config_pll_clk() local

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