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Searched refs:_REG16_CLR (Results 1 – 7 of 7) sorted by relevance

/utopia/UTPA2-700.0.x/modules/dmx/hal/k6/tsio/
H A DhalTSIO.c74 #define _REG16_CLR(reg, value); _HAL_REG16_W(reg, RESET_FLAG1(_HAL_REG16_R(reg), value)); macro
498 _REG16_CLR(&(_TSIO_CLKGEN0->REG_CLKGEN0_TSP), REG_CLKGEN0_TSP_DISABLE_CLOCK); in HAL_TSIO_ClkOpen()
502 _REG16_CLR(&(_TSIOCHIPTOP->REG_TOP_TSIO), REG_TOP_TSIO_TSP_BOOT_CLK_SEL); in HAL_TSIO_ClkOpen()
505 _REG16_CLR(&(_TSIOCtrl0->CKG_TSP_TSIO), TSIO0_CKG_TSP_TSIO); in HAL_TSIO_ClkOpen()
508 _REG16_CLR(&(_TSIO_CLKGEN0->REG_CLKGEN0_TSIO), REG_CLKGEN0_TSIO_DISABLE_CLOCK); in HAL_TSIO_ClkOpen()
527 _REG16_CLR(&(_TSIOCtrl0->SW_RSTZ), TSIO0_SW_RSTZ);//low active in HAL_TSIO_Reset()
539 _REG16_CLR(&(_TSIOCtrl0->TX_CONFIG0), TSIO0_INSERT_CTS_IN_TX); in HAL_TSIO_Tx2Rx_InsertCTS()
551 _REG16_CLR(&(_TSIOCtrl0->TX_CONFIG0), TSIO0_TX_DIRECT_RX_8); in HAL_TSIO_Tx2Rx_Direct8()
565 _REG16_CLR(&(_TSIOCtrl1->RX_CONFIG0), TSIO1_TX_DIRECT_RX_16); in HAL_TSIO_Tx2Rx_Direct16()
566 _REG16_CLR(&(_TSIOCtrl0->PUH_CONFIG1), TSIO0_PUH_CONFIG1_VCC_POWER_GOOD_SET_HIGHT); in HAL_TSIO_Tx2Rx_Direct16()
[all …]
/utopia/UTPA2-700.0.x/modules/dmx/hal/k6lite/tsio/
H A DhalTSIO.c74 #define _REG16_CLR(reg, value); _HAL_REG16_W(reg, RESET_FLAG1(_HAL_REG16_R(reg), value)); macro
498 _REG16_CLR(&(_TSIO_CLKGEN0->REG_CLKGEN0_TSP), REG_CLKGEN0_TSP_DISABLE_CLOCK); in HAL_TSIO_ClkOpen()
502 _REG16_CLR(&(_TSIOCHIPTOP->REG_TOP_TSIO), REG_TOP_TSIO_TSP_BOOT_CLK_SEL); in HAL_TSIO_ClkOpen()
505 _REG16_CLR(&(_TSIOCtrl0->CKG_TSP_TSIO), TSIO0_CKG_TSP_TSIO); in HAL_TSIO_ClkOpen()
508 _REG16_CLR(&(_TSIO_CLKGEN0->REG_CLKGEN0_TSIO), REG_CLKGEN0_TSIO_DISABLE_CLOCK); in HAL_TSIO_ClkOpen()
527 _REG16_CLR(&(_TSIOCtrl0->SW_RSTZ), TSIO0_SW_RSTZ);//low active in HAL_TSIO_Reset()
539 _REG16_CLR(&(_TSIOCtrl0->TX_CONFIG0), TSIO0_INSERT_CTS_IN_TX); in HAL_TSIO_Tx2Rx_InsertCTS()
551 _REG16_CLR(&(_TSIOCtrl0->TX_CONFIG0), TSIO0_TX_DIRECT_RX_8); in HAL_TSIO_Tx2Rx_Direct8()
565 _REG16_CLR(&(_TSIOCtrl1->RX_CONFIG0), TSIO1_TX_DIRECT_RX_16); in HAL_TSIO_Tx2Rx_Direct16()
566 _REG16_CLR(&(_TSIOCtrl0->PUH_CONFIG1), TSIO0_PUH_CONFIG1_VCC_POWER_GOOD_SET_HIGHT); in HAL_TSIO_Tx2Rx_Direct16()
[all …]
/utopia/UTPA2-700.0.x/modules/dmx/hal/k6lite/tso/
H A DhalTSO.c95 #define _REG16_CLR(reg, value); _HAL_REG16_W(reg, RESET_FLAG1(_HAL_REG16_R(reg), value)); macro
250 _REG16_CLR(&(_TSOCtrl->SW_RSTZ), TSO_SW_RSTZ);//low active in HAL_TSO_Reset_All()
254 _REG16_CLR(&(_TSOCtrl->SW_RSTZ), TSO_SW_RST_ALL | TSO_SW_RST_ALL1); in HAL_TSO_Reset_All()
917 _REG16_CLR(&(_TSOCtrl->CHANNEL0_IF1_CONFIG2),TSO_CHCFG_PIDFLT_REC_ALL); in HAL_TSO_Set_PidBypass()
920 … _REG16_CLR(&(_TSOCtrl->CHANNEL0_IF2_CONFIG2),TSO_CHANNEL0_IF2_CONFIG2_PIDFLT_REC_ALL); in HAL_TSO_Set_PidBypass()
923 … _REG16_CLR(&(_TSOCtrl->CHANNEL0_IF3_CONFIG2),TSO_CHANNEL0_IF3_CONFIG2_PIDFLT_REC_ALL); in HAL_TSO_Set_PidBypass()
926 … _REG16_CLR(&(_TSOCtrl->CHANNEL0_IF4_CONFIG2),TSO_CHANNEL0_IF4_CONFIG2_PIDFLT_REC_ALL); in HAL_TSO_Set_PidBypass()
929 … _REG16_CLR(&(_TSOCtrl->CHANNEL0_IF5_CONFIG2),TSO_CHANNEL0_IF5_CONFIG2_PIDFLT_REC_ALL); in HAL_TSO_Set_PidBypass()
932 … _REG16_CLR(&(_TSOCtrl->CHANNEL0_IF6_CONFIG2),TSO_CHANNEL0_IF6_CONFIG2_PIDFLT_REC_ALL); in HAL_TSO_Set_PidBypass()
1036 _REG16_CLR(FILE_CONFIG,TSO_FILE_CONFIG_TSO_RADDR_READ); in HAL_TSO_Get_Filein_ReadAddr()
[all …]
/utopia/UTPA2-700.0.x/modules/dmx/hal/k7u/tso/
H A DhalTSO.c96 #define _REG16_CLR(reg, value); _HAL_REG16_W(reg, RESET_FLAG1(_HAL_REG16_R(reg), value)); macro
253 _REG16_CLR(&(_TSOCtrl->SW_RSTZ), TSO_SW_RSTZ);//low active in HAL_TSO_Reset_All()
257 _REG16_CLR(&(_TSOCtrl->SW_RSTZ), TSO_SW_RST_ALL | TSO_SW_RST_ALL1); in HAL_TSO_Reset_All()
920 _REG16_CLR(&(_TSOCtrl->CHANNEL0_IF1_CONFIG2),TSO_CHCFG_PIDFLT_REC_ALL); in HAL_TSO_Set_PidBypass()
923 … _REG16_CLR(&(_TSOCtrl->CHANNEL0_IF2_CONFIG2),TSO_CHANNEL0_IF2_CONFIG2_PIDFLT_REC_ALL); in HAL_TSO_Set_PidBypass()
926 … _REG16_CLR(&(_TSOCtrl->CHANNEL0_IF3_CONFIG2),TSO_CHANNEL0_IF3_CONFIG2_PIDFLT_REC_ALL); in HAL_TSO_Set_PidBypass()
929 … _REG16_CLR(&(_TSOCtrl->CHANNEL0_IF4_CONFIG2),TSO_CHANNEL0_IF4_CONFIG2_PIDFLT_REC_ALL); in HAL_TSO_Set_PidBypass()
932 … _REG16_CLR(&(_TSOCtrl->CHANNEL0_IF5_CONFIG2),TSO_CHANNEL0_IF5_CONFIG2_PIDFLT_REC_ALL); in HAL_TSO_Set_PidBypass()
935 … _REG16_CLR(&(_TSOCtrl->CHANNEL0_IF6_CONFIG2),TSO_CHANNEL0_IF6_CONFIG2_PIDFLT_REC_ALL); in HAL_TSO_Set_PidBypass()
1039 _REG16_CLR(FILE_CONFIG,TSO_FILE_CONFIG_TSO_RADDR_READ); in HAL_TSO_Get_Filein_ReadAddr()
[all …]
/utopia/UTPA2-700.0.x/modules/dmx/hal/k6/tso/
H A DhalTSO.c95 #define _REG16_CLR(reg, value); _HAL_REG16_W(reg, RESET_FLAG1(_HAL_REG16_R(reg), value)); macro
252 _REG16_CLR(&(_TSOCtrl->SW_RSTZ), TSO_SW_RSTZ);//low active in HAL_TSO_Reset_All()
256 _REG16_CLR(&(_TSOCtrl->SW_RSTZ), TSO_SW_RST_ALL | TSO_SW_RST_ALL1); in HAL_TSO_Reset_All()
911 _REG16_CLR(&(_TSOCtrl->CHANNEL0_IF1_CONFIG2),TSO_CHCFG_PIDFLT_REC_ALL); in HAL_TSO_Set_PidBypass()
914 … _REG16_CLR(&(_TSOCtrl->CHANNEL0_IF2_CONFIG2),TSO_CHANNEL0_IF2_CONFIG2_PIDFLT_REC_ALL); in HAL_TSO_Set_PidBypass()
917 … _REG16_CLR(&(_TSOCtrl->CHANNEL0_IF3_CONFIG2),TSO_CHANNEL0_IF3_CONFIG2_PIDFLT_REC_ALL); in HAL_TSO_Set_PidBypass()
920 … _REG16_CLR(&(_TSOCtrl->CHANNEL0_IF4_CONFIG2),TSO_CHANNEL0_IF4_CONFIG2_PIDFLT_REC_ALL); in HAL_TSO_Set_PidBypass()
923 … _REG16_CLR(&(_TSOCtrl->CHANNEL0_IF5_CONFIG2),TSO_CHANNEL0_IF5_CONFIG2_PIDFLT_REC_ALL); in HAL_TSO_Set_PidBypass()
926 … _REG16_CLR(&(_TSOCtrl->CHANNEL0_IF6_CONFIG2),TSO_CHANNEL0_IF6_CONFIG2_PIDFLT_REC_ALL); in HAL_TSO_Set_PidBypass()
1030 _REG16_CLR(FILE_CONFIG,TSO_FILE_CONFIG_TSO_RADDR_READ); in HAL_TSO_Get_Filein_ReadAddr()
[all …]
/utopia/UTPA2-700.0.x/modules/dmx/hal/curry/tso/
H A DhalTSO.c95 #define _REG16_CLR(reg, value); _HAL_REG16_W(reg, RESET_FLAG1(_HAL_REG16_R(reg), value)); macro
252 _REG16_CLR(&(_TSOCtrl->SW_RSTZ), TSO_SW_RSTZ);//low active in HAL_TSO_Reset_All()
256 _REG16_CLR(&(_TSOCtrl->SW_RSTZ), TSO_SW_RST_ALL | TSO_SW_RST_ALL1); in HAL_TSO_Reset_All()
908 _REG16_CLR(&(_TSOCtrl->CHANNEL0_IF1_CONFIG2),TSO_CHCFG_PIDFLT_REC_ALL); in HAL_TSO_Set_PidBypass()
911 … _REG16_CLR(&(_TSOCtrl->CHANNEL0_IF2_CONFIG2),TSO_CHANNEL0_IF2_CONFIG2_PIDFLT_REC_ALL); in HAL_TSO_Set_PidBypass()
914 … _REG16_CLR(&(_TSOCtrl->CHANNEL0_IF3_CONFIG2),TSO_CHANNEL0_IF3_CONFIG2_PIDFLT_REC_ALL); in HAL_TSO_Set_PidBypass()
917 … _REG16_CLR(&(_TSOCtrl->CHANNEL0_IF4_CONFIG2),TSO_CHANNEL0_IF4_CONFIG2_PIDFLT_REC_ALL); in HAL_TSO_Set_PidBypass()
920 … _REG16_CLR(&(_TSOCtrl->CHANNEL0_IF5_CONFIG2),TSO_CHANNEL0_IF5_CONFIG2_PIDFLT_REC_ALL); in HAL_TSO_Set_PidBypass()
923 … _REG16_CLR(&(_TSOCtrl->CHANNEL0_IF6_CONFIG2),TSO_CHANNEL0_IF6_CONFIG2_PIDFLT_REC_ALL); in HAL_TSO_Set_PidBypass()
998 _REG16_CLR(FILE_CONFIG,TSO_FILE_CONFIG_TSO_RADDR_READ); in HAL_TSO_Get_Filein_ReadAddr()
[all …]
/utopia/UTPA2-700.0.x/modules/dmx/hal/kano/tso/
H A DhalTSO.c95 #define _REG16_CLR(reg, value); _HAL_REG16_W(reg, RESET_FLAG1(_HAL_REG16_R(reg), value)); macro
252 _REG16_CLR(&(_TSOCtrl->SW_RSTZ), TSO_SW_RSTZ);//low active in HAL_TSO_Reset_All()
256 _REG16_CLR(&(_TSOCtrl->SW_RSTZ), TSO_SW_RST_ALL | TSO_SW_RST_ALL1); in HAL_TSO_Reset_All()
908 _REG16_CLR(&(_TSOCtrl->CHANNEL0_IF1_CONFIG2),TSO_CHCFG_PIDFLT_REC_ALL); in HAL_TSO_Set_PidBypass()
911 … _REG16_CLR(&(_TSOCtrl->CHANNEL0_IF2_CONFIG2),TSO_CHANNEL0_IF2_CONFIG2_PIDFLT_REC_ALL); in HAL_TSO_Set_PidBypass()
914 … _REG16_CLR(&(_TSOCtrl->CHANNEL0_IF3_CONFIG2),TSO_CHANNEL0_IF3_CONFIG2_PIDFLT_REC_ALL); in HAL_TSO_Set_PidBypass()
917 … _REG16_CLR(&(_TSOCtrl->CHANNEL0_IF4_CONFIG2),TSO_CHANNEL0_IF4_CONFIG2_PIDFLT_REC_ALL); in HAL_TSO_Set_PidBypass()
920 … _REG16_CLR(&(_TSOCtrl->CHANNEL0_IF5_CONFIG2),TSO_CHANNEL0_IF5_CONFIG2_PIDFLT_REC_ALL); in HAL_TSO_Set_PidBypass()
923 … _REG16_CLR(&(_TSOCtrl->CHANNEL0_IF6_CONFIG2),TSO_CHANNEL0_IF6_CONFIG2_PIDFLT_REC_ALL); in HAL_TSO_Set_PidBypass()
998 _REG16_CLR(FILE_CONFIG,TSO_FILE_CONFIG_TSO_RADDR_READ); in HAL_TSO_Get_Filein_ReadAddr()
[all …]