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Searched refs:VQ0_BASE (Results 1 – 25 of 35) sorted by relevance

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/utopia/UTPA2-700.0.x/modules/dmx/hal/messi/tsp/
H A DregTSP.h844 REG32 VQ0_BASE; // 0x3a2c80 0x20 member
/utopia/UTPA2-700.0.x/modules/dmx/hal/mainz/tsp/
H A DregTSP.h844 REG32 VQ0_BASE; // 0x3a2c80 0x20 member
/utopia/UTPA2-700.0.x/modules/dmx/hal/mooney/tsp/
H A DregTSP.h843 REG32 VQ0_BASE; // 0x3a2c80 0x20 member
/utopia/UTPA2-700.0.x/modules/dmx/hal/k7u/tsp/
H A DregTSP.h975 REG32 VQ0_BASE; // 0xbf802c80 0x20 member
/utopia/UTPA2-700.0.x/modules/dmx/hal/maldives/tsp/
H A DhalTSP.c4061 pReg = &(_TspCtrl[0].VQ0_BASE); in HAL_TSP_SetVQBuffer()
4118 REG32 *pReg = &_TspCtrl[0].VQ0_BASE; in HAL_TSP_VQueue_Reset()
4144 REG32 *pReg = &_TspCtrl[0].VQ0_BASE; in HAL_TSP_VQueue_OverflowInt_En()
H A DregTSP.h1000 REG32 VQ0_BASE; // 0xbf802c80 0x20 member
/utopia/UTPA2-700.0.x/modules/dmx/hal/manhattan/tsp/
H A DregTSP.h1006 REG32 VQ0_BASE; // 0xbf802c80 0x20 member
H A DhalTSP.c4455 pReg = &(_TspCtrl[0].VQ0_BASE); in HAL_TSP_SetVQBuffer()
4522 REG32 *pReg = &_TspCtrl[0].VQ0_BASE; in HAL_TSP_VQueue_Reset()
4552 REG32 *pReg = &_TspCtrl[0].VQ0_BASE; in HAL_TSP_VQueue_OverflowInt_En()
/utopia/UTPA2-700.0.x/modules/dmx/hal/macan/tsp/
H A DregTSP.h997 REG32 VQ0_BASE; // 0xbf802c80 0x20 member
H A DhalTSP.c4418 pReg = &(_TspCtrl[0].VQ0_BASE); in HAL_TSP_SetVQBuffer()
4485 REG32 *pReg = &_TspCtrl[0].VQ0_BASE; in HAL_TSP_VQueue_Reset()
4515 REG32 *pReg = &_TspCtrl[0].VQ0_BASE; in HAL_TSP_VQueue_OverflowInt_En()
/utopia/UTPA2-700.0.x/modules/dmx/hal/mustang/tsp/
H A DregTSP.h1033 REG32 VQ0_BASE; // 0xbf802c80 0x20 member
H A DhalTSP.c4785 pReg = &(_TspCtrl[0].VQ0_BASE); in HAL_TSP_SetVQBuffer()
4852 REG32 *pReg = &_TspCtrl[0].VQ0_BASE; in HAL_TSP_VQueue_Reset()
4882 REG32 *pReg = &_TspCtrl[0].VQ0_BASE; in HAL_TSP_VQueue_OverflowInt_En()
/utopia/UTPA2-700.0.x/modules/dmx/hal/M7621/tsp/
H A DregTSP.h1037 REG32 VQ0_BASE; // 0xbf802c80 0x20 member
H A DhalTSP.c5110 pReg = &(_TspCtrl[0].VQ0_BASE); in HAL_TSP_SetVQBuffer()
5177 REG32 *pReg = &_TspCtrl[0].VQ0_BASE; in HAL_TSP_VQueue_Reset()
5207 REG32 *pReg = &_TspCtrl[0].VQ0_BASE; in HAL_TSP_VQueue_OverflowInt_En()
/utopia/UTPA2-700.0.x/modules/dmx/hal/maxim/tsp/
H A DregTSP.h1037 REG32 VQ0_BASE; // 0xbf802c80 0x20 member
H A DhalTSP.c5127 pReg = &(_TspCtrl[0].VQ0_BASE); in HAL_TSP_SetVQBuffer()
5194 REG32 *pReg = &_TspCtrl[0].VQ0_BASE; in HAL_TSP_VQueue_Reset()
5224 REG32 *pReg = &_TspCtrl[0].VQ0_BASE; in HAL_TSP_VQueue_OverflowInt_En()
/utopia/UTPA2-700.0.x/modules/dmx/hal/maserati/tsp/
H A DregTSP.h1052 REG32 VQ0_BASE; // 0xbf802c80 0x20 member
H A DhalTSP.c5183 pReg = &(_TspCtrl[0].VQ0_BASE); in HAL_TSP_SetVQBuffer()
5250 REG32 *pReg = &_TspCtrl[0].VQ0_BASE; in HAL_TSP_VQueue_Reset()
5280 REG32 *pReg = &_TspCtrl[0].VQ0_BASE; in HAL_TSP_VQueue_OverflowInt_En()
/utopia/UTPA2-700.0.x/modules/dmx/hal/M7821/tsp/
H A DregTSP.h1052 REG32 VQ0_BASE; // 0xbf802c80 0x20 member
H A DhalTSP.c5144 pReg = &(_TspCtrl[0].VQ0_BASE); in HAL_TSP_SetVQBuffer()
5211 REG32 *pReg = &_TspCtrl[0].VQ0_BASE; in HAL_TSP_VQueue_Reset()
5241 REG32 *pReg = &_TspCtrl[0].VQ0_BASE; in HAL_TSP_VQueue_OverflowInt_En()
/utopia/UTPA2-700.0.x/modules/dmx/hal/curry/tsp/
H A DregTSP.h895 REG32 VQ0_BASE; // 0xbf802c80 0x20 member
/utopia/UTPA2-700.0.x/modules/dmx/hal/kano/tsp/
H A DregTSP.h931 REG32 VQ0_BASE; // 0xbf802c80 0x20 member
/utopia/UTPA2-700.0.x/modules/dscmb/hal/kano/nsk2/
H A DregTSP.h933 REG32 VQ0_BASE; // 0xbf802c80 0x20 member
/utopia/UTPA2-700.0.x/modules/dscmb/hal/k6/nsk2/
H A DregTSP.h971 REG32 VQ0_BASE; // 0xbf802c80 0x20 member
/utopia/UTPA2-700.0.x/modules/dscmb/hal/k6lite/nsk2/
H A DregTSP.h952 REG32 VQ0_BASE; // 0xbf802c80 0x20 member

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