Home
last modified time | relevance | path

Searched refs:REG_CLKGEN0_TSO_OUT_DIV_SEL_MASK (Results 1 – 12 of 12) sorted by relevance

/utopia/UTPA2-700.0.x/modules/dmx/hal/maldives/tso/
H A DhalTSO.c184 #define REG_CLKGEN0_TSO_OUT_DIV_SEL_MASK 0x0001 macro
767 …(TSO_CLKGEN1_REG(REG_CLKGEN1_TSO_OUT_CLK) & ~REG_CLKGEN0_TSO_OUT_DIV_SEL_MASK) | *pu16ClkOutDivSrc… in HAL_TSO_TSOOutDiv()
774 …*pu16ClkOutDivSrcSel = TSO_CLKGEN1_REG(REG_CLKGEN1_TSO_OUT_CLK) & REG_CLKGEN0_TSO_OUT_DIV_SEL_MASK; in HAL_TSO_TSOOutDiv()
/utopia/UTPA2-700.0.x/modules/dmx/hal/macan/tso/
H A DhalTSO.c173 #define REG_CLKGEN0_TSO_OUT_DIV_SEL_MASK 0x0001UL macro
913 …(TSO_CLKGEN0_REG(REG_CLKGEN0_TSO_OUT_CLK) & ~REG_CLKGEN0_TSO_OUT_DIV_SEL_MASK) | (*pu16ClkOutDivSr… in HAL_TSO_TSOOutDiv()
920 …*pu16ClkOutDivSrcSel = TSO_CLKGEN0_REG(REG_CLKGEN0_TSO_OUT_CLK) & REG_CLKGEN0_TSO_OUT_DIV_SEL_MASK; in HAL_TSO_TSOOutDiv()
/utopia/UTPA2-700.0.x/modules/dmx/hal/curry/tso/
H A DhalTSO.c122 #define REG_CLKGEN0_TSO_OUT_DIV_SEL_MASK 0x0040 macro
679 …(TSO_CLKGEN0_REG(REG_CLKGEN0_TSO_OUT_PHASE) & ~REG_CLKGEN0_TSO_OUT_DIV_SEL_MASK) | (*pu16ClkOutDiv… in HAL_TSO_TSOOutDiv()
686 …u16ClkOutDivSrcSel = TSO_CLKGEN0_REG(REG_CLKGEN0_TSO_OUT_PHASE) & REG_CLKGEN0_TSO_OUT_DIV_SEL_MASK; in HAL_TSO_TSOOutDiv()
/utopia/UTPA2-700.0.x/modules/dmx/hal/kano/tso/
H A DhalTSO.c122 #define REG_CLKGEN0_TSO_OUT_DIV_SEL_MASK 0x0040 macro
679 …(TSO_CLKGEN0_REG(REG_CLKGEN0_TSO_OUT_PHASE) & ~REG_CLKGEN0_TSO_OUT_DIV_SEL_MASK) | (*pu16ClkOutDiv… in HAL_TSO_TSOOutDiv()
686 …u16ClkOutDivSrcSel = TSO_CLKGEN0_REG(REG_CLKGEN0_TSO_OUT_PHASE) & REG_CLKGEN0_TSO_OUT_DIV_SEL_MASK; in HAL_TSO_TSOOutDiv()
/utopia/UTPA2-700.0.x/modules/dmx/hal/manhattan/tso/
H A DhalTSO.c181 #define REG_CLKGEN0_TSO_OUT_DIV_SEL_MASK 0x0001UL macro
941 …(TSO_CLKGEN0_REG(REG_CLKGEN0_TSO_OUT_CLK) & ~REG_CLKGEN0_TSO_OUT_DIV_SEL_MASK) | (*pu16ClkOutDivSr… in HAL_TSO_TSOOutDiv()
948 …*pu16ClkOutDivSrcSel = TSO_CLKGEN0_REG(REG_CLKGEN0_TSO_OUT_CLK) & REG_CLKGEN0_TSO_OUT_DIV_SEL_MASK; in HAL_TSO_TSOOutDiv()
/utopia/UTPA2-700.0.x/modules/dmx/hal/k6/tso/
H A DhalTSO.c122 #define REG_CLKGEN0_TSO_OUT_DIV_SEL_MASK 0x0040 macro
682 …(TSO_CLKGEN0_REG(REG_CLKGEN0_TSO_OUT_PHASE) & ~REG_CLKGEN0_TSO_OUT_DIV_SEL_MASK) | (*pu16ClkOutDiv… in HAL_TSO_TSOOutDiv()
689 …u16ClkOutDivSrcSel = TSO_CLKGEN0_REG(REG_CLKGEN0_TSO_OUT_PHASE) & REG_CLKGEN0_TSO_OUT_DIV_SEL_MASK; in HAL_TSO_TSOOutDiv()
/utopia/UTPA2-700.0.x/modules/dmx/hal/M7621/tso/
H A DhalTSO.c188 #define REG_CLKGEN0_TSO_OUT_DIV_SEL_MASK 0x0001UL macro
991 …(TSO_CLKGEN0_REG(REG_CLKGEN0_TSO_OUT_CLK) & ~REG_CLKGEN0_TSO_OUT_DIV_SEL_MASK) | (*pu16ClkOutDivSr… in HAL_TSO_TSOOutDiv()
998 …*pu16ClkOutDivSrcSel = TSO_CLKGEN0_REG(REG_CLKGEN0_TSO_OUT_CLK) & REG_CLKGEN0_TSO_OUT_DIV_SEL_MASK; in HAL_TSO_TSOOutDiv()
/utopia/UTPA2-700.0.x/modules/dmx/hal/M7821/tso/
H A DhalTSO.c189 #define REG_CLKGEN0_TSO_OUT_DIV_SEL_MASK 0x0001UL macro
1016 …(TSO_CLKGEN0_REG(REG_CLKGEN0_TSO_OUT_CLK) & ~REG_CLKGEN0_TSO_OUT_DIV_SEL_MASK) | (*pu16ClkOutDivSr… in HAL_TSO_TSOOutDiv()
1023 …*pu16ClkOutDivSrcSel = TSO_CLKGEN0_REG(REG_CLKGEN0_TSO_OUT_CLK) & REG_CLKGEN0_TSO_OUT_DIV_SEL_MASK; in HAL_TSO_TSOOutDiv()
/utopia/UTPA2-700.0.x/modules/dmx/hal/k6lite/tso/
H A DhalTSO.c122 #define REG_CLKGEN0_TSO_OUT_DIV_SEL_MASK 0x0040 macro
680 …(TSO_CLKGEN0_REG(REG_CLKGEN0_TSO_OUT_PHASE) & ~REG_CLKGEN0_TSO_OUT_DIV_SEL_MASK) | (*pu16ClkOutDiv… in HAL_TSO_TSOOutDiv()
687 …u16ClkOutDivSrcSel = TSO_CLKGEN0_REG(REG_CLKGEN0_TSO_OUT_PHASE) & REG_CLKGEN0_TSO_OUT_DIV_SEL_MASK; in HAL_TSO_TSOOutDiv()
/utopia/UTPA2-700.0.x/modules/dmx/hal/maserati/tso/
H A DhalTSO.c189 #define REG_CLKGEN0_TSO_OUT_DIV_SEL_MASK 0x0001UL macro
1016 …(TSO_CLKGEN0_REG(REG_CLKGEN0_TSO_OUT_CLK) & ~REG_CLKGEN0_TSO_OUT_DIV_SEL_MASK) | (*pu16ClkOutDivSr… in HAL_TSO_TSOOutDiv()
1023 …*pu16ClkOutDivSrcSel = TSO_CLKGEN0_REG(REG_CLKGEN0_TSO_OUT_CLK) & REG_CLKGEN0_TSO_OUT_DIV_SEL_MASK; in HAL_TSO_TSOOutDiv()
/utopia/UTPA2-700.0.x/modules/dmx/hal/maxim/tso/
H A DhalTSO.c188 #define REG_CLKGEN0_TSO_OUT_DIV_SEL_MASK 0x0001UL macro
991 …(TSO_CLKGEN0_REG(REG_CLKGEN0_TSO_OUT_CLK) & ~REG_CLKGEN0_TSO_OUT_DIV_SEL_MASK) | (*pu16ClkOutDivSr… in HAL_TSO_TSOOutDiv()
998 …*pu16ClkOutDivSrcSel = TSO_CLKGEN0_REG(REG_CLKGEN0_TSO_OUT_CLK) & REG_CLKGEN0_TSO_OUT_DIV_SEL_MASK; in HAL_TSO_TSOOutDiv()
/utopia/UTPA2-700.0.x/modules/dmx/hal/k7u/tso/
H A DhalTSO.c123 #define REG_CLKGEN0_TSO_OUT_DIV_SEL_MASK 0x0040 macro
683 …(TSO_CLKGEN0_REG(REG_CLKGEN0_TSO_OUT_PHASE) & ~REG_CLKGEN0_TSO_OUT_DIV_SEL_MASK) | (*pu16ClkOutDiv… in HAL_TSO_TSOOutDiv()
690 …u16ClkOutDivSrcSel = TSO_CLKGEN0_REG(REG_CLKGEN0_TSO_OUT_PHASE) & REG_CLKGEN0_TSO_OUT_DIV_SEL_MASK; in HAL_TSO_TSOOutDiv()