Searched refs:REG_CLKGEN0_TSO_OUT_DIVNUM_MASK (Results 1 – 11 of 11) sorted by relevance
168 #define REG_CLKGEN0_TSO_OUT_DIVNUM_MASK 0x001FUL macro916 …(TSO_CLKGEN0_REG(REG_CLKGEN0_TSO_OUT_PHASE) & ~REG_CLKGEN0_TSO_OUT_DIVNUM_MASK) | (*pu16ClkOutDivN… in HAL_TSO_TSOOutDiv()921 … *pu16ClkOutDivNum = TSO_CLKGEN0_REG(REG_CLKGEN0_TSO_OUT_PHASE) & REG_CLKGEN0_TSO_OUT_DIVNUM_MASK; in HAL_TSO_TSOOutDiv()
127 #define REG_CLKGEN0_TSO_OUT_DIVNUM_MASK 0x07C0 macro682 …(TSO_CLKGEN0_REG(REG_CLKGEN0_TSO_OUT_DIVNUM) & ~REG_CLKGEN0_TSO_OUT_DIVNUM_MASK) | (*pu16ClkOutDiv… in HAL_TSO_TSOOutDiv()687 …lkOutDivNum = (TSO_CLKGEN0_REG(REG_CLKGEN0_TSO_OUT_DIVNUM) & REG_CLKGEN0_TSO_OUT_DIVNUM_MASK) >> R… in HAL_TSO_TSOOutDiv()
176 #define REG_CLKGEN0_TSO_OUT_DIVNUM_MASK 0x001FUL macro944 …(TSO_CLKGEN0_REG(REG_CLKGEN0_TSO_OUT_PHASE) & ~REG_CLKGEN0_TSO_OUT_DIVNUM_MASK) | (*pu16ClkOutDivN… in HAL_TSO_TSOOutDiv()949 … *pu16ClkOutDivNum = TSO_CLKGEN0_REG(REG_CLKGEN0_TSO_OUT_PHASE) & REG_CLKGEN0_TSO_OUT_DIVNUM_MASK; in HAL_TSO_TSOOutDiv()
127 #define REG_CLKGEN0_TSO_OUT_DIVNUM_MASK 0x07C0 macro685 …(TSO_CLKGEN0_REG(REG_CLKGEN0_TSO_OUT_DIVNUM) & ~REG_CLKGEN0_TSO_OUT_DIVNUM_MASK) | (*pu16ClkOutDiv… in HAL_TSO_TSOOutDiv()690 …lkOutDivNum = (TSO_CLKGEN0_REG(REG_CLKGEN0_TSO_OUT_DIVNUM) & REG_CLKGEN0_TSO_OUT_DIVNUM_MASK) >> R… in HAL_TSO_TSOOutDiv()
183 #define REG_CLKGEN0_TSO_OUT_DIVNUM_MASK 0x001FUL macro994 …(TSO_CLKGEN0_REG(REG_CLKGEN0_TSO_OUT_PHASE) & ~REG_CLKGEN0_TSO_OUT_DIVNUM_MASK) | (*pu16ClkOutDivN… in HAL_TSO_TSOOutDiv()999 … *pu16ClkOutDivNum = TSO_CLKGEN0_REG(REG_CLKGEN0_TSO_OUT_PHASE) & REG_CLKGEN0_TSO_OUT_DIVNUM_MASK; in HAL_TSO_TSOOutDiv()
184 #define REG_CLKGEN0_TSO_OUT_DIVNUM_MASK 0x001FUL macro1019 …(TSO_CLKGEN0_REG(REG_CLKGEN0_TSO_OUT_PHASE) & ~REG_CLKGEN0_TSO_OUT_DIVNUM_MASK) | (*pu16ClkOutDivN… in HAL_TSO_TSOOutDiv()1024 … *pu16ClkOutDivNum = TSO_CLKGEN0_REG(REG_CLKGEN0_TSO_OUT_PHASE) & REG_CLKGEN0_TSO_OUT_DIVNUM_MASK; in HAL_TSO_TSOOutDiv()
127 #define REG_CLKGEN0_TSO_OUT_DIVNUM_MASK 0x07C0 macro683 …(TSO_CLKGEN0_REG(REG_CLKGEN0_TSO_OUT_DIVNUM) & ~REG_CLKGEN0_TSO_OUT_DIVNUM_MASK) | (*pu16ClkOutDiv… in HAL_TSO_TSOOutDiv()688 …lkOutDivNum = (TSO_CLKGEN0_REG(REG_CLKGEN0_TSO_OUT_DIVNUM) & REG_CLKGEN0_TSO_OUT_DIVNUM_MASK) >> R… in HAL_TSO_TSOOutDiv()
128 #define REG_CLKGEN0_TSO_OUT_DIVNUM_MASK 0x07C0 macro686 …(TSO_CLKGEN0_REG(REG_CLKGEN0_TSO_OUT_DIVNUM) & ~REG_CLKGEN0_TSO_OUT_DIVNUM_MASK) | (*pu16ClkOutDiv… in HAL_TSO_TSOOutDiv()691 …lkOutDivNum = (TSO_CLKGEN0_REG(REG_CLKGEN0_TSO_OUT_DIVNUM) & REG_CLKGEN0_TSO_OUT_DIVNUM_MASK) >> R… in HAL_TSO_TSOOutDiv()