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Searched refs:REG_CLKGEN0_TSO_OUT_CLK_INVERT (Results 1 – 11 of 11) sorted by relevance

/utopia/UTPA2-700.0.x/modules/dmx/hal/macan/tso/
H A DhalTSO.c188 #define REG_CLKGEN0_TSO_OUT_CLK_INVERT 0x0200UL macro
945 u16Clk |= REG_CLKGEN0_TSO_OUT_CLK_INVERT; in HAL_TSO_OutClk()
954 … *pbClkInvert = ((u16Clk & REG_CLKGEN0_TSO_OUT_CLK_INVERT) == REG_CLKGEN0_TSO_OUT_CLK_INVERT); in HAL_TSO_OutClk()
/utopia/UTPA2-700.0.x/modules/dmx/hal/curry/tso/
H A DhalTSO.c135 #define REG_CLKGEN0_TSO_OUT_CLK_INVERT 0x0002 macro
807 u16Clk |= REG_CLKGEN0_TSO_OUT_CLK_INVERT; in HAL_TSO_OutClk()
867 … *pbClkInvert = ((u16Clk & REG_CLKGEN0_TSO_OUT_CLK_INVERT) == REG_CLKGEN0_TSO_OUT_CLK_INVERT); in HAL_TSO_OutClk()
/utopia/UTPA2-700.0.x/modules/dmx/hal/kano/tso/
H A DhalTSO.c135 #define REG_CLKGEN0_TSO_OUT_CLK_INVERT 0x0002 macro
807 u16Clk |= REG_CLKGEN0_TSO_OUT_CLK_INVERT; in HAL_TSO_OutClk()
867 … *pbClkInvert = ((u16Clk & REG_CLKGEN0_TSO_OUT_CLK_INVERT) == REG_CLKGEN0_TSO_OUT_CLK_INVERT); in HAL_TSO_OutClk()
/utopia/UTPA2-700.0.x/modules/dmx/hal/manhattan/tso/
H A DhalTSO.c196 #define REG_CLKGEN0_TSO_OUT_CLK_INVERT 0x0200UL macro
973 u16Clk |= REG_CLKGEN0_TSO_OUT_CLK_INVERT; in HAL_TSO_OutClk()
982 … *pbClkInvert = ((u16Clk & REG_CLKGEN0_TSO_OUT_CLK_INVERT) == REG_CLKGEN0_TSO_OUT_CLK_INVERT); in HAL_TSO_OutClk()
/utopia/UTPA2-700.0.x/modules/dmx/hal/k6/tso/
H A DhalTSO.c135 #define REG_CLKGEN0_TSO_OUT_CLK_INVERT 0x0002 macro
810 u16Clk |= REG_CLKGEN0_TSO_OUT_CLK_INVERT; in HAL_TSO_OutClk()
870 … *pbClkInvert = ((u16Clk & REG_CLKGEN0_TSO_OUT_CLK_INVERT) == REG_CLKGEN0_TSO_OUT_CLK_INVERT); in HAL_TSO_OutClk()
/utopia/UTPA2-700.0.x/modules/dmx/hal/M7621/tso/
H A DhalTSO.c202 #define REG_CLKGEN0_TSO_OUT_CLK_INVERT 0x0200UL macro
1023 u16Clk |= REG_CLKGEN0_TSO_OUT_CLK_INVERT; in HAL_TSO_OutClk()
1032 … *pbClkInvert = ((u16Clk & REG_CLKGEN0_TSO_OUT_CLK_INVERT) == REG_CLKGEN0_TSO_OUT_CLK_INVERT); in HAL_TSO_OutClk()
/utopia/UTPA2-700.0.x/modules/dmx/hal/M7821/tso/
H A DhalTSO.c204 #define REG_CLKGEN0_TSO_OUT_CLK_INVERT 0x0200UL macro
1048 u16Clk |= REG_CLKGEN0_TSO_OUT_CLK_INVERT; in HAL_TSO_OutClk()
1057 … *pbClkInvert = ((u16Clk & REG_CLKGEN0_TSO_OUT_CLK_INVERT) == REG_CLKGEN0_TSO_OUT_CLK_INVERT); in HAL_TSO_OutClk()
/utopia/UTPA2-700.0.x/modules/dmx/hal/k6lite/tso/
H A DhalTSO.c135 #define REG_CLKGEN0_TSO_OUT_CLK_INVERT 0x0002 macro
816 u16Clk |= REG_CLKGEN0_TSO_OUT_CLK_INVERT; in HAL_TSO_OutClk()
876 … *pbClkInvert = ((u16Clk & REG_CLKGEN0_TSO_OUT_CLK_INVERT) == REG_CLKGEN0_TSO_OUT_CLK_INVERT); in HAL_TSO_OutClk()
/utopia/UTPA2-700.0.x/modules/dmx/hal/maserati/tso/
H A DhalTSO.c204 #define REG_CLKGEN0_TSO_OUT_CLK_INVERT 0x0200UL macro
1048 u16Clk |= REG_CLKGEN0_TSO_OUT_CLK_INVERT; in HAL_TSO_OutClk()
1057 … *pbClkInvert = ((u16Clk & REG_CLKGEN0_TSO_OUT_CLK_INVERT) == REG_CLKGEN0_TSO_OUT_CLK_INVERT); in HAL_TSO_OutClk()
/utopia/UTPA2-700.0.x/modules/dmx/hal/maxim/tso/
H A DhalTSO.c202 #define REG_CLKGEN0_TSO_OUT_CLK_INVERT 0x0200UL macro
1023 u16Clk |= REG_CLKGEN0_TSO_OUT_CLK_INVERT; in HAL_TSO_OutClk()
1032 … *pbClkInvert = ((u16Clk & REG_CLKGEN0_TSO_OUT_CLK_INVERT) == REG_CLKGEN0_TSO_OUT_CLK_INVERT); in HAL_TSO_OutClk()
/utopia/UTPA2-700.0.x/modules/dmx/hal/k7u/tso/
H A DhalTSO.c136 #define REG_CLKGEN0_TSO_OUT_CLK_INVERT 0x0002 macro
819 u16Clk |= REG_CLKGEN0_TSO_OUT_CLK_INVERT; in HAL_TSO_OutClk()
879 … *pbClkInvert = ((u16Clk & REG_CLKGEN0_TSO_OUT_CLK_INVERT) == REG_CLKGEN0_TSO_OUT_CLK_INVERT); in HAL_TSO_OutClk()