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Searched refs:GOP_BIT3 (Results 1 – 25 of 64) sorted by relevance

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/utopia/UTPA2-700.0.x/modules/graphic/hal/k6lite/gop/
H A DhalGOP.c341 if (u16GopMask&GOP_BIT3) in HAL_GOP_SetGOPACKMask()
488 HAL_GOP_Write16Reg(pGOPHalLocal, u32bankoff+GOP_4G_H121, GOP_BIT3, GOP_BIT3); // SD data Enable in HAL_GOP_Init()
545 …HAL_GOP_Write16Reg(pGOPHalLocal, GOP_AFBCCLK, CKG_AFBCCLK_432, GOP_BIT2|GOP_BIT3); //Clk… in HAL_GOP_Init()
562 …HAL_GOP_Write16Reg(pGOPHalLocal, u32bankoff+GOP_4G_MIU_SEL, u8MIUSel<<2, GOP_BIT2|GOP_BIT3 );//GWI… in HAL_GOP_Init()
1196 u16Regval &= (~(GOP_BIT3|GOP_BIT4)); in HAL_GOP_SetMixerDst()
1199 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_MIXER_CTRL, u16Regval, (GOP_BIT3|GOP_BIT4)); in HAL_GOP_SetMixerDst()
1448 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_SC_VOP2BLENDING_L, GOP_BIT3, GOP_BIT3); in HAL_GOP_SetGOPEnable2SC()
1450 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_SC_VOP2BLENDING_L, 0, GOP_BIT3); in HAL_GOP_SetGOPEnable2SC()
1482 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_SC_VOP2BLENDING_H, GOP_BIT3, GOP_BIT3); in HAL_GOP_SetGOPEnable2SC()
1484 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_SC_VOP2BLENDING_H, 0, GOP_BIT3); in HAL_GOP_SetGOPEnable2SC()
[all …]
H A DregGOP.h246 #define CKG_GOPG0_MASK (GOP_BIT4 | GOP_BIT3 | GOP_BIT2)
261 #define CKG_GOPMIXER_MASK (GOP_BIT4|GOP_BIT3 | GOP_BIT2)
280 #define CKG_GOPG2_MASK (GOP_BIT4 | GOP_BIT3 | GOP_BIT2)
296 #define CKG_GOPG4_MASK (GOP_BIT4 | GOP_BIT3 | GOP_BIT2)
313 #define CKG_SRAM1_MASK (GOP_BIT2|GOP_BIT3)
319 #define CKG_LB_SRAM1_MASK (GOP_BIT2|GOP_BIT3)
327 #define CKG_AFBCCLK_DISABLE_CLK_MASK (GOP_BIT0|GOP_BIT1|GOP_BIT2|GOP_BIT3)
/utopia/UTPA2-700.0.x/modules/graphic/hal/k6/gop/
H A DhalGOP.c342 if (u16GopMask&GOP_BIT3) in HAL_GOP_SetGOPACKMask()
493 HAL_GOP_Write16Reg(pGOPHalLocal, u32bankoff+GOP_4G_H121, GOP_BIT3, GOP_BIT3); // SD data Enable in HAL_GOP_Init()
550 …HAL_GOP_Write16Reg(pGOPHalLocal, GOP_AFBCCLK, CKG_AFBCCLK_432, GOP_BIT2|GOP_BIT3); //Clk… in HAL_GOP_Init()
567 …HAL_GOP_Write16Reg(pGOPHalLocal, u32bankoff+GOP_4G_MIU_SEL, u8MIUSel<<2, GOP_BIT2|GOP_BIT3 );//GWI… in HAL_GOP_Init()
1202 u16Regval &= (~(GOP_BIT3|GOP_BIT4)); in HAL_GOP_SetMixerDst()
1205 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_MIXER_CTRL, u16Regval, (GOP_BIT3|GOP_BIT4)); in HAL_GOP_SetMixerDst()
1454 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_SC_VOP2BLENDING_L, GOP_BIT3, GOP_BIT3); in HAL_GOP_SetGOPEnable2SC()
1456 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_SC_VOP2BLENDING_L, 0, GOP_BIT3); in HAL_GOP_SetGOPEnable2SC()
1488 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_SC_VOP2BLENDING_H, GOP_BIT3, GOP_BIT3); in HAL_GOP_SetGOPEnable2SC()
1490 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_SC_VOP2BLENDING_H, 0, GOP_BIT3); in HAL_GOP_SetGOPEnable2SC()
[all …]
H A DregGOP.h246 #define CKG_GOPG0_MASK (GOP_BIT4 | GOP_BIT3 | GOP_BIT2)
261 #define CKG_GOPMIXER_MASK (GOP_BIT4|GOP_BIT3 | GOP_BIT2)
280 #define CKG_GOPG2_MASK (GOP_BIT4 | GOP_BIT3 | GOP_BIT2)
296 #define CKG_GOPG4_MASK (GOP_BIT4 | GOP_BIT3 | GOP_BIT2)
313 #define CKG_SRAM1_MASK (GOP_BIT2|GOP_BIT3)
319 #define CKG_LB_SRAM1_MASK (GOP_BIT2|GOP_BIT3)
327 #define CKG_AFBCCLK_DISABLE_CLK_MASK (GOP_BIT0|GOP_BIT1|GOP_BIT2|GOP_BIT3)
/utopia/UTPA2-700.0.x/modules/graphic/hal/kastor/gop/
H A DhalGOP.c314 if (u16GopMask&GOP_BIT3) in HAL_GOP_SetGOPACKMask()
464 HAL_GOP_Write16Reg(pGOPHalLocal, u32bankoff+GOP_4G_H121, GOP_BIT3, GOP_BIT3); // SD data Enable in HAL_GOP_Init()
515 …HAL_GOP_Write16Reg(pGOPHalLocal, GOP_AFBCCLK, CKG_AFBCCLK_432, GOP_BIT2|GOP_BIT3); //Clk… in HAL_GOP_Init()
532 …HAL_GOP_Write16Reg(pGOPHalLocal, u32bankoff+GOP_4G_MIU_SEL, u8MIUSel<<2, GOP_BIT2|GOP_BIT3 );//GWI… in HAL_GOP_Init()
1161 u16Regval &= (~(GOP_BIT3|GOP_BIT4)); in HAL_GOP_SetMixerDst()
1164 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_MIXER_CTRL, u16Regval, (GOP_BIT3|GOP_BIT4)); in HAL_GOP_SetMixerDst()
1404 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_SC_VOP2BLENDING_L, GOP_BIT3, GOP_BIT3); in HAL_GOP_SetGOPEnable2SC()
1406 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_SC_VOP2BLENDING_L, 0, GOP_BIT3); in HAL_GOP_SetGOPEnable2SC()
1438 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_SC_VOP2BLENDING_H, GOP_BIT3, GOP_BIT3); in HAL_GOP_SetGOPEnable2SC()
1440 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_SC_VOP2BLENDING_H, 0, GOP_BIT3); in HAL_GOP_SetGOPEnable2SC()
[all …]
H A DregGOP.h234 #define CKG_GOPG0_MASK (GOP_BIT4 | GOP_BIT3 | GOP_BIT2)
244 #define CKG_GOPMIXER_MASK (GOP_BIT4|GOP_BIT3 | GOP_BIT2)
259 #define CKG_GOPG2_MASK (GOP_BIT4 | GOP_BIT3 | GOP_BIT2)
272 #define CKG_GOPG4_MASK (GOP_BIT4 | GOP_BIT3 | GOP_BIT2)
292 #define CKG_SRAM1_MASK (GOP_BIT2|GOP_BIT3)
298 #define CKG_LB_SRAM1_MASK (GOP_BIT2|GOP_BIT3)
306 #define CKG_AFBCCLK_DISABLE_CLK_MASK (GOP_BIT0|GOP_BIT1|GOP_BIT2|GOP_BIT3)
/utopia/UTPA2-700.0.x/modules/graphic/hal/curry/gop/
H A DhalGOP.c332 if (u16GopMask&GOP_BIT3) in HAL_GOP_SetGOPACKMask()
482 HAL_GOP_Write16Reg(pGOPHalLocal, u32bankoff+GOP_4G_H121, GOP_BIT3, GOP_BIT3); // SD data Enable in HAL_GOP_Init()
497 HAL_GOP_Write16Reg(pGOPHalLocal, CKG_GOPG0_SCALING, GOP_BIT2|GOP_BIT3 , GOP_REG_WORD_MASK); in HAL_GOP_Init()
543 …HAL_GOP_Write16Reg(pGOPHalLocal, GOP_AFBCCLK, CKG_AFBCCLK_432, GOP_BIT2|GOP_BIT3); //Clk… in HAL_GOP_Init()
557 …HAL_GOP_Write16Reg(pGOPHalLocal, u32bankoff+GOP_4G_MIU_SEL, u8MIUSel<<2, GOP_BIT2|GOP_BIT3 );//GWI… in HAL_GOP_Init()
1165 u16Regval &= (~(GOP_BIT3|GOP_BIT4)); in HAL_GOP_SetMixerDst()
1168 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_MIXER_CTRL, u16Regval, (GOP_BIT3|GOP_BIT4)); in HAL_GOP_SetMixerDst()
1398 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_SC_VOP2BLENDING_L, GOP_BIT3, GOP_BIT3); in HAL_GOP_SetGOPEnable2SC()
1400 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_SC_VOP2BLENDING_L, 0, GOP_BIT3); in HAL_GOP_SetGOPEnable2SC()
1432 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_SC_VOP2BLENDING_H, GOP_BIT3, GOP_BIT3); in HAL_GOP_SetGOPEnable2SC()
[all …]
H A DregGOP.h246 #define CKG_GOPG0_MASK (GOP_BIT5 | GOP_BIT4 | GOP_BIT3 | GOP_BIT2)
263 #define CKG_GOPG0_MG_MASK (GOP_BIT3 | GOP_BIT2)
269 #define CKG_GOPMIXER_MASK (GOP_BIT4|GOP_BIT3 | GOP_BIT2)
284 #define CKG_GOPG2_MASK (GOP_BIT5 |GOP_BIT4 | GOP_BIT3 | GOP_BIT2)
330 #define CKG_SRAM1_MASK (GOP_BIT2|GOP_BIT3)
336 #define CKG_LB_SRAM1_MASK (GOP_BIT2|GOP_BIT3)
344 #define CKG_AFBCCLK_DISABLE_CLK_MASK (GOP_BIT0|GOP_BIT1|GOP_BIT2|GOP_BIT3)
/utopia/UTPA2-700.0.x/modules/graphic/hal/kano/gop/
H A DhalGOP.c325 if (u16GopMask&GOP_BIT3) in HAL_GOP_SetGOPACKMask()
483 HAL_GOP_Write16Reg(pGOPHalLocal, CKG_GOPG0_SCALING, GOP_BIT2|GOP_BIT3 , GOP_REG_WORD_MASK); in HAL_GOP_Init()
531 …HAL_GOP_Write16Reg(pGOPHalLocal, GOP_AFBCCLK, CKG_AFBCCLK_432, GOP_BIT2|GOP_BIT3); //Clk… in HAL_GOP_Init()
545 …HAL_GOP_Write16Reg(pGOPHalLocal, u32bankoff+GOP_4G_MIU_SEL, u8MIUSel<<2, GOP_BIT2|GOP_BIT3 );//GWI… in HAL_GOP_Init()
1171 u16Regval &= (~(GOP_BIT3|GOP_BIT4)); in HAL_GOP_SetMixerDst()
1174 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_MIXER_CTRL, u16Regval, (GOP_BIT3|GOP_BIT4)); in HAL_GOP_SetMixerDst()
1412 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_SC_VOP2BLENDING_L, GOP_BIT3, GOP_BIT3); in HAL_GOP_SetGOPEnable2SC()
1414 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_SC_VOP2BLENDING_L, 0, GOP_BIT3); in HAL_GOP_SetGOPEnable2SC()
1446 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_SC_VOP2BLENDING_H, GOP_BIT3, GOP_BIT3); in HAL_GOP_SetGOPEnable2SC()
1448 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_SC_VOP2BLENDING_H, 0, GOP_BIT3); in HAL_GOP_SetGOPEnable2SC()
[all …]
H A DregGOP.h245 #define CKG_GOPG0_MASK (GOP_BIT5 | GOP_BIT4 | GOP_BIT3 | GOP_BIT2)
262 #define CKG_GOPG0_MG_MASK (GOP_BIT3 | GOP_BIT2)
268 #define CKG_GOPMIXER_MASK (GOP_BIT4|GOP_BIT3 | GOP_BIT2)
283 #define CKG_GOPG2_MASK (GOP_BIT5 |GOP_BIT4 | GOP_BIT3 | GOP_BIT2)
329 #define CKG_SRAM1_MASK (GOP_BIT2|GOP_BIT3)
335 #define CKG_LB_SRAM1_MASK (GOP_BIT2|GOP_BIT3)
343 #define CKG_AFBCCLK_DISABLE_CLK_MASK (GOP_BIT0|GOP_BIT1|GOP_BIT2|GOP_BIT3)
/utopia/UTPA2-700.0.x/modules/graphic/hal/M7621/gop/
H A DregGOP.h228 #define CKG_GOPG0_MASK (GOP_BIT5 | GOP_BIT4 | GOP_BIT3 | GOP_BIT2)
242 #define CKG_GOPG0_MG_MASK (GOP_BIT3 | GOP_BIT2)
255 #define CKG_GOPG2_MASK (GOP_BIT5 |GOP_BIT4 | GOP_BIT3 | GOP_BIT2)
274 #define CKG_GOPG3_MASK (GOP_BIT5 | GOP_BIT4 | GOP_BIT3 | GOP_BIT2)
301 #define CKG_LB_SRAM1_MASK (GOP_BIT2|GOP_BIT3)
309 #define CKG_AFBCCLK_DISABLE_CLK_MASK (GOP_BIT0|GOP_BIT1|GOP_BIT2|GOP_BIT3)
H A DhalGOP.c435 if (u16GopMask&GOP_BIT3) in HAL_GOP_SetGOPACKMask()
654 HAL_GOP_Write16Reg(pGOPHalLocal, CKG_GOPG0_SCALING, GOP_BIT2|GOP_BIT3 , GOP_REG_WORD_MASK); in HAL_GOP_Init()
697 …HAL_GOP_Write16Reg(pGOPHalLocal, GOP_AFBCCLK, CKG_AFBCCLK_432, GOP_BIT2|GOP_BIT3); //Clk… in HAL_GOP_Init()
717 …HAL_GOP_Write16Reg(pGOPHalLocal, u32bankoff+GOP_4G_MIU_SEL, u8MIUSel<<2, GOP_BIT2|GOP_BIT3 );//GWI… in HAL_GOP_Init()
1302 HAL_GOP_Write16Reg(pGOPHalLocal, u32BankOffSet+GOP_4G_CTRL1, u16RegVal, BMASK(GOP_BIT3:0)); in HAL_GOP_GWIN_SetDstPlane()
2418 u16RegVal |= GOP_BIT3; //Disable Sub IP blending in HAL_GOP_SetIPSel2SC()
2428 u16RegVal |= GOP_BIT3; //Disable Sub IP blending in HAL_GOP_SetIPSel2SC()
2438 u16RegVal |= GOP_BIT3; //Disable Sub IP blending in HAL_GOP_SetIPSel2SC()
2487 u16RegVal |= GOP_BIT3; //Disable Sub IP blending in HAL_GOP_SetIPSel2SC()
3153 …HAL_GOP_Write16Reg(pGOPHalLocal, u32BankOffSet+GOP_4G_MIU_SEL, miusel<<2, GOP_BIT2|GOP_BIT3 );//GW… in HAL_GOP_Set_GWIN_INTERNAL_MIU()
[all …]
/utopia/UTPA2-700.0.x/modules/graphic/hal/maxim/gop/
H A DregGOP.h228 #define CKG_GOPG0_MASK (GOP_BIT5 | GOP_BIT4 | GOP_BIT3 | GOP_BIT2)
242 #define CKG_GOPG0_MG_MASK (GOP_BIT3 | GOP_BIT2)
255 #define CKG_GOPG2_MASK (GOP_BIT5 |GOP_BIT4 | GOP_BIT3 | GOP_BIT2)
274 #define CKG_GOPG3_MASK (GOP_BIT5 | GOP_BIT4 | GOP_BIT3 | GOP_BIT2)
301 #define CKG_LB_SRAM1_MASK (GOP_BIT2|GOP_BIT3)
309 #define CKG_AFBCCLK_DISABLE_CLK_MASK (GOP_BIT0|GOP_BIT1|GOP_BIT2|GOP_BIT3)
H A DhalGOP.c435 if (u16GopMask&GOP_BIT3) in HAL_GOP_SetGOPACKMask()
654 HAL_GOP_Write16Reg(pGOPHalLocal, CKG_GOPG0_SCALING, GOP_BIT2|GOP_BIT3 , GOP_REG_WORD_MASK); in HAL_GOP_Init()
697 …HAL_GOP_Write16Reg(pGOPHalLocal, GOP_AFBCCLK, CKG_AFBCCLK_432, GOP_BIT2|GOP_BIT3); //Clk… in HAL_GOP_Init()
717 …HAL_GOP_Write16Reg(pGOPHalLocal, u32bankoff+GOP_4G_MIU_SEL, u8MIUSel<<2, GOP_BIT2|GOP_BIT3 );//GWI… in HAL_GOP_Init()
1302 HAL_GOP_Write16Reg(pGOPHalLocal, u32BankOffSet+GOP_4G_CTRL1, u16RegVal, BMASK(GOP_BIT3:0)); in HAL_GOP_GWIN_SetDstPlane()
2418 u16RegVal |= GOP_BIT3; //Disable Sub IP blending in HAL_GOP_SetIPSel2SC()
2428 u16RegVal |= GOP_BIT3; //Disable Sub IP blending in HAL_GOP_SetIPSel2SC()
2438 u16RegVal |= GOP_BIT3; //Disable Sub IP blending in HAL_GOP_SetIPSel2SC()
2487 u16RegVal |= GOP_BIT3; //Disable Sub IP blending in HAL_GOP_SetIPSel2SC()
3153 …HAL_GOP_Write16Reg(pGOPHalLocal, u32BankOffSet+GOP_4G_MIU_SEL, miusel<<2, GOP_BIT2|GOP_BIT3 );//GW… in HAL_GOP_Set_GWIN_INTERNAL_MIU()
[all …]
/utopia/UTPA2-700.0.x/modules/graphic/hal/M7821/gop/
H A DregGOP.h227 #define CKG_GOPG0_MASK (GOP_BIT5 | GOP_BIT4 | GOP_BIT3 | GOP_BIT2)
241 #define CKG_GOPG0_MG_MASK (GOP_BIT3 | GOP_BIT2)
254 #define CKG_GOPG2_MASK (GOP_BIT5 |GOP_BIT4 | GOP_BIT3 | GOP_BIT2)
273 #define CKG_GOPG3_MASK (GOP_BIT5 | GOP_BIT4 | GOP_BIT3 | GOP_BIT2)
300 #define CKG_LB_SRAM1_MASK (GOP_BIT2|GOP_BIT3)
308 #define CKG_AFBCCLK_DISABLE_CLK_MASK (GOP_BIT0|GOP_BIT1|GOP_BIT2|GOP_BIT3)
H A DhalGOP.c507 if (u16GopMask&GOP_BIT3) in HAL_GOP_SetGOPACKMask()
739 HAL_GOP_Write16Reg(pGOPHalLocal, CKG_GOPG0_SCALING, GOP_BIT2|GOP_BIT3 , GOP_REG_WORD_MASK); in HAL_GOP_Init()
782 …HAL_GOP_Write16Reg(pGOPHalLocal, GOP_AFBCCLK, CKG_AFBCCLK_432, GOP_BIT2|GOP_BIT3); //Clk… in HAL_GOP_Init()
802 …HAL_GOP_Write16Reg(pGOPHalLocal, u32bankoff+GOP_4G_MIU_SEL, u8MIUSel<<2, GOP_BIT2|GOP_BIT3 );//GWI… in HAL_GOP_Init()
1395 HAL_GOP_Write16Reg(pGOPHalLocal, u32BankOffSet+GOP_4G_CTRL1, u16RegVal, BMASK(GOP_BIT3:0)); in HAL_GOP_GWIN_SetDstPlane()
1401 … HAL_GOP_Write16Reg(pGOPHalLocal, u32SubBnkOffSet+GOP_4G_CTRL1, u16RegVal, BMASK(GOP_BIT3:0)); in HAL_GOP_GWIN_SetDstPlane()
3208 …HAL_GOP_Write16Reg(pGOPHalLocal, u32BankOffSet+GOP_4G_MIU_SEL, miusel<<2, GOP_BIT2|GOP_BIT3 );//GW… in HAL_GOP_Set_GWIN_INTERNAL_MIU()
3227 …e16Reg(pGOPHalLocal, u32BankOffSet+GOP_4G_MIU_SEL, miusel<<2, (GOP_BIT2|GOP_BIT3));//GWIN MIU Sele… in HAL_GOP_Set_MIU()
3308 …GOPHalLocal, u32CombineBankOffSet + GOP_4G_MIU_SEL, miusel<<2, GOP_BIT2|GOP_BIT3 );//GWIN MIU Sele… in HAL_GOP_Set_MIU()
/utopia/UTPA2-700.0.x/modules/graphic/hal/maserati/gop/
H A DregGOP.h227 #define CKG_GOPG0_MASK (GOP_BIT5 | GOP_BIT4 | GOP_BIT3 | GOP_BIT2)
241 #define CKG_GOPG0_MG_MASK (GOP_BIT3 | GOP_BIT2)
254 #define CKG_GOPG2_MASK (GOP_BIT5 |GOP_BIT4 | GOP_BIT3 | GOP_BIT2)
273 #define CKG_GOPG3_MASK (GOP_BIT5 | GOP_BIT4 | GOP_BIT3 | GOP_BIT2)
300 #define CKG_LB_SRAM1_MASK (GOP_BIT2|GOP_BIT3)
308 #define CKG_AFBCCLK_DISABLE_CLK_MASK (GOP_BIT0|GOP_BIT1|GOP_BIT2|GOP_BIT3)
H A DhalGOP.c507 if (u16GopMask&GOP_BIT3) in HAL_GOP_SetGOPACKMask()
739 HAL_GOP_Write16Reg(pGOPHalLocal, CKG_GOPG0_SCALING, GOP_BIT2|GOP_BIT3 , GOP_REG_WORD_MASK); in HAL_GOP_Init()
782 …HAL_GOP_Write16Reg(pGOPHalLocal, GOP_AFBCCLK, CKG_AFBCCLK_432, GOP_BIT2|GOP_BIT3); //Clk… in HAL_GOP_Init()
802 …HAL_GOP_Write16Reg(pGOPHalLocal, u32bankoff+GOP_4G_MIU_SEL, u8MIUSel<<2, GOP_BIT2|GOP_BIT3 );//GWI… in HAL_GOP_Init()
1395 HAL_GOP_Write16Reg(pGOPHalLocal, u32BankOffSet+GOP_4G_CTRL1, u16RegVal, BMASK(GOP_BIT3:0)); in HAL_GOP_GWIN_SetDstPlane()
1401 … HAL_GOP_Write16Reg(pGOPHalLocal, u32SubBnkOffSet+GOP_4G_CTRL1, u16RegVal, BMASK(GOP_BIT3:0)); in HAL_GOP_GWIN_SetDstPlane()
3211 …HAL_GOP_Write16Reg(pGOPHalLocal, u32BankOffSet+GOP_4G_MIU_SEL, miusel<<2, GOP_BIT2|GOP_BIT3 );//GW… in HAL_GOP_Set_GWIN_INTERNAL_MIU()
3230 …e16Reg(pGOPHalLocal, u32BankOffSet+GOP_4G_MIU_SEL, miusel<<2, (GOP_BIT2|GOP_BIT3));//GWIN MIU Sele… in HAL_GOP_Set_MIU()
3311 …GOPHalLocal, u32CombineBankOffSet + GOP_4G_MIU_SEL, miusel<<2, GOP_BIT2|GOP_BIT3 );//GWIN MIU Sele… in HAL_GOP_Set_MIU()
/utopia/UTPA2-700.0.x/modules/graphic/hal/messi/gop/
H A DregGOP.h208 #define CKG_GOPG0_MASK (GOP_BIT4 | GOP_BIT3 | GOP_BIT2)
220 #define CKG_GOPG0_MG_MASK (GOP_BIT3 | GOP_BIT2)
231 #define CKG_GOPG2_MASK (GOP_BIT4 | GOP_BIT3 | GOP_BIT2)
249 #define CKG_GOPG3_MASK (GOP_BIT5 | GOP_BIT4 | GOP_BIT3 | GOP_BIT2)
275 #define CKG_LB_SRAM1_MASK (GOP_BIT2|GOP_BIT3)
/utopia/UTPA2-700.0.x/modules/graphic/hal/mainz/gop/
H A DregGOP.h208 #define CKG_GOPG0_MASK (GOP_BIT4 | GOP_BIT3 | GOP_BIT2)
220 #define CKG_GOPG0_MG_MASK (GOP_BIT3 | GOP_BIT2)
231 #define CKG_GOPG2_MASK (GOP_BIT4 | GOP_BIT3 | GOP_BIT2)
249 #define CKG_GOPG3_MASK (GOP_BIT5 | GOP_BIT4 | GOP_BIT3 | GOP_BIT2)
275 #define CKG_LB_SRAM1_MASK (GOP_BIT2|GOP_BIT3)
/utopia/UTPA2-700.0.x/modules/graphic/hal/mooney/gop/
H A DregGOP.h205 #define CKG_GOPG0_MASK (GOP_BIT5 | GOP_BIT4 | GOP_BIT3 | GOP_BIT2)
218 #define CKG_GOPG0_MG_MASK (GOP_BIT3 | GOP_BIT2)
230 #define CKG_GOPG2_MASK (GOP_BIT5 |GOP_BIT4 | GOP_BIT3 | GOP_BIT2)
247 #define CKG_GOPG3_MASK (GOP_BIT5 | GOP_BIT4 | GOP_BIT3 | GOP_BIT2)
273 #define CKG_LB_SRAM1_MASK (GOP_BIT2|GOP_BIT3)
/utopia/UTPA2-700.0.x/modules/graphic/hal/macan/gop/
H A DregGOP.h216 #define CKG_GOPG0_MASK (GOP_BIT5 | GOP_BIT4 | GOP_BIT3 | GOP_BIT2)
230 #define CKG_GOPG0_MG_MASK (GOP_BIT3 | GOP_BIT2)
243 #define CKG_GOPG2_MASK (GOP_BIT5 |GOP_BIT4 | GOP_BIT3 | GOP_BIT2)
262 #define CKG_GOPG3_MASK (GOP_BIT5 | GOP_BIT4 | GOP_BIT3 | GOP_BIT2)
289 #define CKG_LB_SRAM1_MASK (GOP_BIT2|GOP_BIT3)
/utopia/UTPA2-700.0.x/modules/graphic/hal/manhattan/gop/
H A DregGOP.h218 #define CKG_GOPG0_MASK (GOP_BIT5 | GOP_BIT4 | GOP_BIT3 | GOP_BIT2)
232 #define CKG_GOPG0_MG_MASK (GOP_BIT3 | GOP_BIT2)
245 #define CKG_GOPG2_MASK (GOP_BIT5 |GOP_BIT4 | GOP_BIT3 | GOP_BIT2)
264 #define CKG_GOPG3_MASK (GOP_BIT5 | GOP_BIT4 | GOP_BIT3 | GOP_BIT2)
291 #define CKG_LB_SRAM1_MASK (GOP_BIT2|GOP_BIT3)
/utopia/UTPA2-700.0.x/modules/graphic/hal/mustang/gop/
H A DregGOP.h196 #define CKG_GOPG0_MASK (GOP_BIT4 | GOP_BIT3 | GOP_BIT2)
205 #define CKG_GOPG0_MG_MASK (GOP_BIT3 | GOP_BIT2)
214 #define CKG_GOPG2_MASK (GOP_BIT4 | GOP_BIT3 | GOP_BIT2)
227 #define CKG_GOPG3_MASK (GOP_BIT4 | GOP_BIT3 | GOP_BIT2)
/utopia/UTPA2-700.0.x/modules/graphic/hal/maldives/gop/
H A DregGOP.h193 #define CKG_GOPG0_MASK (GOP_BIT4 | GOP_BIT3 | GOP_BIT2)
202 #define CKG_GOPG0_MG_MASK (GOP_BIT3 | GOP_BIT2)
211 #define CKG_GOPG2_MASK (GOP_BIT4 | GOP_BIT3 | GOP_BIT2)
224 #define CKG_GOPG3_MASK (GOP_BIT4 | GOP_BIT3 | GOP_BIT2)

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