1 //<MStar Software>
2 //******************************************************************************
3 // MStar Software
4 // Copyright (c) 2010 - 2012 MStar Semiconductor, Inc. All rights reserved.
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76 //******************************************************************************
77 //<MStar Software>
78 ////////////////////////////////////////////////////////////////////////////////
79 //
80 // Copyright (c) 2008-2009 MStar Semiconductor, Inc.
81 // All rights reserved.
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92 //
93 ////////////////////////////////////////////////////////////////////////////////
94
95 #include "MsCommon.h"
96 #ifndef MSOS_TYPE_LINUX_KERNEL
97 #include <string.h>
98 #endif
99 #include "MsTypes.h"
100 #include "halGOP.h"
101 #include "regGOP.h"
102 #include "halCHIP.h"
103 #include "drvSYS.h"
104
105 //------------------------------------------------------------------------------
106 // Driver Compiler Options
107 //------------------------------------------------------------------------------
108
109
110 //------------------------------------------------------------------------------
111 // Local Defines
112 //------------------------------------------------------------------------------
113 #define RIU ((unsigned short volatile *) pGOPHalLocal->va_mmio_base)
114 #define GOP_WRITE2BYTE(addr, val) { RIU[addr] = val; }
115 #define GOP_READ2BYTE(addr) RIU[addr]
116 #define GOP_BANK_MASK 0x1FUL
117 #define GOP_DST_MASK 0xFUL
118
119 // Debug Log
120 #include "ULog.h"
121 MS_U32 u32GOPDbgLevel_hal;
122
123 // Debug Logs, level form low(INFO) to high(FATAL, always show)
124 // Function information, ex function entry
125 #define GOP_H_INFO(x, args...) if(u32GOPDbgLevel_hal >= E_GOP_Debug_Level_HIGH) {ULOGI("GOP HAL", x, ##args);}
126 // Warning, illegal paramter but can be self fixed in functions
127 #define GOP_H_WARN(x, args...) if(u32GOPDbgLevel_hal >= E_GOP_Debug_Level_HIGH) {ULOGW("GOP HAL", x, ##args);}
128 // Need debug, illegal paramter.
129 #define GOP_H_DBUG(x, args...) if(u32GOPDbgLevel_hal >= E_GOP_Debug_Level_MED) {ULOGD("GOP HAL", x, ##args);}
130 // Error, function will be terminated but system not crash
131 #define GOP_H_ERR(x, args...) if(u32GOPDbgLevel_hal >= E_GOP_Debug_Level_LOW) {ULOGE("GOP HAL", x, ##args);}
132 // Critical, system crash. (ex. assert)
133 #define GOP_H_FATAL(x, args...) if(u32GOPDbgLevel_hal >= E_GOP_Debug_Level_LOW){ULOGF("GOP HAL", x, ##args);}
134
135 #define GOP_ASSERT(_bool_){\
136 if ( ! ( _bool_ ) )\
137 {\
138 GOP_H_FATAL("\033[35m UTOPIA ASSERT: %s, %s %s %d\033[35m\n", #_bool_, __FILE__, __PRETTY_FUNCTION__, __LINE__);\
139 }\
140 }
141
142 //------------------------------------------------------------------------------
143 // Local Var
144 //------------------------------------------------------------------------------
145 MS_BOOL bIsMuxVaildToGopDst[MAX_GOP_MUX][MAX_DRV_GOP_DST_SUPPORT] =
146 {
147 /*IP0, IP0_SUB, MIXER2VE, OP0, VOP, IP1, IP1_SUB, MIXER2OP*/
148 {TRUE, FALSE, FALSE, TRUE, TRUE, FALSE, FALSE, FALSE}, /*All Gop Dst case is vaild or FALSE for mux 0 */
149 {TRUE, FALSE, FALSE, FALSE, TRUE, FALSE, FALSE, FALSE}, /*All Gop Dst case is vaild or FALSE for mux 1 */
150 {TRUE, FALSE, FALSE, TRUE, TRUE, FALSE, FALSE, FALSE}, /*All Gop Dst case is vaild or FALSE for mux 0 */
151 {TRUE, FALSE, FALSE, TRUE, TRUE, FALSE, FALSE, FALSE}, /*All Gop Dst case is vaild or FALSE for mux 0 */
152 };
153 #ifdef GOP_CMDQ_ENABLE
154 extern MS_U16 u16MIUSelect[MAX_GOP_SUPPORT];
155 extern MS_BOOL bMIUSelect[MAX_GOP_SUPPORT];
156
157 extern MS_U16 u16AFBCMIUSelect[MAX_GOP_SUPPORT];
158 extern MS_BOOL bAFBCMIUSelect[MAX_GOP_SUPPORT];
159 #endif
160 GOP_CHIP_PROPERTY g_GopChipPro =
161 {
162 .bSetHSyncInverse = FALSE,
163 .bGop1GPalette = FALSE,
164 .bSetHPipeOfst = FALSE,
165 .bNeedCheckMVOP = FALSE,
166 .bNeedSetMUX1ToIP0 = FALSE,
167 .bNeedSetMUX3ToIP0 = FALSE,
168 .bNewMux = TRUE,
169 .bNewPalette = TRUE,
170 .bNewBwReg = TRUE,
171 .bGop2VStretch = TRUE,
172 .bIgnoreIPHPD = TRUE, //Uranus4 has handshack with XC, should not set HPD
173 .bIgnoreVEHPD = FALSE, //Uranus4 to VE through Mixer, do not need adjust HPD
174 .bhastilemode = TRUE,
175 .bInitNotEnableGOPToSC = FALSE, //For Uranus4 mux init setting, enable GOP to SC in GOP init would cause problem
176 .bAutoAdjustMirrorHSize = TRUE, //whether hw will auto adjust start addr when H mirror is enable
177 .bGOPWithVscale = {TRUE, TRUE, TRUE, TRUE, FALSE}, //setting GOP with/without Vscale
178 .bGOPWithScaleDown = {TRUE, FALSE, TRUE, FALSE, FALSE},
179
180 .bDWINSupport = FALSE,
181 .DwinVer = 0x1,
182 .bTstPatternAlpha = TRUE,
183 .bXCDirrectBankSupport = TRUE, /*XC Dirrect Bank R/W*/
184 .bFRCSupport = FALSE, /*OC path*/
185 .bGOPMixerToVE= FALSE, /*Mixer to VE path*/
186 .bBnkForceWrite = TRUE, /*Direct Bank Force Write*/
187 .bPixelModeSupport = TRUE, /*Pixel Mode Support*/
188 .bScalingDownSupport= TRUE,
189 .b2Pto1PSupport= TRUE,
190 .bTLBSupport= {TRUE, TRUE, TRUE, TRUE, FALSE, FALSE},
191 .GOP_TestPattern_Vaild= E_GOP0,
192 .bInternalMIUSelect= {TRUE, FALSE, TRUE, TRUE, FALSE, FALSE, FALSE, FALSE}, //{E_GOP0, E_GOP1, E_GOP2, E_GOP3, E_GOP4, E_GOP_Dwin, E_GOP_MIXER, E_GOP5}
193 .bAFBC_Support= {FALSE, FALSE, FALSE, FALSE, FALSE, FALSE},
194
195 #ifdef ENABLE_GOP_T3DPATCH
196 .GOP_PD = GOP_PD_T3D,
197 #else
198 .GOP_PD = 0x159,
199 #endif
200
201 .GOP_HDR_OP_PD = 0x0,
202 .GOP_IP_PD = 0x00,
203 .GOP_MVOP_PD = 0x69,
204 .GOP_VE_PD = 0x89,
205 .GOP_MIXER_PD = 0x0,
206 .GOP_NonVS_PD_Offset = 0x5, //GOP without Vsacle might need add offset on pipedelay
207 .GOP_NonVS_DualOpPD_Offset= 0x6,
208 .GOP_VE_V_Offset = 0x0,
209 .GOP_DUAL_OP_PD = 0x63,
210
211 .GOP_MUX_Delta = 0x1,
212 .GOP_Mux_Offset = {0x0, 0x36, 0x3C, 0x42, 0x48},
213 .GOP_MapLayer2Mux = {E_GOP_MUX0, E_GOP_MUX1, E_GOP_MUX2, E_GOP_MUX3, E_GOP_MUX4},
214 .GOP_MapLayer2DualOpMux = {E_GOP_DUALRATE_OP_MUX0, E_GOP_DUALRATE_OP_MUX1, E_GOP_DUALRATE_OP_MUX2},
215 .GOP_Mux_FRC_offset= 0x13,
216 .GOP_DualRateMux_Offset = {0x0, 0x6, 0xC},
217 .GOP_REF_POSITION_X = 0x418,
218
219 .WordUnit = GOP_WordUnit,
220 .TotalGwinNum = GOP_TotalGwinNum,
221 .Default_ConsAlpha_bits = DRV_VALID_8BITS,
222 .enGOP3DType = E_DRV_3D_DUP_FULL,
223 .bOpInterlace = FALSE,
224 .bAFBCMIUSelDoubleBuffer = TRUE,
225 .bAFBC_Merge_GOP_Trig = TRUE,
226 .bGOPVscalePipeDelay = {FALSE, FALSE, FALSE, FALSE, TRUE, FALSE},
227 .bGOPNeedSplitMode4DualRate = {FALSE, FALSE, FALSE, FALSE, TRUE},
228 .bGOPAutoClkGating = TRUE,
229 };
230
231 typedef struct
232 {
233 MS_U8 u8Gop;
234 MS_U8 mainGop;
235 MS_U8 subGop;
236 } GOP_4K120_COMBINE_PAIRS;
237
238 static const GOP_4K120_COMBINE_PAIRS gop_4k120_pairs[] =
239 {
240 {E_GOP0, E_GOP0, E_GOP3},
241 {E_GOP1, E_GOP2, E_GOP1},
242 {E_GOP2, E_GOP2, E_GOP1},
243 {E_GOP3, E_GOP0, E_GOP3},
244 {E_GOP4, E_GOP4, E_GOP4},
245 };
246
247 const MS_U8 GOP_4K120MUX_IDX_TABLE[GOP_4K120_MUX_COUNT] = {E_GOP0, E_GOP2, E_GOP4};
248
249 static const int GOP4_SPLITMODE_MAX_HSIZE = 256;
250 static const int GOP4_SPLITMODE_MAX_VSIZE = 512;
251
252 static MS_BOOL Hal_get4K120CombinedGOP(GOP_CTX_HAL_LOCAL *pGOPHalLocal, MS_U8 u8GOP, MS_U8 * main_gop, MS_U8 * sub_gop);
253 static GOP_Result Hal_Ctrl4K120GopMode(GOP_CTX_HAL_LOCAL *pGOPHalLocal, MS_U8 u8GOP, MS_BOOL bEnable);
254 static MS_U16 _findMuxNumberByGOP(GOP_CTX_HAL_LOCAL *pGOPHalLocal, DRV_GOPDstType dst_type, MS_U8 u8Gop);
255
256 //------------------------------------------------------------------------------
257 // Global Functions
258 //------------------------------------------------------------------------------
HAL_GOP_GetGOPEnum(GOP_CTX_HAL_LOCAL * pGOPHalLocal,GOP_TYPE_DEF * GOP_TYPE)259 void HAL_GOP_GetGOPEnum(GOP_CTX_HAL_LOCAL *pGOPHalLocal, GOP_TYPE_DEF* GOP_TYPE)
260 {
261 GOP_TYPE->GOP0 = E_GOP0;
262 GOP_TYPE->GOP1 = E_GOP1;
263 GOP_TYPE->GOP2 = E_GOP2;
264 GOP_TYPE->GOP3 = E_GOP3;
265 GOP_TYPE->GOP4 = E_GOP4;
266 GOP_TYPE->GOP5 = E_GOP5;
267 GOP_TYPE->DWIN = E_GOP_Dwin;
268 GOP_TYPE->MIXER = E_GOP_MIXER;
269 }
270
HAL_GOP_SetWinFmt(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_U8 regForm,MS_U8 u8GOPNum,MS_U8 u8GwinNum,MS_U16 colortype)271 GOP_Result HAL_GOP_SetWinFmt(GOP_CTX_HAL_LOCAL *pGOPHalLocal, MS_U8 regForm, MS_U8 u8GOPNum, MS_U8 u8GwinNum, MS_U16 colortype)
272 {
273 MS_U32 u32BankOffSet = 0;
274
275 _GetBnkOfstByGop(u8GOPNum, &u32BankOffSet);
276
277 if (((regForm & E_GOP_REG_FORM_MASK) == E_GOP_REG_FORM_T21G) || ((regForm & E_GOP_REG_FORM_MASK) == E_GOP_REG_FORM_T81G))
278 {
279 HAL_GOP_Write16Reg(pGOPHalLocal, u32BankOffSet + GOP_4G_GWIN0_CTRL(Gop23_GwinCtl_Ofet), colortype, GOP_REG_COLORTYPE_MASK<<GOP_REG_COLORTYPE_SHIFT);
280 }
281 else
282 {
283 HAL_GOP_Write16Reg(pGOPHalLocal, u32BankOffSet + GOP_4G_GWIN0_CTRL(u8GwinNum), colortype, GOP_REG_COLORTYPE_MASK<<GOP_REG_COLORTYPE_SHIFT);
284 }
285
286 return GOP_SUCCESS;
287 }
288
HAL_GOP_Set_PINPON(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_U8 u8GOPNum,MS_BOOL bEn,E_DRV_GOP_PINPON_MODE pinpon_mode)289 GOP_Result HAL_GOP_Set_PINPON(GOP_CTX_HAL_LOCAL *pGOPHalLocal, MS_U8 u8GOPNum, MS_BOOL bEn, E_DRV_GOP_PINPON_MODE pinpon_mode)
290 {
291 MS_U32 u32BankOffSet =0;
292 MS_U32 u32BitMask,Regval;
293
294 _GetBnkOfstByGop(u8GOPNum, &u32BankOffSet);
295
296 switch(pinpon_mode)
297 {
298 default:
299 case E_DRV_GOP_PINPON_G3D:
300 Regval = bEn << 5;
301 u32BitMask = GOP_BIT5;
302 break;
303 case E_DRV_GOP_PINPON_DWIN:
304 Regval = bEn << 6;
305 u32BitMask = GOP_BIT6;
306 break;
307 case E_DRV_GOP_PINPON_DIP:
308 Regval = bEn << 7;
309 u32BitMask = GOP_BIT7;
310 HAL_GOP_Write16Reg(pGOPHalLocal, u32BankOffSet+GOP_4G_MULTI_ALPHA, GOP_BIT9,(GOP_BIT8|GOP_BIT9));
311 break;
312 case E_DRV_GOP_PINPON_DWIN0:
313 Regval = bEn << 7;
314 u32BitMask = GOP_BIT7;
315 HAL_GOP_Write16Reg(pGOPHalLocal, u32BankOffSet+GOP_4G_MULTI_ALPHA, 0x0,(GOP_BIT8|GOP_BIT9));
316 break;
317 case E_DRV_GOP_PINPON_DWIN1:
318 Regval = bEn << 7;
319 u32BitMask = GOP_BIT7;
320 HAL_GOP_Write16Reg(pGOPHalLocal, u32BankOffSet+GOP_4G_MULTI_ALPHA, GOP_BIT8,(GOP_BIT8|GOP_BIT9));
321 break;
322 break;
323 }
324
325 HAL_GOP_Write16Reg(pGOPHalLocal, u32BankOffSet+GOP_4G_CTRL1, Regval, u32BitMask);
326 MS_U8 u8_mainGop = INVAILD_GOP_NUM, u8_combinedGop = INVAILD_GOP_NUM;
327 MS_U32 u32CombineBankOffSet = 0x0;
328
329 if( FALSE == Hal_get4K120CombinedGOP(pGOPHalLocal, u8GOPNum, &u8_mainGop, &u8_combinedGop) )
330 {
331 GOP_H_ERR("Skipped [%s] Line %d !!", __FUNCTION__, __LINE__);
332 return GOP_FAIL;
333 }
334 if (pGOPHalLocal->pHALShared->GOP_Dst[u8_mainGop] == E_DRV_GOP_DST_OP_DUAL_RATE)
335 {
336 _GetBnkOfstByGop(u8_combinedGop, &u32CombineBankOffSet);
337 HAL_GOP_Write16Reg(pGOPHalLocal, u32CombineBankOffSet+GOP_4G_CTRL1, 0x4100, GOP_REG_HW_MASK);
338 }
339
340 return GOP_SUCCESS;
341 }
342
343
_GetBnkOfstByGop(MS_U8 gop,MS_U32 * pBnkOfst)344 MS_BOOL _GetBnkOfstByGop(MS_U8 gop, MS_U32 *pBnkOfst)
345 {
346 if (gop==E_GOP0)
347 *pBnkOfst = GOP_4G_OFST<<16;
348 else if (gop==E_GOP1)
349 *pBnkOfst = GOP_2G_OFST<<16;
350 else if (gop==E_GOP2)
351 *pBnkOfst = GOP_1G_OFST<<16;
352 else if (gop==E_GOP3)
353 *pBnkOfst = GOP_1GX_OFST<<16;
354 else if (gop==E_GOP4)
355 *pBnkOfst = GOP_1GS0_OFST<<16;
356 else if (gop==E_GOP_MIXER)
357 *pBnkOfst = 0xD<<16;
358 else
359 return FALSE;
360
361 return TRUE;
362 }
363
_dumpGopNumFromBnkOffset(MS_U8 * gop,MS_U16 * subBnkOfst,MS_U32 pBnkOfst)364 MS_BOOL _dumpGopNumFromBnkOffset(MS_U8 * gop, MS_U16 * subBnkOfst, MS_U32 pBnkOfst)
365 {
366 MS_U32 subbnk = 0x0;
367 pBnkOfst = pBnkOfst >> 8;
368
369 if ((pBnkOfst >= GOP_4G_OFST) && (pBnkOfst < GOP_2G_OFST))
370 {
371 *gop = E_GOP0;
372 subbnk = pBnkOfst - GOP_4G_OFST;
373 }
374 else if ((pBnkOfst >= GOP_2G_OFST) && (pBnkOfst < GOP_1G_OFST))
375 {
376 *gop = E_GOP1;
377 subbnk = pBnkOfst - GOP_2G_OFST;
378 }
379 else if ((pBnkOfst >= GOP_1G_OFST) && (pBnkOfst < GOP_1GX_OFST))
380 {
381 *gop = E_GOP2;
382 subbnk = pBnkOfst - GOP_1G_OFST;
383 }
384 else if ((pBnkOfst >= GOP_1GX_OFST) && (pBnkOfst < GOP_1GS0_OFST))
385 {
386 *gop = E_GOP3;
387 subbnk = pBnkOfst - GOP_1GX_OFST;
388 }
389 else if ((pBnkOfst >= GOP_1GS0_OFST) || (pBnkOfst < GOP_1GS1_OFST))
390 {
391 *gop = E_GOP4;
392 subbnk = pBnkOfst - GOP_1GS0_OFST;
393 }
394 else
395 {
396 return FALSE;
397 }
398
399 *subBnkOfst = (MS_U16)(subbnk << 8);
400 return TRUE;
401 }
402
_isGopCommonRegs(MS_U16 reg)403 static MS_BOOL _isGopCommonRegs(MS_U16 reg)
404 {
405 MS_BOOL ret;
406
407 if ((reg >= (GOP_MUX_IPVOP & 0xFF)) && (reg <= (GOP_BAK_SEL & 0xFF)))
408 {
409 ret = TRUE;
410 }
411 else
412 {
413 ret = FALSE;
414 }
415
416 return ret;
417 }
418
HAL_GOP_SetGOPACKMask(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_U16 u16GopMask)419 GOP_Result HAL_GOP_SetGOPACKMask(GOP_CTX_HAL_LOCAL *pGOPHalLocal,MS_U16 u16GopMask)
420 {
421 MS_U16 u16Mask0 = 0;
422 MS_U16 u16Mask1 = 0;
423 if (u16GopMask&GOP_BIT0)
424 {
425 u16Mask0 |= GOP_BIT12;
426 }
427 if (u16GopMask&GOP_BIT1)
428 {
429 u16Mask0 |= GOP_BIT13;
430 }
431 if (u16GopMask&GOP_BIT2)
432 {
433 u16Mask0 |= GOP_BIT14;
434 }
435 if (u16GopMask&GOP_BIT3)
436 {
437 u16Mask0 |= GOP_BIT15;
438 }
439 if (u16GopMask&GOP_BIT4)
440 {
441 u16Mask1 |= GOP_BIT4;
442 }
443
444 if (u16Mask0 & (GOP_BIT12 | GOP_BIT15))
445 {
446 if (pGOPHalLocal->pHALShared->GOP_Dst[(MS_U8)E_GOP0] == E_DRV_GOP_DST_OP_DUAL_RATE)
447 {
448 u16Mask0 |= (GOP_BIT12 | GOP_BIT15);
449 }
450 }
451 if (u16Mask0 & (GOP_BIT13 | GOP_BIT14))
452 {
453 if (pGOPHalLocal->pHALShared->GOP_Dst[(MS_U8)E_GOP2] == E_DRV_GOP_DST_OP_DUAL_RATE)
454 {
455 u16Mask0 |= (GOP_BIT13 | GOP_BIT14);
456 }
457 }
458
459 if (u16Mask0 != 0)
460 {
461 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_BAK_SEL, 0xFFFF , u16Mask0);
462 }
463 if (u16Mask1 != 0)
464 {
465 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_BAK_SEL_EX, 0xFFFF , u16Mask1);
466 }
467
468 if(g_GopChipPro.bAFBC_Merge_GOP_Trig ==FALSE)
469 {
470 HAL_GOP_Write16Reg(pGOPHalLocal, REG_AFBC_TRIGGER, GOP_BIT1, GOP_BIT1);
471 }
472 return GOP_SUCCESS;
473 }
474
HAL_GOP_SetGOPACK(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_U8 gop)475 GOP_Result HAL_GOP_SetGOPACK(GOP_CTX_HAL_LOCAL *pGOPHalLocal,MS_U8 gop)
476 {
477 MS_U8 u8_mainGop = INVAILD_GOP_NUM, u8_combinedGop = INVAILD_GOP_NUM;
478 if( FALSE == Hal_get4K120CombinedGOP(pGOPHalLocal, gop, &u8_mainGop, &u8_combinedGop) )
479 {
480 GOP_H_ERR("Skipped [%s] Line %d !!", __FUNCTION__, __LINE__);
481 return GOP_FAIL;
482 }
483
484 if (pGOPHalLocal->pHALShared->GOP_Dst[u8_mainGop] == E_DRV_GOP_DST_OP_DUAL_RATE)
485 {
486 switch (u8_mainGop)
487 {
488 case E_GOP0:
489 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_BAK_SEL, (GOP_BIT12 | GOP_BIT15), (GOP_BIT12 | GOP_BIT15));
490 break;
491 case E_GOP2:
492 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_BAK_SEL, (GOP_BIT13 | GOP_BIT14), (GOP_BIT13 | GOP_BIT14));
493 break;
494 case E_GOP4:
495 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_BAK_SEL_EX, GOP_BIT4 , GOP_BIT4);
496 break;
497 default:
498 break;
499 }
500 }
501 else
502 {
503 switch(gop)
504 {
505 case E_GOP0:
506 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_BAK_SEL, GOP_BIT12 , GOP_BIT12);
507 break;
508 case E_GOP1:
509 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_BAK_SEL, GOP_BIT13 , GOP_BIT13);
510 break;
511 case E_GOP2:
512 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_BAK_SEL, GOP_BIT14 , GOP_BIT14);
513 break;
514 case E_GOP3:
515 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_BAK_SEL, GOP_BIT15 , GOP_BIT15);
516 break;
517 case E_GOP4:
518 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_BAK_SEL_EX, GOP_BIT4 , GOP_BIT4);
519 break;
520 default:
521 break;
522 }
523 }
524
525 if(g_GopChipPro.bAFBC_Merge_GOP_Trig ==FALSE)
526 {
527 HAL_GOP_Write16Reg(pGOPHalLocal, REG_AFBC_TRIGGER, GOP_BIT0, GOP_BIT0);
528 HAL_GOP_Write16Reg(pGOPHalLocal, REG_AFBC_TRIGGER, GOP_BIT1, GOP_BIT1);
529 }
530 return GOP_SUCCESS;
531 }
532
HAL_GOP_GetGOPACK(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_U8 gop)533 MS_U16 HAL_GOP_GetGOPACK(GOP_CTX_HAL_LOCAL *pGOPHalLocal,MS_U8 gop)
534 {
535 MS_U16 u16GopAck = FALSE, reg_val =0;
536 MS_U8 u8_mainGop = INVAILD_GOP_NUM, u8_combinedGop = INVAILD_GOP_NUM;
537
538 if( FALSE == Hal_get4K120CombinedGOP(pGOPHalLocal, gop, &u8_mainGop, &u8_combinedGop) )
539 {
540 GOP_H_ERR("Skipped [%s] Line %d !!", __FUNCTION__, __LINE__);
541 return u16GopAck;
542 }
543
544 if (pGOPHalLocal->pHALShared->GOP_Dst[u8_mainGop] == E_DRV_GOP_DST_OP_DUAL_RATE)
545 {
546 switch (u8_mainGop)
547 {
548 case E_GOP0:
549 HAL_GOP_Read16Reg(pGOPHalLocal,GOP_BAK_SEL,®_val);
550 if ((reg_val&GOP_BIT12) || (reg_val&GOP_BIT15))
551 u16GopAck = FALSE;
552 else
553 u16GopAck = TRUE;
554 break;
555 case E_GOP2:
556 HAL_GOP_Read16Reg(pGOPHalLocal,GOP_BAK_SEL,®_val);
557 if ((reg_val&GOP_BIT13) || (reg_val&GOP_BIT14))
558 u16GopAck = FALSE;
559 else
560 u16GopAck = TRUE;
561 break;
562 case E_GOP4:
563 HAL_GOP_Read16Reg(pGOPHalLocal,GOP_BAK_SEL_EX,®_val);
564 if(reg_val&GOP_BIT4)
565 u16GopAck = FALSE;
566 else
567 u16GopAck = TRUE;
568 break;
569 default:
570 break;
571 }
572 }
573 else
574 {
575 switch(gop)
576 {
577 case E_GOP0:
578 HAL_GOP_Read16Reg(pGOPHalLocal,GOP_BAK_SEL,®_val);
579 if(reg_val&GOP_BIT12)
580 u16GopAck = FALSE;
581 else
582 u16GopAck = TRUE;
583 break;
584 case E_GOP1:
585 HAL_GOP_Read16Reg(pGOPHalLocal,GOP_BAK_SEL,®_val);
586 if(reg_val&GOP_BIT13)
587 u16GopAck = FALSE;
588 else
589 u16GopAck = TRUE;
590 break;
591 case E_GOP2:
592 HAL_GOP_Read16Reg(pGOPHalLocal,GOP_BAK_SEL,®_val);
593 if(reg_val&GOP_BIT14)
594 u16GopAck = FALSE;
595 else
596 u16GopAck = TRUE;
597 break;
598 case E_GOP3:
599 HAL_GOP_Read16Reg(pGOPHalLocal,GOP_BAK_SEL,®_val);
600 if(reg_val&GOP_BIT15)
601 u16GopAck = FALSE;
602 else
603 u16GopAck = TRUE;
604 break;
605 case E_GOP4:
606 HAL_GOP_Read16Reg(pGOPHalLocal,GOP_BAK_SEL_EX,®_val);
607 if(reg_val&GOP_BIT4)
608 u16GopAck = FALSE;
609 else
610 u16GopAck = TRUE;
611 break;
612 default:
613 break;
614 }
615 }
616 return u16GopAck;
617 }
618
HAL_GOP_EnableTwoLineBufferMode(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_U8 u8GOP,MS_BOOL bEnable)619 GOP_Result HAL_GOP_EnableTwoLineBufferMode(GOP_CTX_HAL_LOCAL *pGOPHalLocal, MS_U8 u8GOP, MS_BOOL bEnable)
620 {
621 MS_U32 u32BankOffSet;
622
623 if (u8GOP < 3) /* only GOP0~GOP2 can support two linebuufer mode */
624 {
625 _GetBnkOfstByGop(u8GOP, &u32BankOffSet);
626 HAL_GOP_Write16Reg(pGOPHalLocal, u32BankOffSet+GOP_4G_TWO_LINEBUFFER, bEnable?GOP_BIT12:0, GOP_BIT12);
627 }
628
629 return GOP_SUCCESS;
630 }
631
HAL_GOP_Init(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_U8 u8GOPNum)632 void HAL_GOP_Init(GOP_CTX_HAL_LOCAL *pGOPHalLocal, MS_U8 u8GOPNum)
633 {
634 MS_U32 u32bankoff = 0;
635 MS_U16 mask_shift=0xFF;
636 MS_U16 u16RegVal=0xFF;
637 MS_U8 u8MIUSel=0xF;
638 MS_U8 u8Core=0;
639
640 _GetBnkOfstByGop(u8GOPNum, &u32bankoff);
641 HAL_GOP_Write16Reg(pGOPHalLocal, u32bankoff+GOP_4G_CTRL0, 0x000, GOP_BIT9); // Genshot fast=0 for t3, for T4 and after no need to set this bit.
642
643 HAL_GOP_Write16Reg(pGOPHalLocal, u32bankoff+GOP_4G_BW, 0xDFD0, GOP_REG_WORD_MASK); //set GOP DMA Burst length to "32", set DMA FIFO threhold to "0xD0"
644
645 HAL_GOP_Write16Reg(pGOPHalLocal, u32bankoff+GOP_4G_NEW_BW, GOP_BIT14, GOP_BIT14);
646 HAL_GOP_Write16Reg(pGOPHalLocal, u32bankoff+GOP_4G_NEW_BW, GOP_BIT12, GOP_BIT13|GOP_BIT12);
647
648 HAL_GOP_Write16Reg(pGOPHalLocal, u32bankoff+GOP_4G_HW_USAGE, 0, GOP_BIT0);
649
650 if((u8GOPNum == 0)||(u8GOPNum == 1)||(u8GOPNum == 2))
651 {
652 HAL_GOP_Write16Reg(pGOPHalLocal, u32bankoff+GOP_4G_TWO_LINEBUFFER, GOP_BIT12, GOP_BIT12);
653
654 HAL_GOP_Write16Reg(pGOPHalLocal, CKG_GOPG0_SCALING, GOP_BIT2|GOP_BIT3 , GOP_REG_WORD_MASK);
655 HAL_GOP_Write16Reg(pGOPHalLocal, CKG_GOPG0_MG, 0, GOP_BIT2);
656 // HAL_GOP_Write16Reg(pGOPHalLocal, GOP_SC_GOPSC_SRAM_CTRL, GOP_BIT8|GOP_BIT10|GOP_BIT12, (GOP_BIT8|GOP_BIT9)|(GOP_BIT10|GOP_BIT11)|(GOP_BIT12|GOP_BIT13));
657 }
658
659 /* enable GOP clock */
660 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_SRAMCLK, 0, CKG_SRAM1_DISABLE_CLK|CKG_SRAM0_DISABLE_CLK); /* GOP palette SRAM0&1 */
661 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_LB_SRAMCLK, 0, BMASK(7:0)); /* GOP Line buffer sram clock */
662
663 switch(u8GOPNum)
664 {
665 case E_GOP0:
666 mask_shift = GOP_MIU_CLIENT_GOP0;
667 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_GOPCLK, 0, CKG_GOPG0_DISABLE_CLK_MASK); /* GOP 0 */
668 break;
669 case E_GOP1:
670 mask_shift = GOP_MIU_CLIENT_GOP1;
671 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_GOPCLK, 0, CKG_GOPG1_DISABLE_CLK_MASK); /* GOP 1 */
672 break;
673 case E_GOP2:
674 mask_shift = GOP_MIU_CLIENT_GOP2;
675 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_GOP2CLK, 0, CKG_GOPG2_DISABLE_CLK_MASK); /* GOP 2 */
676 break;
677 case E_GOP3:
678 mask_shift = GOP_MIU_CLIENT_GOP3;
679 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_GOP3CLK, 0, CKG_GOPG3_DISABLE_CLK_MASK); /* GOP 3 */
680 break;
681 case E_GOP4:
682 mask_shift = GOP_MIU_CLIENT_GOP4;
683 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_GOP4CLK, 0, CKG_GOPG4_DISABLE_CLK_MASK); /* GOP 4 */
684 break;
685 case E_GOP_Dwin:
686 mask_shift = GOP_MIU_CLIENT_DWIN;
687 break;
688 default:
689 mask_shift = 0xFF;
690 break;
691 }
692 if(g_GopChipPro.bAFBC_Support[u8GOPNum] ==TRUE)
693 {
694 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_AFBCCLK, 0, CKG_AFBCCLK_DISABLE_CLK_MASK);
695 HAL_GOP_Write16Reg(pGOPHalLocal, REG_AFBC_FMT(0), GOP_BIT5 , GOP_BIT5); //Half block
696 HAL_GOP_Write16Reg(pGOPHalLocal, REG_AFBC_FMT(1), GOP_BIT5 , GOP_BIT5); //Half block
697 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_AFBCCLK, CKG_AFBCCLK_432, GOP_BIT2|GOP_BIT3); //Clk(Without resoluton)
698 HAL_GOP_Write16Reg(pGOPHalLocal, REG_AFBC_TRIGGER, GOP_BIT0, GOP_BIT0); //Double buffer
699 HAL_GOP_Write16Reg(pGOPHalLocal, REG_AFBC_CORE_EN(0), 0, GOP_BIT4); //quick_preload_0
700 HAL_GOP_Write16Reg(pGOPHalLocal, REG_AFBC_CORE_EN(1), 0, GOP_BIT4); //quick_preload_1
701 }
702
703
704 if(pGOPHalLocal->pGopChipPro->bInternalMIUSelect[u8GOPNum] ==TRUE)
705 {
706 HAL_GOP_Read16Reg(pGOPHalLocal, GOP_MIU_GROUP1, &u16RegVal);
707 u8MIUSel = (u16RegVal>>mask_shift)&0x0000001UL;
708 #ifdef GOP_MIU_GROUP2
709 HAL_GOP_Read16Reg(pGOPHalLocal, GOP_MIU_GROUP2, &u16RegVal);
710 u8MIUSel = u8MIUSel|(((u16RegVal>>mask_shift)&0x0000001UL)<<1);
711 #endif
712
713 // Maserati Bug, AFBC disable need set bit15 = 1
714 HAL_GOP_Write16Reg(pGOPHalLocal, u32bankoff+GOP_MUX4_4K120, GOP_BIT7, GOP_BIT7 );
715
716 HAL_GOP_Write16Reg(pGOPHalLocal, u32bankoff+GOP_4G_MIU_SEL, u8MIUSel<<0, GOP_BIT0|GOP_BIT1 );//GWIN Palette MIU Select
717 HAL_GOP_Write16Reg(pGOPHalLocal, u32bankoff+GOP_4G_MIU_SEL, u8MIUSel<<2, GOP_BIT2|GOP_BIT3 );//GWIN MIU Select
718 HAL_GOP_Write16Reg(pGOPHalLocal, u32bankoff+GOP_4G_MIU_SEL, u8MIUSel<<4, GOP_BIT4|GOP_BIT5 );//GWIN_3D MIU Select
719 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_SC_MIU_IP_SEL, 1<<mask_shift, 1<<mask_shift );//Get Control MIU select by GOP itself
720 if(g_GopChipPro.bAFBC_Support[u8GOPNum]==TRUE)
721 {
722 HAL_GOP_AFBC_GetCore(pGOPHalLocal, u8GOPNum, &u8Core);
723 HAL_GOP_Write16Reg(pGOPHalLocal, REG_AFBC_MIU, u8MIUSel<<4 , GOP_BIT4|GOP_BIT5);
724 }
725 }
726
727 //OC_RM_alpha
728 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_SC_OCALPHA, GOP_BIT0, GOP_BIT0);
729 //THEALE/utopia_release/UTPA2-205.0.x_Muji/mxlib/hal/muji/gop/
730 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_MUX_4K2K, 0x7<< GOP_DIP_MUX_SHIFT, GOP_DIP_MUX_MASK);
731
732 // set VIP/VOP timing select, always select VOP should be OK.
733 HAL_GOP_Write16Reg(pGOPHalLocal, u32bankoff+GOP_4G_VIP_VOP_TIMING_SEL, GOP_BIT10, GOP_BIT10);
734
735 // Set Gwin priority,prio0 : Gwin0; prio1:Gwin1, so set GOP_BIT4
736 if(u8GOPNum == E_GOP0 || u8GOPNum == E_GOP1)
737 {
738 HAL_GOP_Write16Reg(pGOPHalLocal, u32bankoff + GOP_4G_PRI0, GOP_BIT4, (GOP_BIT0 | GOP_BIT1 | GOP_BIT4 | GOP_BIT5 ));
739 }
740
741 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_SC_GOP_HSYNC_START, g_GopChipPro.GOP_REF_POSITION_X, 0x1FFF);
742
743 // Enable OP Mux double buff
744 //HAL_GOP_Write16Reg(pGOPHalLocal, GOP_4G_OP_MUX_DBF, GOP_BIT15 , GOP_BIT15); //mark, wait gflip fixed
745 }
746
HAL_GOP_Chip_Proprity_Init(GOP_CTX_HAL_LOCAL * pGOPHalLocal)747 void HAL_GOP_Chip_Proprity_Init(GOP_CTX_HAL_LOCAL *pGOPHalLocal)
748 {
749 pGOPHalLocal->pGopChipPro = &g_GopChipPro;
750 }
751
HAL_GOP_GetMaxGwinNumByGOP(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_U8 u8GopNum)752 MS_U8 HAL_GOP_GetMaxGwinNumByGOP(GOP_CTX_HAL_LOCAL *pGOPHalLocal, MS_U8 u8GopNum)
753 {
754 switch(u8GopNum)
755 {
756 case E_GOP0:
757 return (MS_U8)MAX_GOP0_GWIN;
758 break;
759 case E_GOP1:
760 return (MS_U8)MAX_GOP1_GWIN;
761 break;
762 case E_GOP2:
763 return (MS_U8)MAX_GOP2_GWIN;
764 break;
765 case E_GOP3:
766 return (MS_U8)MAX_GOP3_GWIN;
767 break;
768 case E_GOP4:
769 return (MS_U8)MAX_GOP4_GWIN;
770 break;
771 default:
772 GOP_ASSERT(0);
773 return 0xFF;
774 break;
775 }
776 }
777
HAL_GOP_SelGwinIdByGOP(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_U8 u8Gop,MS_U8 u8Idx)778 MS_U8 HAL_GOP_SelGwinIdByGOP(GOP_CTX_HAL_LOCAL *pGOPHalLocal, MS_U8 u8Gop, MS_U8 u8Idx)
779 {
780 MS_U8 u8GWinId = 0;
781
782 //Adjust GWIN ID by different Chip
783
784 switch(u8Gop)
785 {
786 case E_GOP0:
787 u8GWinId = GOP0_GwinIdBase + u8Idx;
788 break;
789 case E_GOP1:
790 u8GWinId = GOP1_GwinIdBase + u8Idx;
791 break;
792 case E_GOP2:
793 u8GWinId = GOP2_GwinIdBase + u8Idx;
794 break;
795 case E_GOP3:
796 u8GWinId = GOP3_GwinIdBase + u8Idx;
797 break;
798 case E_GOP4:
799 u8GWinId = GOP4_GwinIdBase + u8Idx;
800 break;
801 default:
802 break;
803 }
804 return u8GWinId;
805
806 }
807
HAL_GOP_GOPSel(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_U8 u8GOPNum)808 GOP_Result HAL_GOP_GOPSel(GOP_CTX_HAL_LOCAL *pGOPHalLocal, MS_U8 u8GOPNum)
809 {
810 switch(u8GOPNum)
811 {
812 case E_GOP0: // GOP4G
813 pGOPHalLocal->bank_offset = GOP_4G_OFST<<16;
814 return GOP_SUCCESS;
815 case E_GOP1: // GOP2G
816 pGOPHalLocal->bank_offset = GOP_2G_OFST<<16;
817 return GOP_SUCCESS;
818 case E_GOP2: // GOP1G
819 pGOPHalLocal->bank_offset = GOP_1G_OFST<<16;
820 return GOP_SUCCESS;
821 case E_GOP3: // GOP1GX
822 pGOPHalLocal->bank_offset = GOP_1GX_OFST<<16;
823 return GOP_SUCCESS;
824 case E_GOP4: // GOP1GS
825 pGOPHalLocal->bank_offset = GOP_1GS0_OFST<<16;
826 return GOP_SUCCESS;
827 default:
828 GOP_ASSERT(0);
829 return GOP_FAIL;
830 }
831 }
832
HAL_GOP_BANK_SEL(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_U8 u8bank)833 void HAL_GOP_BANK_SEL(GOP_CTX_HAL_LOCAL *pGOPHalLocal, MS_U8 u8bank)
834 {
835 MS_U16 u16Bank;
836 u16Bank = GOP_READ2BYTE(GOP_BAK_SEL);
837 u16Bank &= ~BMASK(3:0);
838 u16Bank |= (u8bank&BMASK(3:0));
839 GOP_WRITE2BYTE(GOP_BAK_SEL, u16Bank);
840 u16Bank = GOP_READ2BYTE(GOP_BAK_SEL_EX);
841 u16Bank &= ~GOP_BIT4;
842 u16Bank |= ((u8bank&GOP_BIT4)<<GOP_BIT4);
843 GOP_WRITE2BYTE(GOP_BAK_SEL_EX, u16Bank);
844 }
845
HAL_GOP_Get_BANK(GOP_CTX_HAL_LOCAL * pGOPHalLocal)846 MS_U8 HAL_GOP_Get_BANK(GOP_CTX_HAL_LOCAL *pGOPHalLocal)
847 {
848 MS_U16 u16GetBank;
849 u16GetBank = ((GOP_READ2BYTE(GOP_BAK_SEL_EX)& GOP_BIT8)>> GOP_BIT4)| (GOP_READ2BYTE(GOP_BAK_SEL)&0xF);
850 return (u16GetBank&GOP_BANK_MASK);
851 }
852
HAL_GOP_Read16Reg(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_U32 u32addr,MS_U16 * pu16ret)853 void HAL_GOP_Read16Reg(GOP_CTX_HAL_LOCAL *pGOPHalLocal, MS_U32 u32addr, MS_U16* pu16ret)
854 {
855 MS_U16 u16xcSubbank=0, u16BankAddr=0, u16BankTemp=0;
856 MS_U32 bank;
857 MS_U32 direct_addr;
858
859 GOP_H_INFO("HAL_GOP_Read16Reg[%td]\n", (ptrdiff_t)u32addr);
860
861 //* Gop driver should access another HW IP register
862 //* ex: SC's IP and OP setting, GE's det frame buffer setting, ChipTop GOP clk setting
863 switch (u32addr & 0xFF00)
864 {
865 case GOP_REG_BASE:
866 {
867 bank = (u32addr & 0xFF0000) >> 8;
868
869 if(bank==0xE00)//GOP4: 0x121B00
870 {
871 bank=GOP_REG_GOP4_BK_OFFSET;
872 }
873 else if(bank==0xF00)//GWIN4: 0x121E00
874 {
875 bank=GOP_REG_GOP4_GW_OFFSET;
876 }
877 else if(bank==0x1000)//GOP4_ST
878 {
879 bank=GOP_REG_GOP4_ST_OFFSET;
880 }
881 else if(bank==0x3100)//AFBC
882 {
883 direct_addr = AFBC_REG_BASE + (u32addr & 0xFF); //Direct_Base + addr_offset
884 *pu16ret = GOP_READ2BYTE((direct_addr&0xFFFFF));
885 break;
886 }
887
888 direct_addr = GOP_REG_DIRECT_BASE + bank + (u32addr & 0xFF); //Direct_Base + bank + addr_offset
889 *pu16ret = GOP_READ2BYTE((direct_addr&0xFFFFF));
890 break;
891 }
892 case SC1_REG_BASE:
893 {
894 if(g_GopChipPro.bXCDirrectBankSupport)
895 {
896 u16xcSubbank = (u32addr & 0xFF0000)>>8;
897 u32addr = SC1_DIRREG_BASE+ u16xcSubbank + (u32addr & 0xFF);
898 *pu16ret = GOP_READ2BYTE((u32addr&0xFFFFF));
899 }
900 else
901 {
902 u16xcSubbank = (u32addr & 0xFF0000)>>16;
903 u16BankAddr = GOP_SC_BANKSEL+0;
904 u32addr = SC1_REG_BASE + (u32addr & 0xFF);
905
906 u16BankTemp = GOP_READ2BYTE(u16BankAddr&0xFFFF);
907 GOP_WRITE2BYTE(u16BankAddr&0xFFFF, u16xcSubbank);
908 *pu16ret = GOP_READ2BYTE((u32addr&0xFFFF));
909 GOP_WRITE2BYTE(u16BankAddr&0xFFFF, u16BankTemp);
910 }
911 break;
912 }
913 case GE_REG_BASE:
914 case CKG_REG_BASE:
915 case MIU0_REG_BASE:
916 case MIU_REG_BASE:
917 case MVOP_REG_BASE:
918 {
919 *pu16ret = GOP_READ2BYTE((u32addr&0xFFFF));
920 break;
921 }
922 #ifdef GOP_MIU_GROUP2
923 case (MIU2_REG_BASE & 0xFF00):
924 {
925 direct_addr = MIU2_REG_BASE + (u32addr & 0xFF); //Direct_Base + addr_offset
926 *pu16ret = GOP_READ2BYTE((direct_addr&0xFFFFF));
927
928 break;
929 }
930 #endif
931 default:
932 {
933 //Gop lib current do not support this HW ip base
934 GOP_ASSERT(0);
935 *pu16ret =0;
936 break;
937 }
938 }
939 }
940
HAL_GOP_Write16Reg(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_U32 u32addr,MS_U16 u16val,MS_U16 mask)941 void HAL_GOP_Write16Reg(GOP_CTX_HAL_LOCAL *pGOPHalLocal, MS_U32 u32addr, MS_U16 u16val, MS_U16 mask)
942 {
943 MS_U16 u16tmp=0;
944 MS_U16 u16xcSubbank=0,u16BankAddr=0,pu16ret=0;
945 MS_U32 bank;
946 MS_U32 direct_addr;
947
948 MS_U8 u8_gop =INVAILD_GOP_NUM;
949 MS_U8 u8_mainGop =INVAILD_GOP_NUM, u8_combinedGop =INVAILD_GOP_NUM;
950 MS_U16 u16SubBnkOfst = 0x0;
951
952 GOP_H_INFO("HAL_GOP_Write16Reg[%04tx] = %04x\n", (ptrdiff_t)u32addr, u16val);
953
954 if(mask!=0xffff)
955 {
956 HAL_GOP_Read16Reg(pGOPHalLocal, u32addr, &u16tmp);
957 u16tmp &= ~mask;
958 u16val &= mask;
959 u16val |= u16tmp;
960 }
961
962 //* Gop driver should access another HW IP register
963 //* ex: SC's IP and OP setting, GE's det frame buffer setting, ChipTop GOP clk setting
964 switch (u32addr & 0xFF00)
965 {
966 case GOP_REG_BASE:
967 {
968 bank = (u32addr & 0xFF0000) >> 8;
969
970 if(bank==0xE00)//GOP4: 0x121B00
971 {
972 bank=GOP_REG_GOP4_BK_OFFSET;
973 }
974 else if(bank==0xF00)//GWIN4: 0x121E00
975 {
976 bank=GOP_REG_GOP4_GW_OFFSET;
977 }
978 else if(bank==0x1000) //GOP4_ST
979 {
980 bank=GOP_REG_GOP4_ST_OFFSET;
981 }
982 else if(bank==0x3100)//AFBC
983 {
984 direct_addr = AFBC_REG_BASE + (u32addr & 0xFF); //Direct_Base + addr_offset
985 GOP_WRITE2BYTE((direct_addr&0xFFFFF), u16val);
986 break;
987 }
988
989 if( FALSE == _dumpGopNumFromBnkOffset(&u8_gop, &u16SubBnkOfst, bank) )
990 {
991 GOP_H_ERR("Skipped [%s] Line %d !!", __FUNCTION__, __LINE__);
992 return;
993 }
994
995 if( FALSE == Hal_get4K120CombinedGOP(pGOPHalLocal, u8_gop, &u8_mainGop, &u8_combinedGop) )
996 {
997 GOP_H_ERR("Skipped [%s] Line %d !!", __FUNCTION__, __LINE__);
998 return;
999 }
1000
1001 if ((u8_gop == u8_mainGop) &&
1002 (pGOPHalLocal->pHALShared->GOP_Dst[u8_mainGop] == E_DRV_GOP_DST_OP_DUAL_RATE) &&
1003 (_isGopCommonRegs(u32addr & 0xFF) == FALSE) // combined register only the set once
1004 )
1005 {
1006 // to combine GOP0&GOP3, GOP1&GOP2
1007 MS_U8 u8_Copy2Gop = (u8_gop == u8_mainGop) ? u8_combinedGop : u8_mainGop;
1008 MS_U32 CopyGopbkofst = 0x0;
1009
1010 _GetBnkOfstByGop(u8_Copy2Gop, &CopyGopbkofst);
1011 CopyGopbkofst = (CopyGopbkofst >> 8) + u16SubBnkOfst;
1012
1013 direct_addr = GOP_REG_DIRECT_BASE + CopyGopbkofst + (u32addr & 0xFF);
1014 GOP_WRITE2BYTE((direct_addr&0xFFFFF), u16val);
1015 direct_addr = GOP_REG_DIRECT_BASE + bank + (u32addr & 0xFF);
1016 GOP_WRITE2BYTE((direct_addr&0xFFFFF), u16val);
1017 }
1018 else
1019 {
1020 direct_addr = GOP_REG_DIRECT_BASE + bank + (u32addr & 0xFF);
1021 GOP_WRITE2BYTE((direct_addr&0xFFFFF), u16val);
1022 }
1023 break;
1024 }
1025 case SC1_REG_BASE:
1026 if(g_GopChipPro.bXCDirrectBankSupport)
1027 { /*Derrick Bank*/
1028 u16xcSubbank = (u32addr & 0xFF0000)>>8 ;
1029 direct_addr = SC1_DIRREG_BASE + u16xcSubbank+ (u32addr & 0xFF);
1030 GOP_WRITE2BYTE((direct_addr&0xFFFFF), u16val);
1031 }
1032 else
1033 { /*Sub Bank*/
1034 u16xcSubbank = (u32addr & 0xFF0000)>>16 ;
1035 u16BankAddr = GOP_SC_BANKSEL+0;
1036 u32addr = SC1_REG_BASE + (u32addr & 0xFF);
1037
1038 pu16ret = GOP_READ2BYTE(u16BankAddr&0xFFFF);
1039 GOP_WRITE2BYTE((u16BankAddr&0xFFFF), u16xcSubbank);
1040 GOP_WRITE2BYTE((u32addr&0xFFFF), u16val);
1041 GOP_WRITE2BYTE((u16BankAddr&0xFFFF), pu16ret);
1042 }
1043 break;
1044 case GE_REG_BASE:
1045 case CKG_REG_BASE:
1046 case MIU0_REG_BASE:
1047 case MIU_REG_BASE:
1048 {
1049 GOP_WRITE2BYTE((u32addr&0xFFFF), u16val);
1050 break;
1051 }
1052 #ifdef GOP_MIU_GROUP2
1053 case (MIU2_REG_BASE & 0xFF00):
1054 {
1055 direct_addr = MIU2_REG_BASE + (u32addr & 0xFF); //Direct_Base + addr_offset
1056 GOP_WRITE2BYTE((direct_addr&0xFFFFF), u16val);
1057 break;
1058 }
1059 #endif
1060 default:
1061 {
1062 //Gop lib current do not support this HW ip base
1063 GOP_ASSERT(0);
1064 break;
1065 }
1066
1067 }
1068 }
1069
1070
HAL_GOP_Write32Reg(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_U32 u32addr,MS_U32 u32val)1071 void HAL_GOP_Write32Reg(GOP_CTX_HAL_LOCAL *pGOPHalLocal, MS_U32 u32addr, MS_U32 u32val)
1072 {
1073 HAL_GOP_Write16Reg(pGOPHalLocal, u32addr, (MS_U16)(u32val&0xFFFF), 0xffff);
1074 HAL_GOP_Write16Reg(pGOPHalLocal, u32addr+2, (MS_U16)((u32val&0xFFFF0000)>>16), 0xffff);
1075 }
1076
1077 //extern E_BDMA_Ret MDrv_BDMA_Mem_Fill(MS_U32 u32Addr, MS_U32 u32Len, MS_U32 u32Pattern, E_BDMA_DstDev eDev);
1078
HAL_GOP_Write32Pal(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_U8 * pREGMAP_Base,MS_U16 * pREGMAP_Offset,MS_U32 u32REGMAP_Len,MS_U8 u8Index,MS_U8 u8A,MS_U8 u8R,MS_U8 u8G,MS_U8 u8B)1079 void HAL_GOP_Write32Pal(GOP_CTX_HAL_LOCAL *pGOPHalLocal,
1080 MS_U8 *pREGMAP_Base, MS_U16 *pREGMAP_Offset, MS_U32 u32REGMAP_Len,
1081 MS_U8 u8Index, MS_U8 u8A, MS_U8 u8R, MS_U8 u8G, MS_U8 u8B)
1082 {
1083 MS_U8 i=0;
1084 GOP_H_INFO("GOP_Write32Pal : i= %02x, ARGB = %02x,%02x,%02x,%02x\n",u8Index, u8A, u8R, u8G, u8B);
1085
1086 /* Don't care high byte */
1087 GOP_ASSERT((MS_U32)(*pREGMAP_Offset +GOP_WordUnit)<= u32REGMAP_Len);
1088
1089 for(i =(GOP_WordUnit-1);i>4;i--)
1090 {
1091 *(pREGMAP_Base + *pREGMAP_Offset + i) = 0;
1092 }
1093 *(pREGMAP_Base + *pREGMAP_Offset + 4) = u8Index;
1094 *(pREGMAP_Base + *pREGMAP_Offset + 3) = u8A;
1095 *(pREGMAP_Base + *pREGMAP_Offset + 2) = u8R;
1096 *(pREGMAP_Base + *pREGMAP_Offset + 1) = u8G;
1097 *(pREGMAP_Base + *pREGMAP_Offset) = u8B;
1098 *pREGMAP_Offset += GOP_WordUnit;
1099
1100 MsOS_FlushMemory(); //make sure cpu write data to dram
1101
1102 }
1103
HAL_GOP_GetBPP(GOP_CTX_HAL_LOCAL * pGOPHalLocal,DRV_GOPColorType fbFmt)1104 MS_U16 HAL_GOP_GetBPP(GOP_CTX_HAL_LOCAL *pGOPHalLocal, DRV_GOPColorType fbFmt)
1105 {
1106 MS_U16 bpp=0;
1107
1108 switch ( fbFmt )
1109 {
1110 case E_DRV_GOP_COLOR_RGB555_BLINK :
1111 case E_DRV_GOP_COLOR_RGB565 :
1112 case E_DRV_GOP_COLOR_ARGB1555:
1113 case E_DRV_GOP_COLOR_RGBA5551:
1114 case E_DRV_GOP_COLOR_ARGB4444 :
1115 case E_DRV_GOP_COLOR_RGBA4444 :
1116 case E_DRV_GOP_COLOR_RGB555YUV422:
1117 case E_DRV_GOP_COLOR_YUV422:
1118 case E_DRV_GOP_COLOR_2266:
1119 bpp = 16;
1120 break;
1121 case E_DRV_GOP_COLOR_ARGB8888 :
1122 case E_DRV_GOP_COLOR_ABGR8888 :
1123 bpp = 32;
1124 break;
1125
1126 case E_DRV_GOP_COLOR_I8 :
1127 bpp = 8;
1128 break;
1129
1130 default :
1131 //print err
1132 GOP_ASSERT(0);
1133 bpp = 0xFFFF;
1134 break;
1135 }
1136 return bpp;
1137
1138 }
1139
HAL_GOP_GWIN_SetBlending(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_U8 u8win,MS_BOOL bEnable,MS_U8 u8coef)1140 void HAL_GOP_GWIN_SetBlending(GOP_CTX_HAL_LOCAL *pGOPHalLocal, MS_U8 u8win, MS_BOOL bEnable, MS_U8 u8coef)
1141 {
1142 MS_U16 regval;
1143 /*For compatibility
1144 Old chip only have alpha coeffient 6 bits. Charka2 define UI alpha value base on it.*/
1145 MS_U8 u8coef_cpt = u8coef;
1146
1147 //if UI alpha value based on alpha coeffient 6 bits, and our chip is 8bit, please do it.
1148 if( pGOPHalLocal->User_ConsAlpha_bits != g_GopChipPro.Default_ConsAlpha_bits)
1149 {
1150 switch(u8coef)
1151 {
1152 case 0x0 :
1153 u8coef_cpt = u8coef<<2;
1154 break;
1155 case 0x3f :
1156 u8coef_cpt = ((u8coef<<2)|0x3);
1157 break;
1158 default:
1159 u8coef_cpt = ((u8coef<<2)|0x1);
1160 break;
1161 }
1162 }
1163
1164 /*alpha coeffient 6/8bit chip has GOP0,GOP1*/
1165 if (u8win<(MAX_GOP0_GWIN+MAX_GOP1_GWIN))
1166 {
1167 regval = (MS_U16)(bEnable?(1<<14):0)|(MS_U16)((u8coef&0x3F)<<8);
1168 HAL_GOP_Write16Reg(pGOPHalLocal, (u8win < MAX_GOP0_GWIN)? GOP_4G_GWIN0_CTRL(u8win):GOP_2G_GWIN_CTRL(u8win-MAX_GOP0_GWIN), regval, 0x4000);
1169 HAL_GOP_Write16Reg(pGOPHalLocal, (u8win < MAX_GOP0_GWIN)? GOP_4G_GWIN_ALPHA01(u8win):GOP_2G_GWIN_ALPHA01(u8win-MAX_GOP0_GWIN), u8coef_cpt, 0xFF);
1170 }
1171 /*Only alpha coeffient 8bit chip has GOP2,GOP3...*/
1172 else
1173 {
1174 if (u8win==(MAX_GOP0_GWIN+MAX_GOP1_GWIN))
1175 {
1176 regval = (MS_U16)(bEnable?(1<<14):0);
1177 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_1G_GWIN0_CTRL, regval, 0x4000);
1178 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_1G_GWIN_ALPHA01, u8coef, 0xFF);
1179 }
1180 else if ((u8win==(MAX_GOP0_GWIN+MAX_GOP1_GWIN+MAX_GOP2_GWIN)))
1181 {
1182 regval = (MS_U16)(bEnable?(1<<14):0);
1183 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_1GX_GWIN0_CTRL, regval, 0x4000);
1184 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_1GX_GWIN_ALPHA01, u8coef, 0xFF);
1185 }
1186 else
1187 {
1188 regval = (MS_U16)(bEnable?(1<<14):0);
1189 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_1GS0_GWIN0_CTRL, regval, 0x4000);
1190 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_1GS0_GWIN_ALPHA01, u8coef, 0xFF);
1191 }
1192 }
1193 }
1194
HAL_GOP_SetIOMapBase(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_VIRT addr)1195 void HAL_GOP_SetIOMapBase(GOP_CTX_HAL_LOCAL *pGOPHalLocal, MS_VIRT addr)
1196 {
1197 pGOPHalLocal->va_mmio_base = addr;
1198 }
HAL_GOP_SetIOFRCMapBase(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_VIRT addr)1199 void HAL_GOP_SetIOFRCMapBase(GOP_CTX_HAL_LOCAL *pGOPHalLocal, MS_VIRT addr)
1200 {
1201 }
HAL_GOP_SetIOPMMapBase(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_VIRT addr)1202 void HAL_GOP_SetIOPMMapBase(GOP_CTX_HAL_LOCAL *pGOPHalLocal, MS_VIRT addr)
1203 {
1204 }
1205
1206
HAL_GOP_GWIN_SetDstPlane(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_U8 GopNum,DRV_GOPDstType eDstType,MS_BOOL bOnlyCheck)1207 GOP_Result HAL_GOP_GWIN_SetDstPlane(GOP_CTX_HAL_LOCAL *pGOPHalLocal, MS_U8 GopNum, DRV_GOPDstType eDstType,MS_BOOL bOnlyCheck)
1208 {
1209 /*A5 GOP dst type:
1210 1: IP (Main)
1211 0: IP (Sub)
1212 2: OP
1213 3: MVOP
1214 4: MVOP (Sub)
1215 6: FRC
1216 11: InsideFRC
1217 */
1218 MS_U8 i=0, Cnt=0;
1219 MS_U16 u16RegVal;
1220 MS_U32 u32BankOffSet;
1221 DRV_GOPDstType pGopDst;
1222 MS_BOOL bEnable;
1223 MS_U16 u16HSyncMask=GOP_BIT14;
1224 MS_U8 u8_mainGop = INVAILD_GOP_NUM, u8_combinedGop = INVAILD_GOP_NUM;
1225
1226 if( GopNum >= MAX_GOP_SUPPORT)
1227 {
1228 return GOP_INVALID_PARAMETERS;
1229 }
1230
1231 switch (eDstType)
1232 {
1233 case E_DRV_GOP_DST_IP0:
1234 u16RegVal = 0x0;
1235 bEnable = FALSE;
1236 u16HSyncMask=0;
1237 break;
1238
1239 case E_DRV_GOP_DST_IP0_SUB:
1240 u16RegVal = 0x1;
1241 bEnable = FALSE;
1242 u16HSyncMask=0;
1243 break;
1244
1245 case E_DRV_GOP_DST_OP0:
1246 u16RegVal = 0x2;
1247 bEnable = FALSE;
1248 u16HSyncMask=GOP_BIT14;
1249 break;
1250
1251 case E_DRV_GOP_DST_VOP:
1252 u16RegVal = 0x3;
1253 bEnable = FALSE;
1254 u16HSyncMask=GOP_BIT14;
1255 break;
1256
1257 case E_DRV_GOP_DST_VOP_SUB:
1258 u16RegVal = 0x4;
1259 bEnable = FALSE;
1260 u16HSyncMask=GOP_BIT14;
1261 break;
1262
1263 case E_DRV_GOP_DST_FRC:
1264 u16RegVal = 0x6;
1265 bEnable = TRUE;
1266 u16HSyncMask=GOP_BIT14;
1267 break;
1268
1269 case E_DRV_GOP_DST_VE:
1270 u16RegVal = 0x7;
1271 bEnable = TRUE;
1272 u16HSyncMask=GOP_BIT14;
1273 break;
1274 case E_DRV_GOP_DST_DIP:
1275 u16RegVal = 0x8;
1276 bEnable = TRUE;
1277 u16HSyncMask=GOP_BIT14;
1278 break;
1279 case E_DRV_GOP_DST_OP_DUAL_RATE:
1280 u16RegVal = 0xB;
1281 bEnable = FALSE;
1282 u16HSyncMask=0x0;
1283 break;
1284 default:
1285 return GOP_FUN_NOT_SUPPORTED;
1286 }
1287 if(bOnlyCheck == FALSE)
1288 {
1289 Hal_get4K120CombinedGOP(pGOPHalLocal, GopNum, &u8_mainGop, &u8_combinedGop);
1290 if (E_DRV_GOP_DST_OP_DUAL_RATE == eDstType)
1291 {
1292 pGOPHalLocal->pHALShared->GOP_Dst[u8_mainGop] = eDstType;
1293 pGOPHalLocal->pHALShared->GOP_Dst[u8_combinedGop] = eDstType;
1294 }
1295 else
1296 {
1297 pGOPHalLocal->pHALShared->GOP_Dst[GopNum] = eDstType;
1298 }
1299
1300 _GetBnkOfstByGop(GopNum, &u32BankOffSet);
1301 HAL_GOP_SetGOP2Pto1P(pGOPHalLocal, GopNum, bEnable);
1302 HAL_GOP_Write16Reg(pGOPHalLocal, u32BankOffSet+GOP_4G_CTRL1, u16RegVal, BMASK(GOP_BIT3:0));
1303
1304 //For Bypass
1305 for(i=0; i<MAX_GOP_SUPPORT ;i++)
1306 {
1307 HAL_GOP_GetGOPDst(pGOPHalLocal, i, &pGopDst);
1308 if(pGopDst == E_DRV_GOP_DST_FRC)
1309 {
1310 Cnt++;
1311 }
1312 }
1313
1314 if (E_DRV_GOP_DST_OP_DUAL_RATE == eDstType)
1315 {
1316 Hal_Ctrl4K120GopMode(pGOPHalLocal, GopNum, TRUE);
1317 Hal_SetCropWindow(pGOPHalLocal, GopNum, EN_GOP_CROP_ENABLE);
1318 }
1319 else
1320 {
1321 Hal_Ctrl4K120GopMode(pGOPHalLocal, GopNum, FALSE);
1322 Hal_SetCropWindow(pGOPHalLocal, GopNum, EN_GOP_CROP_DISABLE);
1323 }
1324
1325 HAL_GOP_Write16Reg(pGOPHalLocal, u32BankOffSet+GOP_4G_CTRL0, u16HSyncMask, GOP_BIT14); // Set mask Hsync when VFDE is low
1326 }
1327 return GOP_SUCCESS;
1328 }
1329
HAL_GOP_SetMixerDst(GOP_CTX_HAL_LOCAL * pGOPHalLocal,DRV_GOPDstType eDstType)1330 GOP_Result HAL_GOP_SetMixerDst(GOP_CTX_HAL_LOCAL *pGOPHalLocal, DRV_GOPDstType eDstType)
1331 {
1332 return GOP_FUN_NOT_SUPPORTED;
1333 }
1334
HAL_GOP_GetMixerDst(GOP_CTX_HAL_LOCAL * pGOPHalLocal,DRV_GOPDstType * pGopDst)1335 GOP_Result HAL_GOP_GetMixerDst(GOP_CTX_HAL_LOCAL *pGOPHalLocal, DRV_GOPDstType *pGopDst)
1336 {
1337 return GOP_FUN_NOT_SUPPORTED;
1338 }
1339
HAL_GOP_InitMux(GOP_CTX_HAL_LOCAL * pGOPHalLocal)1340 GOP_Result HAL_GOP_InitMux(GOP_CTX_HAL_LOCAL *pGOPHalLocal)
1341 {
1342 /*T8
1343 OP path: support 3 mux (mux0, mux 2, mux3) to blend with SC simultaneously
1344 IP path: support mux0 and mux1 to IPMain/IPSub. Only one mux of mux0 and mux1 can be blended to IPMain/IPSub
1345 SW default setting=> mux0:gop1g, mux1:gop1gx, mux2:gop2g, mux3:gop4g
1346 */
1347 MS_U8 gop4g=0, gop2g=1, gop1g=2, gop1gx=3, gop1gs=4;
1348 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_MUX, ((gop1gs<<(GOP_MUX_SHIFT*4))|(gop4g<<(GOP_MUX_SHIFT*3))|(gop2g<<(GOP_MUX_SHIFT*2))|(gop1gx<<(GOP_MUX_SHIFT*1))|gop1g), GOP_REG_WORD_MASK);
1349 //THEALE/utopia_release/UTPA2-205.0.x_Muji/mxlib/hal/muji/gop/
1350 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_MUX_4K2K, 0x7<< GOP_DIP_MUX_SHIFT, GOP_DIP_MUX_MASK);
1351
1352 // 4k120_mux0: GOP0+GOP3
1353 // 4k120_mux1: GOP2+GOP1
1354 // 4k120_mux2: GOP4
1355 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_MUX4_4K120, 0x24, 0x3F);
1356
1357 return GOP_SUCCESS;
1358 }
1359
HAL_GOP_GWIN_GetMUX(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_U8 * u8GOPNum,Gop_MuxSel eGopMux)1360 void HAL_GOP_GWIN_GetMUX(GOP_CTX_HAL_LOCAL*pGOPHalLocal, MS_U8* u8GOPNum, Gop_MuxSel eGopMux)
1361 {
1362 MS_U16 u16GopMux=0;
1363
1364 switch(eGopMux)
1365 {
1366 case E_GOP_MUX0:
1367 case E_GOP_MUX1:
1368 case E_GOP_MUX2:
1369 case E_GOP_MUX3:
1370 case E_GOP_MUX4:
1371 HAL_GOP_Read16Reg(pGOPHalLocal, GOP_MUX, &u16GopMux);
1372 *u8GOPNum = (u16GopMux >> (eGopMux*GOP_MUX_SHIFT))& GOP_REGMUX_MASK;
1373 break;
1374 case E_GOP_IP0_MUX:
1375 HAL_GOP_Read16Reg(pGOPHalLocal, GOP_MUX_IPVOP, &u16GopMux);
1376 *u8GOPNum = (u16GopMux&GOP_IP_MAIN_MUX_MASK)>>GOP_IP_MAIN_MUX_SHIFT;
1377 break;
1378 case E_GOP_IP0_SUB_MUX:
1379 HAL_GOP_Read16Reg(pGOPHalLocal, GOP_MUX_IPVOP, &u16GopMux);
1380 *u8GOPNum = (u16GopMux&GOP_IP_SUB_MUX_MASK)>>GOP_IP_SUB_MUX_SHIFT;
1381 break;
1382 case E_GOP_VOP0_MUX:
1383 HAL_GOP_Read16Reg(pGOPHalLocal, GOP_MUX_IPVOP, &u16GopMux);
1384 *u8GOPNum = (u16GopMux&GOP_IP_VOP0_MUX_MASK)>>GOP_IP_VOP0_MUX_SHIFT;
1385 break;
1386 case E_GOP_VOP0_SUB_MUX:
1387 HAL_GOP_Read16Reg(pGOPHalLocal, GOP_MUX_IPVOP, &u16GopMux);
1388 *u8GOPNum = (u16GopMux&GOP_IP_VOP1_MUX_MASK)>>GOP_IP_VOP1_MUX_SHIFT;
1389 break;
1390 case E_GOP_Mix_MUX0:
1391 HAL_GOP_Read16Reg(pGOPHalLocal, GOP_MUX4_MIX_VE, &u16GopMux);
1392 *u8GOPNum = (u16GopMux&GOP_Mix_MUX0_MASK)>>GOP_Mix_MUX0_SHIFT;
1393 break;
1394 case E_GOP_Mix_MUX1:
1395 HAL_GOP_Read16Reg(pGOPHalLocal, GOP_MUX4_MIX_VE, &u16GopMux);
1396 *u8GOPNum = (u16GopMux&GOP_Mix_MUX1_MASK)>>GOP_Mix_MUX1_SHIFT;
1397 break;
1398 case E_GOP_VE0_MUX:
1399 HAL_GOP_Read16Reg(pGOPHalLocal, GOP_MUX4_MIX_VE, &u16GopMux);
1400 *u8GOPNum = (u16GopMux&GOP_VE0_MUX_MASK)>>GOP_VE0_MUX_SHIFT;
1401 break;
1402 case E_GOP_VE1_MUX:
1403 HAL_GOP_Read16Reg(pGOPHalLocal, GOP_MUX4_MIX_VE, &u16GopMux);
1404 *u8GOPNum = (u16GopMux&GOP_VE1_MUX_MASK)>>GOP_VE1_MUX_SHIFT;
1405 break;
1406 case E_GOP_DIP_MUX:
1407 HAL_GOP_Read16Reg(pGOPHalLocal, GOP_MUX_4K2K, &u16GopMux);
1408 *u8GOPNum = (u16GopMux&GOP_DIP_MUX_MASK)>>GOP_DIP_MUX_SHIFT;
1409 break;
1410 case E_GOP_FRC_MUX0:
1411 case E_GOP_FRC_MUX1:
1412 case E_GOP_FRC_MUX2:
1413 case E_GOP_FRC_MUX3:
1414 HAL_GOP_Read16Reg(pGOPHalLocal, GOP_MUX_4K2K, &u16GopMux);
1415 *u8GOPNum = (u16GopMux >> ((eGopMux%E_GOP_FRC_MUX0)*GOP_FRC_MUX_SHIFT))& GOP_FRC_REGMUX_MASK;
1416 break;
1417 case E_GOP_BYPASS_MUX0:
1418 break;
1419
1420 case E_GOP_DUALRATE_OP_MUX0:
1421 case E_GOP_DUALRATE_OP_MUX1:
1422 case E_GOP_DUALRATE_OP_MUX2:
1423 {
1424 MS_U8 mux_sel_idx;
1425 HAL_GOP_Read16Reg(pGOPHalLocal, GOP_MUX4_4K120, &u16GopMux);
1426
1427 mux_sel_idx = (u16GopMux >> ((eGopMux-E_GOP_DUALRATE_OP_MUX0)*GOP_4K120_MUX_SHIFT))& GOP_4K120_REGMUX_MASK;
1428 if (mux_sel_idx < GOP_4K120_MUX_COUNT)
1429 {
1430 *u8GOPNum = GOP_4K120MUX_IDX_TABLE[mux_sel_idx];
1431 }
1432 else
1433 {
1434 *u8GOPNum = MAX_GOP_DualMUX_Num;
1435 }
1436 }
1437 break;
1438 case E_GOP_IP1_MUX:
1439 case E_GOP_VOP1_MUX:
1440 case E_GOP_OP1_MUX:
1441 case E_GOP_GS_MUX:
1442 // to prevent warning log
1443 break;
1444 default:
1445 GOP_H_ERR("[%s]ERROR, not support the mux[%d]\n",__FUNCTION__,eGopMux);
1446 break;
1447 }
1448 }
1449
HAL_GOP_GWIN_SetMUX(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_U8 u8GOPNum,Gop_MuxSel eGopMux)1450 void HAL_GOP_GWIN_SetMUX(GOP_CTX_HAL_LOCAL*pGOPHalLocal, MS_U8 u8GOPNum, Gop_MuxSel eGopMux)
1451 {
1452 MS_U16 u16Ret[4]={0};
1453 MS_U8 u8_mainGop = INVAILD_GOP_NUM, u8_combinedGop = INVAILD_GOP_NUM;
1454
1455 if( FALSE == Hal_get4K120CombinedGOP(pGOPHalLocal, u8GOPNum, &u8_mainGop, &u8_combinedGop) )
1456 {
1457 GOP_H_ERR("Skipped [%s] Line %d !!", __FUNCTION__, __LINE__);
1458 return;
1459 }
1460
1461 if (pGOPHalLocal->pHALShared->GOP_Dst[u8_mainGop] == E_DRV_GOP_DST_OP_DUAL_RATE)
1462 {
1463 if (eGopMux == E_GOP_MUX0)
1464 {
1465 eGopMux = E_GOP_DUALRATE_OP_MUX0;
1466 }
1467 else if (eGopMux == E_GOP_MUX1)
1468 {
1469 eGopMux = E_GOP_DUALRATE_OP_MUX1;
1470 }
1471 else if (eGopMux == E_GOP_MUX2)
1472 {
1473 eGopMux = E_GOP_DUALRATE_OP_MUX2;
1474 }
1475 else if ((eGopMux == E_GOP_MUX3) || (eGopMux == E_GOP_MUX4))
1476 {
1477 eGopMux = E_GOP_MUX_INVAILD;
1478 }
1479 }
1480
1481 switch(eGopMux)
1482 {
1483 case E_GOP_MUX0:
1484 case E_GOP_MUX1:
1485 case E_GOP_MUX2:
1486 case E_GOP_MUX3:
1487 case E_GOP_MUX4:
1488 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_MUX, u8GOPNum <<(GOP_MUX_SHIFT*eGopMux), GOP_REGMUX_MASK<<(GOP_MUX_SHIFT*eGopMux));
1489 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_BAK_SEL_EX, GOP_BIT15 , GOP_BIT15); // trigger
1490 break;
1491
1492 case E_GOP_DUALRATE_OP_MUX0:
1493 case E_GOP_DUALRATE_OP_MUX1:
1494 case E_GOP_DUALRATE_OP_MUX2:
1495 // if GOP0 on 4K120 mode, GOP3 can't set to other destination
1496 if ((u8GOPNum == u8_combinedGop) && (u8_mainGop != E_GOP4))
1497 {
1498 GOP_H_ERR("[%s]GOP%d can't set to other mode when GOP%d is on 4K@120\n",
1499 __FUNCTION__, u8_combinedGop, u8_mainGop);
1500 break;
1501 }
1502 if (u8_mainGop == E_GOP0)
1503 {
1504 // for GOP0+GOP3
1505 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_MUX4_4K120, 0, GOP_4K120_REGMUX_MASK<<(GOP_4K120_MUX_SHIFT*(eGopMux-E_GOP_DUALRATE_OP_MUX0)));
1506 }
1507 else if (u8_mainGop == E_GOP2)
1508 {
1509 // for GOP1+GOOP2
1510 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_MUX4_4K120, 1, GOP_4K120_REGMUX_MASK<<(GOP_4K120_MUX_SHIFT*(eGopMux-E_GOP_DUALRATE_OP_MUX0)));
1511 }
1512 else if (u8_mainGop == E_GOP4)
1513 {
1514 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_MUX4_4K120, 2, GOP_4K120_REGMUX_MASK<<(GOP_4K120_MUX_SHIFT*(eGopMux-E_GOP_DUALRATE_OP_MUX0)));
1515 }
1516 break;
1517 case E_GOP_IP0_MUX:
1518 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_MUX_IPVOP, u8GOPNum << GOP_IP_MAIN_MUX_SHIFT, GOP_IP_MAIN_MUX_MASK);
1519 break;
1520 case E_GOP_IP1_MUX:
1521 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_MUX_IPVOP, u8GOPNum << GOP_IP_SUB_MUX_SHIFT, GOP_IP_SUB_MUX_MASK);
1522 break;
1523 case E_GOP_VOP0_MUX:
1524 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_MUX_IPVOP, u8GOPNum << GOP_IP_VOP0_MUX_SHIFT, GOP_IP_VOP0_MUX_MASK);
1525 break;
1526 case E_GOP_VOP1_MUX:
1527 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_MUX_IPVOP, u8GOPNum << GOP_IP_VOP1_MUX_SHIFT, GOP_IP_VOP1_MUX_MASK);
1528 break;
1529 case E_GOP_Mix_MUX0:
1530 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_MUX4_MIX_VE, u8GOPNum << GOP_Mix_MUX0_SHIFT, GOP_Mix_MUX0_MASK);
1531 break;
1532 case E_GOP_Mix_MUX1:
1533 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_MUX4_MIX_VE, u8GOPNum << GOP_Mix_MUX1_SHIFT, GOP_Mix_MUX1_MASK);
1534 break;
1535 case E_GOP_VE0_MUX:
1536 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_MUX4_MIX_VE, u8GOPNum << GOP_VE0_MUX_SHIFT, GOP_VE0_MUX_MASK);
1537 break;
1538 case E_GOP_VE1_MUX:
1539 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_MUX4_MIX_VE, u8GOPNum << GOP_VE1_MUX_SHIFT, GOP_VE1_MUX_MASK);
1540 break;
1541 case E_GOP_DIP_MUX:
1542 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_MUX_4K2K, u8GOPNum << GOP_DIP_MUX_SHIFT, GOP_DIP_MUX_MASK);
1543 break;
1544 case E_GOP_FRC_MUX0:
1545 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_MUX_4K2K, u8GOPNum <<(GOP_FRC_MUX_SHIFT*(eGopMux%E_GOP_FRC_MUX0)) , GOP_REGMUX_MASK<<(GOP_FRC_MUX_SHIFT*(eGopMux%E_GOP_FRC_MUX0)));
1546 break;
1547 case E_GOP_FRC_MUX1:
1548 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_MUX_4K2K, u8GOPNum <<(GOP_FRC_MUX_SHIFT*(eGopMux%E_GOP_FRC_MUX0)) , GOP_REGMUX_MASK<<(GOP_FRC_MUX_SHIFT*(eGopMux%E_GOP_FRC_MUX0)));
1549 break;
1550 case E_GOP_FRC_MUX2:
1551 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_MUX_4K2K, u8GOPNum <<(GOP_FRC_MUX_SHIFT*(eGopMux%E_GOP_FRC_MUX0)) , GOP_REGMUX_MASK<<(GOP_FRC_MUX_SHIFT*(eGopMux%E_GOP_FRC_MUX0)));
1552 break;
1553 case E_GOP_FRC_MUX3:
1554 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_MUX_4K2K, u8GOPNum <<(GOP_FRC_MUX_SHIFT*(eGopMux%E_GOP_FRC_MUX0)) , GOP_REGMUX_MASK<<(GOP_FRC_MUX_SHIFT*(eGopMux%E_GOP_FRC_MUX0)));
1555 break;
1556 case E_GOP_BYPASS_MUX0:
1557 //Check MUX is using? Checking from priority high to low
1558 HAL_GOP_Read16Reg(pGOPHalLocal, GOP_SC_FRC_LAYER2_L_EN, &u16Ret[0]);
1559 HAL_GOP_Read16Reg(pGOPHalLocal, GOP_SC_FRC_LAYER2_R_EN, &u16Ret[1]);
1560 HAL_GOP_Read16Reg(pGOPHalLocal, GOP_SC_FRC_LAYER1_L_EN, &u16Ret[2]);
1561 HAL_GOP_Read16Reg(pGOPHalLocal, GOP_SC_FRC_LAYER1_R_EN, &u16Ret[3]);
1562
1563 //Checking if un-use
1564 if((u16Ret[0] & GOP_BIT0) ==0)
1565 {
1566 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_MUX_4K2K, u8GOPNum <<(GOP_FRC_MUX_SHIFT*(E_GOP_FRC_MUX2%E_GOP_FRC_MUX0)) , GOP_REGMUX_MASK<<(GOP_FRC_MUX_SHIFT*(E_GOP_FRC_MUX2%E_GOP_FRC_MUX0)));
1567 }
1568 else if((u16Ret[1] & GOP_BIT0) ==0)
1569 {
1570 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_MUX_4K2K, u8GOPNum <<(GOP_FRC_MUX_SHIFT*(E_GOP_FRC_MUX3%E_GOP_FRC_MUX0)) , GOP_REGMUX_MASK<<(GOP_FRC_MUX_SHIFT*(E_GOP_FRC_MUX3%E_GOP_FRC_MUX0)));
1571 }
1572 else if((u16Ret[2] & GOP_BIT0) ==0)
1573 {
1574 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_MUX_4K2K, u8GOPNum <<(GOP_FRC_MUX_SHIFT*(E_GOP_FRC_MUX0%E_GOP_FRC_MUX0)) , GOP_REGMUX_MASK<<(GOP_FRC_MUX_SHIFT*(E_GOP_FRC_MUX0%E_GOP_FRC_MUX0)));
1575 }
1576 else if((u16Ret[3] & GOP_BIT0) ==0)
1577 {
1578 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_MUX_4K2K, u8GOPNum <<(GOP_FRC_MUX_SHIFT*(E_GOP_FRC_MUX1%E_GOP_FRC_MUX0)) , GOP_REGMUX_MASK<<(GOP_FRC_MUX_SHIFT*(E_GOP_FRC_MUX1%E_GOP_FRC_MUX0)));
1579 }
1580 else
1581 {
1582 GOP_H_ERR("[%s][%d]FRC mux is already full.\n",__FUNCTION__,__LINE__);
1583 }
1584 break;
1585 break;
1586 default:
1587 GOP_H_ERR("[%s]ERROR mux setting\n",__FUNCTION__);
1588 break;
1589 }
1590 }
1591
HAL_GOP_SetGOPEnable2SC(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_U8 gopNum,MS_BOOL bEnable)1592 GOP_Result HAL_GOP_SetGOPEnable2SC(GOP_CTX_HAL_LOCAL *pGOPHalLocal, MS_U8 gopNum, MS_BOOL bEnable)
1593 {
1594 /* GOP OP Path enable to SC Setting
1595 A5: GOP OP Path blending with SC sequence
1596 mux1-->mux0-->mux2-->mux3
1597 */
1598 MS_U16 muxValue=0, regval=0;
1599
1600 DRV_GOPDstType pGopDst = E_DRV_GOP_DST_INVALID;
1601 MS_U16 u164K2KMuxValue=0;
1602 MS_U8 u8_mainGop = INVAILD_GOP_NUM, u8_combinedGop = INVAILD_GOP_NUM;
1603 MS_U8 mux_need_ctrl = 0;
1604
1605 HAL_GOP_Read16Reg(pGOPHalLocal, GOP_MUX, &muxValue);
1606 HAL_GOP_Read16Reg(pGOPHalLocal, GOP_SC_GOPEN, ®val);
1607
1608 if (gopNum== (muxValue & GOP_MUX0_MASK)) //enable mux0 to SC
1609 {
1610 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_SC_GOPEN, bEnable?(regval |GOP_BIT15):(regval & ~GOP_BIT15), GOP_BIT15);
1611 }
1612
1613 if (gopNum== ((muxValue & GOP_MUX1_MASK)>>(GOP_MUX_SHIFT*1))) //enable mux1
1614 {
1615 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_SC_GOPEN, bEnable?(regval | GOP_BIT14):(regval & ~GOP_BIT14), GOP_BIT14);
1616 }
1617
1618 if (gopNum== ((muxValue & GOP_MUX2_MASK)>>(GOP_MUX_SHIFT*2))) //enable mux2
1619 {
1620 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_SC_GOPEN, bEnable?(regval |GOP_BIT13):(regval & ~GOP_BIT13), GOP_BIT13);
1621 }
1622
1623 if (gopNum== ((muxValue & GOP_MUX3_MASK)>>(GOP_MUX_SHIFT*3))) //enable mux3
1624 {
1625 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_SC_GOPEN, bEnable?(regval |GOP_BIT12):(regval & ~GOP_BIT12), GOP_BIT12);
1626 }
1627
1628 if (gopNum== ((muxValue & GOP_MUX4_MASK)>> (GOP_MUX_SHIFT*4))) //enable mux4
1629 {
1630 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_SC_GOPEN, bEnable?(regval |GOP_BIT11):(regval & ~GOP_BIT11), GOP_BIT11);
1631 }
1632
1633 /*For FRC mux switch*/
1634 HAL_GOP_GetGOPDst(pGOPHalLocal, gopNum, &pGopDst);
1635 HAL_GOP_Read16Reg(pGOPHalLocal, GOP_MUX_4K2K, &u164K2KMuxValue);
1636 if (gopNum== (u164K2KMuxValue & GOP_MUX0_MASK))
1637 {
1638 /* Switch FRC blending */
1639 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_SC_FRC_LAYER1_L_EN, (pGopDst==E_DRV_GOP_DST_BYPASS)?GOP_BIT0: ~GOP_BIT0, GOP_BIT0);
1640 }
1641
1642 if (gopNum== ((u164K2KMuxValue & GOP_MUX1_MASK)>>(GOP_MUX_SHIFT*1)))
1643 {
1644 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_SC_FRC_LAYER1_R_EN, (pGopDst==E_DRV_GOP_DST_BYPASS)?GOP_BIT0: ~GOP_BIT0, GOP_BIT0);
1645 }
1646
1647 if (gopNum== ((u164K2KMuxValue & GOP_MUX2_MASK)>>(GOP_MUX_SHIFT*2)))
1648 {
1649 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_SC_FRC_LAYER2_L_EN, (pGopDst==E_DRV_GOP_DST_BYPASS)?GOP_BIT0: ~GOP_BIT0, GOP_BIT0);
1650 }
1651
1652 if (gopNum== ((u164K2KMuxValue & GOP_MUX3_MASK)>>(GOP_MUX_SHIFT*3)))
1653 {
1654 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_SC_FRC_LAYER2_R_EN, (pGopDst==E_DRV_GOP_DST_BYPASS)?GOP_BIT0: ~GOP_BIT0, GOP_BIT0);
1655 }
1656
1657
1658 Hal_get4K120CombinedGOP(pGOPHalLocal, gopNum, &u8_mainGop, &u8_combinedGop);
1659 if ((E_DRV_GOP_DST_OP_DUAL_RATE == pGopDst) &&
1660 (u8_mainGop != u8_combinedGop))
1661 {
1662 // disable the xc OP blending mux of sub GOP
1663 if (u8_combinedGop== (muxValue & GOP_MUX0_MASK)) //enable mux0 to SC
1664 {
1665 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_SC_GOPEN, (regval & ~GOP_BIT15), GOP_BIT15);
1666 }
1667 else if (u8_combinedGop== ((muxValue & GOP_MUX1_MASK)>>(GOP_MUX_SHIFT*1)))
1668 {
1669 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_SC_GOPEN, (regval & ~GOP_BIT12), GOP_BIT12);
1670 }
1671 else if (u8_combinedGop== ((muxValue & GOP_MUX2_MASK)>>(GOP_MUX_SHIFT*2)))
1672 {
1673 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_SC_GOPEN, (regval & ~GOP_BIT14), GOP_BIT14);
1674 }
1675 else if (u8_combinedGop== ((muxValue & GOP_MUX3_MASK)>>(GOP_MUX_SHIFT*3)))
1676 {
1677 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_SC_GOPEN, (regval & ~GOP_BIT13), GOP_BIT13);
1678 }
1679 else if (u8_combinedGop== ((muxValue & GOP_MUX4_MASK)>> (GOP_MUX_SHIFT*4)))
1680 {
1681 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_SC_GOPEN, (regval & ~GOP_BIT11), GOP_BIT11);
1682 }
1683 }
1684
1685 mux_need_ctrl = _findMuxNumberByGOP(pGOPHalLocal, pGopDst, u8_mainGop);
1686 if (GOP_4K120MUX_MUX0 == mux_need_ctrl)
1687 {
1688 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_SC_4K120_EN0, (E_DRV_GOP_DST_OP_DUAL_RATE == pGopDst) ? GOP_BIT15 : ~GOP_BIT15, GOP_BIT15);
1689 }
1690 else if (GOP_4K120MUX_MUX1 == mux_need_ctrl)
1691 {
1692 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_SC_4K120_EN1, (E_DRV_GOP_DST_OP_DUAL_RATE == pGopDst) ? GOP_BIT15 : ~GOP_BIT15, GOP_BIT15);
1693 }
1694 else if (GOP_4K120MUX_MUX2 == mux_need_ctrl)
1695 {
1696 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_SC_4K120_EN2, (E_DRV_GOP_DST_OP_DUAL_RATE == pGopDst) ? GOP_BIT15 : ~GOP_BIT15, GOP_BIT15);
1697 }
1698
1699 return GOP_SUCCESS;
1700 }
1701
HAL_GOP_SetGOP2Pto1P(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_U8 gopNum,MS_BOOL bEnable)1702 GOP_Result HAL_GOP_SetGOP2Pto1P(GOP_CTX_HAL_LOCAL *pGOPHalLocal, MS_U8 gopNum, MS_BOOL bEnable)
1703 {
1704 MS_U32 u32pBankOffSet=0;
1705 MS_U16 u16Regval;
1706
1707 if(g_GopChipPro.b2Pto1PSupport)
1708 {
1709 _GetBnkOfstByGop(gopNum, &u32pBankOffSet);
1710 HAL_GOP_Read16Reg(pGOPHalLocal, u32pBankOffSet + GOP_4G_SRAM_BORROW, &u16Regval);
1711 HAL_GOP_Write16Reg(pGOPHalLocal, u32pBankOffSet + GOP_4G_SRAM_BORROW, bEnable?(u16Regval |0x0800):(u16Regval & ~0x0800), 0x0800);
1712 }
1713 return GOP_SUCCESS;
1714 }
1715
_IsGopInDualOpMux(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_U8 u8GopNum,Gop_MuxSel * corr_mux)1716 static MS_BOOL _IsGopInDualOpMux(GOP_CTX_HAL_LOCAL* pGOPHalLocal, MS_U8 u8GopNum, Gop_MuxSel * corr_mux)
1717 {
1718 MS_U8 i=0x0;
1719 MS_U8 mux_val = 0x0;
1720 for (i=0; i<GOP_4K120_MUX_COUNT; i++)
1721 {
1722 HAL_GOP_GWIN_GetMUX(pGOPHalLocal, &mux_val, (Gop_MuxSel)i + E_GOP_DUALRATE_OP_MUX0);
1723 if (((u8GopNum == E_GOP0) && (mux_val == 0)) ||
1724 ((u8GopNum == E_GOP2) && (mux_val == 1)) ||
1725 ((u8GopNum == E_GOP4) && (mux_val == 2)))
1726 {
1727 *corr_mux = (Gop_MuxSel)i;
1728 return TRUE;
1729 }
1730 }
1731 return FALSE;
1732 }
1733
HAL_GOP_SetGOPEnable2Mode1(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_U8 gopNum,MS_BOOL bEnable)1734 GOP_Result HAL_GOP_SetGOPEnable2Mode1(GOP_CTX_HAL_LOCAL *pGOPHalLocal, MS_U8 gopNum, MS_BOOL bEnable)
1735 {
1736 /* GOP OP Path enable to SC Setting
1737 A5: GOP OP Path blending with SC sequence
1738 mux1-->mux0-->mux2-->mux3
1739 */
1740 MS_U16 muxValue=0, regval=0;
1741 MS_U8 u8_mainGop = INVAILD_GOP_NUM, u8_combinedGop = INVAILD_GOP_NUM;
1742
1743 HAL_GOP_Read16Reg(pGOPHalLocal, GOP_MUX, &muxValue);
1744 HAL_GOP_Read16Reg(pGOPHalLocal, GOP_SC_GOPENMODE1, ®val);
1745 if (gopNum== (muxValue & GOP_MUX0_MASK)) //enable mux0 to SC
1746 {
1747 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_SC_GOPENMODE1, bEnable?(regval |GOP_BIT4):(regval & ~GOP_BIT4), GOP_BIT4|GOP_BIT5);
1748 }
1749 else if (gopNum== ((muxValue & GOP_MUX1_MASK)>>(GOP_MUX_SHIFT*1))) //enable mux1
1750 {
1751 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_SC_GOPENMODE1, bEnable?(regval |GOP_BIT6):(regval & ~GOP_BIT6), GOP_BIT6|GOP_BIT7);
1752 }
1753 else if (gopNum== ((muxValue & GOP_MUX2_MASK)>>(GOP_MUX_SHIFT*2))) //enable mux2
1754 {
1755 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_SC_GOPENMODE1, bEnable?(regval |GOP_BIT8):(regval & ~GOP_BIT8), GOP_BIT8|GOP_BIT9);
1756 }
1757 else if (gopNum== ((muxValue & GOP_MUX3_MASK)>>(GOP_MUX_SHIFT*3))) //enable mux3
1758 {
1759 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_SC_GOPENMODE1, bEnable?(regval |GOP_BIT12):(regval & ~GOP_BIT12), GOP_BIT12|GOP_BIT13);
1760 }
1761 else if (gopNum== ((muxValue & GOP_MUX4_MASK)>> (GOP_MUX_SHIFT*4))) //enable mux4
1762 {
1763 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_SC_GOPENMODE1, bEnable?(regval |GOP_BIT14):(regval & ~GOP_BIT14), GOP_BIT14|GOP_BIT15);
1764 }
1765 else
1766 {
1767 return GOP_FAIL;
1768 }
1769
1770 if( TRUE == Hal_get4K120CombinedGOP(pGOPHalLocal, gopNum, &u8_mainGop, &u8_combinedGop) )
1771 {
1772 if (pGOPHalLocal->pHALShared->GOP_Dst[u8_mainGop] == E_DRV_GOP_DST_OP_DUAL_RATE)
1773 {
1774 MS_U16 mux4mainGop;
1775 MS_U16 mux4combinedGop;
1776 Gop_MuxSel mux_value = E_GOP_MUX_INVAILD;
1777 MS_U32 reg_num = 0x0;
1778
1779 mux4mainGop = _findMuxNumberByGOP(pGOPHalLocal, pGOPHalLocal->pHALShared->GOP_Dst[u8_mainGop], u8_mainGop);
1780 mux4combinedGop = _findMuxNumberByGOP(pGOPHalLocal, pGOPHalLocal->pHALShared->GOP_Dst[u8_mainGop], u8_combinedGop);
1781
1782 if ((mux4mainGop == INVALID_GOP_MUX_VAL) || (mux4combinedGop == INVALID_GOP_MUX_VAL))
1783 {
1784 return GOP_FAIL;
1785 }
1786
1787 if (_IsGopInDualOpMux(pGOPHalLocal, mux4mainGop, &mux_value) == TRUE)
1788 {
1789 if (mux_value == 0)
1790 {
1791 reg_num = GOP_SC_4K120_EN0;
1792 }
1793 else if (mux_value == 1)
1794 {
1795 reg_num = GOP_SC_4K120_EN1;
1796 }
1797 else if (mux_value == 2)
1798 {
1799 reg_num = GOP_SC_4K120_EN2;
1800 }
1801
1802 HAL_GOP_Write16Reg(pGOPHalLocal, reg_num, (bEnable == TRUE) ? GOP_BIT10 : ~GOP_BIT10, GOP_BIT10);
1803 }
1804 }
1805 }
1806
1807 return GOP_SUCCESS;
1808 }
1809
HAL_GOP_GetGOPAlphaMode1(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_U8 gopNum,MS_BOOL * pbEnable)1810 GOP_Result HAL_GOP_GetGOPAlphaMode1(GOP_CTX_HAL_LOCAL *pGOPHalLocal, MS_U8 gopNum, MS_BOOL *pbEnable)
1811 {
1812 MS_U16 muxValue=0, regval=0;
1813 MS_U8 u8_mainGop = INVAILD_GOP_NUM, u8_combinedGop = INVAILD_GOP_NUM;
1814
1815 if( FALSE == Hal_get4K120CombinedGOP(pGOPHalLocal, gopNum, &u8_mainGop, &u8_combinedGop) )
1816 {
1817 GOP_H_ERR("Skipped [%s] Line %d !!", __FUNCTION__, __LINE__);
1818 return GOP_FAIL;
1819 }
1820
1821 if (pGOPHalLocal->pHALShared->GOP_Dst[u8_mainGop] == E_DRV_GOP_DST_OP_DUAL_RATE)
1822 {
1823 gopNum = u8_mainGop;
1824 }
1825
1826 HAL_GOP_Read16Reg(pGOPHalLocal, GOP_MUX, &muxValue);
1827 HAL_GOP_Read16Reg(pGOPHalLocal, GOP_SC_GOPENMODE1, ®val);
1828 if (gopNum== (muxValue & GOP_MUX0_MASK)) //enable mux0 to SC
1829 {
1830 *pbEnable = (regval & GOP_BIT4) == GOP_BIT4;
1831 }
1832 else if (gopNum== ((muxValue & GOP_MUX1_MASK)>>(GOP_MUX_SHIFT*1))) //enable mux1
1833 {
1834 *pbEnable = (regval & GOP_BIT6) == GOP_BIT6;
1835 }
1836 else if (gopNum== ((muxValue & GOP_MUX2_MASK)>>(GOP_MUX_SHIFT*2))) //enable mux2
1837 {
1838 *pbEnable = (regval & GOP_BIT8) == GOP_BIT8;
1839 }
1840 else if (gopNum== ((muxValue & GOP_MUX3_MASK)>>(GOP_MUX_SHIFT*3))) //enable mux3
1841 {
1842 *pbEnable = (regval & GOP_BIT12) == GOP_BIT12;
1843 }
1844 else if (gopNum== ((muxValue & GOP_MUX4_MASK)>> (GOP_MUX_SHIFT*4))) //enable mux4
1845 {
1846 *pbEnable = (regval & GOP_BIT14) == GOP_BIT14;
1847 }
1848 else
1849 {
1850 return GOP_FAIL;
1851 }
1852 return GOP_SUCCESS;
1853 }
1854
HAL_GOP_SetGOPHighPri(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_U8 gopNum)1855 GOP_Result HAL_GOP_SetGOPHighPri(GOP_CTX_HAL_LOCAL *pGOPHalLocal, MS_U8 gopNum)
1856 {
1857 /*T8
1858 OP path: support 4 mux (mux0, mux1, mux 2, mux3) to blend with SC simultaneously
1859 IP path: support mux0 and mux1 to IPMain/IPSub. Only one mux of mux0 and mux1 can be blended to IPMain/IPSub
1860 */
1861 MS_U16 Mux3Gop, muxValue=0, i;
1862 MS_U16 MuxShift;
1863
1864 MuxShift = GOP_MUX_SHIFT * E_GOP_MUX3;
1865
1866 HAL_GOP_Read16Reg(pGOPHalLocal, GOP_MUX, &muxValue);
1867 for (i=0; i<MAX_GOP_MUX;i++) //T8 4 mux
1868 {
1869 if (gopNum== ((muxValue&(GOP_REGMUX_MASK<<(i*GOP_MUX_SHIFT)))>>(i*GOP_MUX_SHIFT)))
1870 {
1871 Mux3Gop = (muxValue&GOP_MUX3_MASK)>> MuxShift; //save mux2 gop
1872
1873 muxValue &= ~GOP_MUX3_MASK; //clear mux2 setting
1874 muxValue &= ~(GOP_REGMUX_MASK<<(i*GOP_MUX_SHIFT)); //clear current mux setting
1875 muxValue |= ((gopNum<< MuxShift)|(Mux3Gop<<(i*GOP_MUX_SHIFT)));
1876 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_MUX, muxValue, GOP_REG_WORD_MASK);
1877 break;
1878 }
1879 }
1880 return GOP_SUCCESS;
1881 }
1882
HAL_GOP_SetGOPClk(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_U8 gopNum,DRV_GOPDstType eDstType)1883 GOP_Result HAL_GOP_SetGOPClk(GOP_CTX_HAL_LOCAL *pGOPHalLocal, MS_U8 gopNum, DRV_GOPDstType eDstType)
1884 {
1885 /*T8 GOP dst type:
1886 0: IP (Main)
1887 1: IP (Sub)
1888 2: OP
1889 3: MVOP
1890 */
1891
1892 /* Monaco clkgen setting */
1893 /******************
1894 0: odclk
1895 1: idclk_f2 (ipm)
1896 2: idclk_f1 (ips)
1897 3: ocmixer
1898 4: ve
1899 5 : mvop main
1900 6 : mvop sub
1901 ******************/
1902
1903 switch(eDstType)
1904 {
1905 case E_DRV_GOP_DST_IP0:
1906
1907 if (gopNum==E_GOP1)
1908 {
1909 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_GOPCLK, CKG_GOPG1_IDCLK2, CKG_GOPG1_MASK);
1910 }
1911 else if (gopNum ==E_GOP2)
1912 {
1913 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_GOP2CLK, CKG_GOPG2_IDCLK2, CKG_GOPG2_MASK);
1914 }
1915 else if (gopNum ==E_GOP3)
1916 {
1917 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_GOP3CLK, CKG_GOPG3_IDCLK2, CKG_GOPG3_MASK);
1918 }
1919 else if (gopNum ==E_GOP4)
1920 {
1921 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_GOP4CLK, CKG_GOPG4_IDCLK2, CKG_GOPG4_MASK);
1922 }
1923 else if (gopNum==E_GOP0)
1924 {
1925 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_GOPCLK, CKG_GOPG0_IDCLK2, CKG_GOPG0_MASK);
1926 }
1927 else
1928 {
1929 GOP_ASSERT(0);
1930 return GOP_INVALID_PARAMETERS;
1931 }
1932 break;
1933
1934 case E_DRV_GOP_DST_IP0_SUB:
1935 if (gopNum==E_GOP1)
1936 {
1937 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_GOPCLK, CKG_GOPG1_IDCLK1, CKG_GOPG1_MASK);
1938 }
1939 else if (gopNum==E_GOP2)
1940 {
1941 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_GOP2CLK, CKG_GOPG2_IDCLK1, CKG_GOPG2_MASK);
1942 }
1943 else if (gopNum==E_GOP3)
1944 {
1945 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_GOP3CLK, CKG_GOPG3_IDCLK1, CKG_GOPG3_MASK);
1946 }
1947 else if (gopNum ==E_GOP4)
1948 {
1949 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_GOP4CLK, CKG_GOPG4_IDCLK1, CKG_GOPG4_MASK);
1950 }
1951 else if (gopNum==E_GOP0)
1952 {
1953 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_GOPCLK, CKG_GOPG0_IDCLK1, CKG_GOPG0_MASK);
1954 }
1955 else
1956 {
1957 GOP_ASSERT(0);
1958 return GOP_INVALID_PARAMETERS;
1959 }
1960 break;
1961
1962
1963 case E_DRV_GOP_DST_OP0:
1964 if (gopNum==E_GOP1)
1965 {
1966 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_GOPCLK, CKG_GOPG1_ODCLK, CKG_GOPG1_MASK);
1967 }
1968 else if (gopNum==E_GOP2)
1969 {
1970 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_GOP2CLK, CKG_GOPG2_ODCLK, CKG_GOPG2_MASK);
1971 }
1972 else if (gopNum==E_GOP3)
1973 {
1974 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_GOP3CLK, CKG_GOPG3_ODCLK, CKG_GOPG3_MASK);
1975 }
1976 else if (gopNum ==E_GOP4)
1977 {
1978 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_GOP4CLK, CKG_GOPG4_ODCLK, CKG_GOPG4_MASK);
1979 }
1980 else if (gopNum==E_GOP0)
1981 {
1982 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_GOPCLK, CKG_GOPG0_ODCLK, CKG_GOPG0_MASK);
1983 }
1984 else
1985 {
1986 GOP_ASSERT(0);
1987 return GOP_INVALID_PARAMETERS;
1988 }
1989 break;
1990 case E_DRV_GOP_DST_DIP:
1991 if (gopNum==E_GOP1)
1992 {
1993 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_GOPCLK, CKG_GOPG1_FCLK, CKG_GOPG1_MASK);
1994 }
1995 else if (gopNum==E_GOP2)
1996 {
1997 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_GOP2CLK, CKG_GOPG2_FCLK, CKG_GOPG2_MASK);
1998 }
1999 else if (gopNum==E_GOP3)
2000 {
2001 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_GOP3CLK, CKG_GOPG3_FCLK, CKG_GOPG3_MASK);
2002 }
2003 else if (gopNum ==E_GOP4)
2004 {
2005 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_GOP4CLK, CKG_GOPG4_FCLK, CKG_GOPG4_MASK);
2006 }
2007 else if (gopNum==E_GOP0)
2008 {
2009 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_GOPCLK, CKG_GOPG0_FCLK, CKG_GOPG0_MASK);
2010 }
2011 else
2012 {
2013 GOP_ASSERT(0);
2014 return GOP_INVALID_PARAMETERS;
2015 }
2016
2017 break;
2018
2019 case E_DRV_GOP_DST_VOP:
2020 if (gopNum==E_GOP1)
2021 {
2022 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_GOPCLK, CKG_GOPG1_IDCLK2, CKG_GOPG1_MASK);
2023 }
2024 else if (gopNum ==E_GOP2)
2025 {
2026 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_GOPCLK, CKG_GOPG2_IDCLK2, CKG_GOPG2_MASK);
2027 }
2028 else if (gopNum ==E_GOP3)
2029 {
2030 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_GOPCLK, CKG_GOPG3_IDCLK2, CKG_GOPG3_MASK);
2031 }
2032 else if (gopNum ==E_GOP4)
2033 {
2034 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_GOP4CLK, CKG_GOPG4_IDCLK2, CKG_GOPG4_MASK);
2035 }
2036 else if (gopNum==E_GOP0)
2037 {
2038 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_GOPCLK, CKG_GOPG0_IDCLK2, CKG_GOPG0_MASK);
2039 }
2040 else
2041 {
2042 GOP_ASSERT(0);
2043 return GOP_INVALID_PARAMETERS;
2044 }
2045
2046 break;
2047 case E_DRV_GOP_DST_FRC:
2048 if (gopNum==E_GOP1)
2049 {
2050 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_GOPCLK, CKG_GOPG1_OCC_FRCCLK, CKG_GOPG1_MASK);
2051 }
2052 else if (gopNum==E_GOP0)
2053 {
2054 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_GOPCLK, CKG_GOPG0_OCC_FRCCLK, CKG_GOPG0_MASK);
2055 }
2056 else if (gopNum==E_GOP2)
2057 {
2058 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_GOP2CLK, CKG_GOPG2_OCC_FRCCLK, CKG_GOPG2_MASK);
2059 }
2060 else if (gopNum==E_GOP3)
2061 {
2062 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_GOP3CLK, CKG_GOPG3_OCC_FRCCLK, CKG_GOPG3_MASK);
2063 }
2064 else if (gopNum ==E_GOP4)
2065 {
2066 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_GOP4CLK, CKG_GOPG4_OCC_FRCCLK, CKG_GOPG4_MASK);
2067 }
2068 else
2069 {
2070 GOP_ASSERT(0);
2071 return GOP_INVALID_PARAMETERS;
2072 }
2073
2074 break;
2075
2076 case E_DRV_GOP_DST_MIXER2VE:
2077 //HAL_GOP_Write16Reg(pGOPHalLocal, CKG_GOPMIXER_CLK, CKG_GOPMIXER_VECLK, CKG_GOPMIXER_MASK);
2078
2079 if(gopNum == 0)
2080 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_GOPCLK, CKG_GOPG0_MIXERCLK_VE, CKG_GOPG0_MASK);
2081 else if(gopNum == 1)
2082 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_GOPCLK, CKG_GOPG1_MIXERCLK_VE, CKG_GOPG1_MASK);
2083 else if(gopNum == 2)
2084 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_GOP2CLK, CKG_GOPG2_MIXERCLK_VE, CKG_GOPG2_MASK);
2085 else if(gopNum == 3)
2086 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_GOP3CLK, CKG_GOPG3_MIXERCLK_VE, CKG_GOPG3_MASK);
2087 else if(gopNum == 4)
2088 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_GOP4CLK, CKG_GOPG4_MIXERCLK_VE, CKG_GOPG4_MASK);
2089
2090 break;
2091
2092 case E_DRV_GOP_DST_VE:
2093 if(gopNum == 0)
2094 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_GOPCLK, CKG_GOPG0_MIXERCLK_VE, CKG_GOPG0_MASK);
2095 else if(gopNum == 1)
2096 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_GOPCLK, CKG_GOPG1_MIXERCLK_VE, CKG_GOPG1_MASK);
2097 else if(gopNum == 2)
2098 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_GOP2CLK, CKG_GOPG2_MIXERCLK_VE, CKG_GOPG2_MASK);
2099 else if(gopNum == 3)
2100 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_GOP3CLK, CKG_GOPG3_MIXERCLK_VE, CKG_GOPG3_MASK);
2101 else if(gopNum == 4)
2102 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_GOP4CLK, CKG_GOPG4_MIXERCLK_VE, CKG_GOPG4_MASK);
2103 break;
2104 case E_DRV_GOP_DST_OP_DUAL_RATE:
2105 {
2106 MS_U8 u8_mainGop=0, u8_combinedGop=0;
2107
2108 Hal_get4K120CombinedGOP(pGOPHalLocal, gopNum, &u8_mainGop, &u8_combinedGop);
2109 if (u8_mainGop == E_GOP0)
2110 {
2111 // for GOP0+GOP3
2112 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_GOPCLK, CKG_GOPG0_ODCLK, CKG_GOPG0_MASK);
2113 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_GOP3CLK, CKG_GOPG3_ODCLK, CKG_GOPG3_MASK);
2114 }
2115 else if (u8_mainGop == E_GOP2)
2116 {
2117 // for GOP1+GOOP2
2118 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_GOP2CLK, CKG_GOPG2_ODCLK, CKG_GOPG2_MASK);
2119 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_GOPCLK, CKG_GOPG1_ODCLK, CKG_GOPG1_MASK);
2120 }
2121 else if (u8_mainGop == E_GOP4)
2122 {
2123 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_GOP4CLK, CKG_GOPG4_ODCLK, CKG_GOPG4_MASK);
2124 }
2125 }
2126 break;
2127 default:
2128 GOP_ASSERT(0);
2129 return GOP_ENUM_NOT_SUPPORTED;
2130 }
2131 HAL_GOP_Read16Reg(pGOPHalLocal, GOP_GOPCLK, &pGOPHalLocal->u16Clk0Setting); //Backup current GOPG clock settings
2132 HAL_GOP_Read16Reg(pGOPHalLocal, GOP_SRAMCLK,&pGOPHalLocal->u16Clk2Setting); //Backup current SRAM clock settings
2133
2134 return GOP_SUCCESS;
2135 }
2136
2137
HAL_GOP_SetClkForCapture(GOP_CTX_HAL_LOCAL * pGOPHalLocal,DRV_GOP_DWIN_SRC_SEL enSrcSel)2138 GOP_Result HAL_GOP_SetClkForCapture(GOP_CTX_HAL_LOCAL *pGOPHalLocal, DRV_GOP_DWIN_SRC_SEL enSrcSel)
2139 {
2140 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_GOP2CLK, 0, GOP_BIT8);
2141 if (enSrcSel==GOP_DRV_DWIN_SRC_OP)
2142 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_GOP2CLK, CKG_GOPD_CLK_ODCLK, CKG_GOPD_MASK);
2143 else if (enSrcSel==GOP_DRV_DWIN_SRC_MVOP)
2144 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_GOP2CLK, CKG_GOPD_CLK_DC0CLK, CKG_GOPD_MASK);
2145 else if (enSrcSel==GOP_DRV_DWIN_SRC_IP)
2146 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_GOP2CLK, CKG_GOPD_CLK_IDCLK2, CKG_GOPD_MASK);
2147 else
2148 return GOP_INVALID_PARAMETERS;
2149
2150 HAL_GOP_Read16Reg(pGOPHalLocal, GOP_GOP2CLK, &pGOPHalLocal->u16Clk1Setting); //Backup current GOPD clock settings
2151 return GOP_SUCCESS;
2152 }
HAL_GOP_SetClock(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_BOOL bEnable)2153 GOP_Result HAL_GOP_SetClock(GOP_CTX_HAL_LOCAL *pGOPHalLocal,MS_BOOL bEnable)
2154 {
2155 if (bEnable)
2156 {
2157 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_GOPCLK, pGOPHalLocal->u16Clk0Setting, GOP_REG_WORD_MASK);
2158 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_GOP2CLK, pGOPHalLocal->u16Clk1Setting, GOP_REG_WORD_MASK);
2159 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_SRAMCLK, pGOPHalLocal->u16Clk2Setting, GOP_REG_WORD_MASK);
2160 }
2161 else
2162 {
2163 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_GOPCLK, CKG_GOPG0_DISABLE_CLK, CKG_GOPG0_MASK);
2164 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_GOPCLK, CKG_GOPG1_DISABLE_CLK, CKG_GOPG1_MASK);
2165 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_GOP2CLK, CKG_GOPG2_DISABLE_CLK, CKG_GOPG2_MASK);
2166 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_GOP2CLK, CKG_GOPD_DISABLE_CLK, CKG_GOPD_MASK);
2167 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_SRAMCLK, CKG_SRAM0_DISABLE_CLK, CKG_SRAM0_MASK);
2168 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_SRAMCLK, CKG_SRAM1_DISABLE_CLK, CKG_SRAM1_MASK);
2169 }
2170
2171 return GOP_SUCCESS;
2172 }
2173
HAL_GOP_MIXER_SetGOPEnable2Mixer(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_U8 gopNum,MS_BOOL bEnable)2174 GOP_Result HAL_GOP_MIXER_SetGOPEnable2Mixer(GOP_CTX_HAL_LOCAL *pGOPHalLocal, MS_U8 gopNum, MS_BOOL bEnable)
2175 {
2176 return GOP_FUN_NOT_SUPPORTED;
2177 }
2178
HAL_GOP_MIXER_SetMux(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_U8 gopNum,MS_U8 muxNum,MS_BOOL bEnable)2179 GOP_Result HAL_GOP_MIXER_SetMux(GOP_CTX_HAL_LOCAL *pGOPHalLocal, MS_U8 gopNum, MS_U8 muxNum, MS_BOOL bEnable)
2180 {
2181 return GOP_FUN_NOT_SUPPORTED;
2182 }
2183
HAL_GOP_MIXER_EnableOldBlendMode(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_U8 u8GOP,MS_BOOL bEn)2184 GOP_Result HAL_GOP_MIXER_EnableOldBlendMode(GOP_CTX_HAL_LOCAL *pGOPHalLocal, MS_U8 u8GOP, MS_BOOL bEn)
2185 {
2186 return GOP_FUN_NOT_SUPPORTED;
2187 }
2188
HAL_GOP_Init_Context(GOP_CTX_HAL_LOCAL * pGOPHalLocal,GOP_CTX_HAL_SHARED * pHALShared,MS_BOOL bNeedInitShared)2189 void HAL_GOP_Init_Context(GOP_CTX_HAL_LOCAL *pGOPHalLocal, GOP_CTX_HAL_SHARED *pHALShared, MS_BOOL bNeedInitShared)
2190 {
2191 MS_U32 u32GopIdx;
2192
2193 memset(pGOPHalLocal, 0, sizeof(*pGOPHalLocal));
2194 pGOPHalLocal->pHALShared = pHALShared;
2195
2196 for(u32GopIdx=0; u32GopIdx<MAX_GOP_SUPPORT; u32GopIdx++)
2197 {
2198 pGOPHalLocal->drvGFlipGOPDst[u32GopIdx] = E_DRV_GOP_DST_OP0;
2199 }
2200 pGOPHalLocal->pGopChipPro = &g_GopChipPro;
2201 pGOPHalLocal->pbIsMuxVaildToGopDst = (MS_BOOL *)bIsMuxVaildToGopDst;
2202 }
HAL_GOP_Restore_Ctx(GOP_CTX_HAL_LOCAL * pGOPHalLocal)2203 void HAL_GOP_Restore_Ctx(GOP_CTX_HAL_LOCAL *pGOPHalLocal)
2204 {
2205 }
2206
HAL_ConvertAPIAddr(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_U8 gwinid,MS_PHY * u64Adr)2207 GOP_Result HAL_ConvertAPIAddr(GOP_CTX_HAL_LOCAL *pGOPHalLocal, MS_U8 gwinid, MS_PHY* u64Adr)
2208 {
2209 MS_U8 u8Miu=0xff;
2210 MS_U8 u8GOP=0;
2211
2212 if (gwinid<MAX_GOP0_GWIN) //gop0
2213 {
2214 u8GOP=0;
2215 }
2216 else if (gwinid>=MAX_GOP0_GWIN && gwinid<MAX_GOP0_GWIN+MAX_GOP1_GWIN) //gop1
2217 {
2218 u8GOP=1;
2219 }
2220 else if (gwinid==GOP2_GwinIdBase) //gop2
2221 {
2222 u8GOP=2;
2223 }
2224 else if (gwinid==GOP3_GwinIdBase) //gop3
2225 {
2226 u8GOP=3;
2227 }
2228 else if (gwinid==GOP4_GwinIdBase) //gop4
2229 {
2230 u8GOP=4;
2231 }
2232 else
2233 {
2234 return GOP_FAIL;
2235 }
2236
2237 u8Miu = HAL_GOP_GetMIUDst(pGOPHalLocal, u8GOP);
2238
2239 if (u8Miu <= 2)
2240 {
2241 _miu_offset_to_phy(u8Miu, *u64Adr, *u64Adr);
2242 }
2243 else
2244 {
2245 GOP_H_ERR("[%s] ERROR GOP miu client\n",__FUNCTION__);
2246 return GOP_FAIL;
2247 }
2248 return GOP_SUCCESS;
2249 }
2250
HAL_GOP_GetMIUDst(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_U8 gopnum)2251 MS_U8 HAL_GOP_GetMIUDst(GOP_CTX_HAL_LOCAL *pGOPHalLocal, MS_U8 gopnum)
2252 {
2253 MS_U8 u8Miu=0xff;
2254 MS_U16 u16RegVal_L=0;
2255 MS_U32 u32BnkOfst=0xFFFF;
2256 #ifdef GOP_MIU_GROUP2
2257 MS_U16 u16RegVal_H=0;
2258 #endif
2259
2260 if(pGOPHalLocal->pGopChipPro->bInternalMIUSelect[gopnum]==TRUE)
2261 {
2262 _GetBnkOfstByGop(gopnum, &u32BnkOfst);
2263 HAL_GOP_Read16Reg(pGOPHalLocal, u32BnkOfst+GOP_4G_MIU_SEL, &u16RegVal_L);
2264
2265 u8Miu= u16RegVal_L&(GOP_BIT1|GOP_BIT0) ;
2266 }
2267 else
2268 {
2269 HAL_GOP_Read16Reg(pGOPHalLocal, GOP_SC_MIU_SEL, &u16RegVal_L);
2270
2271 #ifdef GOP_MIU_GROUP2
2272 HAL_GOP_Read16Reg(pGOPHalLocal, GOP_MIU_GROUP2, &u16RegVal_H);
2273 #endif
2274 switch (gopnum)
2275 {
2276 case 0:
2277 u16RegVal_L &= BIT(GOP_MIU_CLIENT_GOP0);
2278 #ifdef GOP_MIU_GROUP2
2279 u16RegVal_H &= BIT(GOP_MIU_CLIENT_GOP0);
2280 u8Miu = (u16RegVal_L>>GOP_MIU_CLIENT_GOP0) | (u16RegVal_H>>GOP_MIU_CLIENT_GOP0)<<1;
2281 #else
2282 u8Miu = (u16RegVal_L>>GOP_MIU_CLIENT_GOP0);
2283 #endif
2284 break;
2285 case 1:
2286 u16RegVal_L &= BIT(GOP_MIU_CLIENT_GOP1);
2287 #ifdef GOP_MIU_GROUP2
2288 u16RegVal_H &= BIT(GOP_MIU_CLIENT_GOP1);
2289 u8Miu = (u16RegVal_L>>GOP_MIU_CLIENT_GOP1) | (u16RegVal_H>>GOP_MIU_CLIENT_GOP1)<<1;
2290 #else
2291 u8Miu = (u16RegVal_L>>GOP_MIU_CLIENT_GOP1);
2292 #endif
2293 break;
2294
2295 case 2:
2296 u16RegVal_L &= BIT(GOP_MIU_CLIENT_GOP2);
2297 #ifdef GOP_MIU_GROUP2
2298 u16RegVal_H &= BIT(GOP_MIU_CLIENT_GOP2);
2299 u8Miu = (u16RegVal_L>>GOP_MIU_CLIENT_GOP2) | (u16RegVal_H>>GOP_MIU_CLIENT_GOP2)<<1;
2300 #else
2301 u8Miu = (u16RegVal_L>>GOP_MIU_CLIENT_GOP2);
2302 #endif
2303 break;
2304
2305 case 3:
2306 u16RegVal_L &= BIT(GOP_MIU_CLIENT_GOP3);
2307 #ifdef GOP_MIU_GROUP2
2308 u16RegVal_H &= BIT(GOP_MIU_CLIENT_GOP3);
2309 u8Miu = (u16RegVal_L>>GOP_MIU_CLIENT_GOP3) | (u16RegVal_H>>GOP_MIU_CLIENT_GOP3)<<1;
2310 #else
2311 u8Miu = (u16RegVal_L>>GOP_MIU_CLIENT_GOP3);
2312 #endif
2313 break;
2314 case 4:
2315 u16RegVal_L &= BIT(GOP_MIU_CLIENT_GOP4);
2316 #ifdef GOP_MIU_GROUP2
2317 u16RegVal_H &= BIT(GOP_MIU_CLIENT_GOP4);
2318 u8Miu = (u16RegVal_L>>GOP_MIU_CLIENT_GOP4) | (u16RegVal_H>>GOP_MIU_CLIENT_GOP4)<<1;
2319 #else
2320 u8Miu = (u16RegVal_L>>GOP_MIU_CLIENT_GOP4);
2321 #endif
2322 break;
2323 default:
2324 return 0xff;
2325 break;
2326 }
2327
2328 if(u8Miu > MAX_GOP_MIUSEL )
2329 {
2330 GOP_H_ERR("[%s] ERROR GOP miu client\n",__FUNCTION__);
2331 return 0xff;
2332 }
2333
2334 }
2335 return u8Miu;
2336 }
HAL_GOP_GetGOPDst(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_U8 u8gopNum,DRV_GOPDstType * pGopDst)2337 GOP_Result HAL_GOP_GetGOPDst(GOP_CTX_HAL_LOCAL *pGOPHalLocal, MS_U8 u8gopNum, DRV_GOPDstType *pGopDst)
2338 {
2339 MS_U16 u16Regval;
2340 MS_U32 u32pBankOffSet=0;
2341 GOP_Result ret;
2342
2343 _GetBnkOfstByGop(u8gopNum, &u32pBankOffSet);
2344 HAL_GOP_Read16Reg(pGOPHalLocal, u32pBankOffSet + GOP_4G_CTRL1, &u16Regval);
2345
2346 switch (u16Regval&GOP_DST_MASK)
2347 {
2348 case 0:
2349 *pGopDst = E_DRV_GOP_DST_IP0;
2350 ret = GOP_SUCCESS;
2351 break;
2352 case 1:
2353 *pGopDst = E_DRV_GOP_DST_IP0_SUB;
2354 ret = GOP_SUCCESS;
2355 break;
2356 case 2:
2357 *pGopDst = E_DRV_GOP_DST_OP0;
2358 ret = GOP_SUCCESS;
2359 break;
2360 case 3:
2361 *pGopDst = E_DRV_GOP_DST_VOP;
2362 ret = GOP_SUCCESS;
2363 break;
2364 case 4:
2365 *pGopDst = E_DRV_GOP_DST_VOP_SUB;
2366 ret = GOP_SUCCESS;
2367 break;
2368 case 6:
2369 *pGopDst = E_DRV_GOP_DST_FRC;
2370 ret = GOP_SUCCESS;
2371 break;
2372 case 0xB:
2373 *pGopDst = E_DRV_GOP_DST_OP_DUAL_RATE;
2374 ret = GOP_SUCCESS;
2375 break;
2376 case 8:
2377 *pGopDst = E_DRV_GOP_DST_DIP;
2378 ret = GOP_SUCCESS;
2379 break;
2380 default:
2381 *pGopDst = E_DRV_GOP_DST_INVALID;
2382 ret = GOP_FAIL;
2383 break;
2384 }
2385
2386 return ret;
2387
2388 }
2389
HAL_GOP_SetIPSel2SC(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_IPSEL_GOP ipSelGop)2390 void HAL_GOP_SetIPSel2SC(GOP_CTX_HAL_LOCAL *pGOPHalLocal, MS_IPSEL_GOP ipSelGop)
2391 {
2392 MS_U16 muxValue=0;
2393 MS_U16 u16RegVal= 0, u16RegMsk = 0;
2394
2395 HAL_GOP_Read16Reg(pGOPHalLocal, GOP_MUX_IPVOP, &muxValue);
2396
2397 /*
2398 mustang IP blending
2399 [15:8] IP Main blending
2400 [7:0] IP Sub blending
2401 ===========================================
2402 [10:8]/[2:0] No use
2403 [11]/[3] 0: Enable IP blending
2404 1: Disable IP blending
2405 [13:12]/[5:4] 2'b01 : Select GOP ips mux as source
2406 2'b10 : Select GOP ipm mux as source
2407 [15:14]/[7:6] 2'b00, 2'b01 : Select SUB timing for GOP
2408 2'b10, 2'b11 : Select Main timing for GOP
2409 */
2410 switch(ipSelGop)
2411 {
2412 case MS_DRV_IP0_SEL_GOP0:
2413 u16RegVal = GOP_BIT15 ;
2414 if(E_GOP0 == (muxValue &GOP_MUX0_MASK))
2415 u16RegVal |= IPMUX0_BLENDING_ENABLE;//mux0
2416 else
2417 u16RegVal |= IPMUX1_BLENDING_ENABLE;//mux1
2418 u16RegVal |= GOP_BIT3; //Disable Sub IP blending
2419 u16RegMsk = GOP_REG_WORD_MASK;
2420 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_SC1_CHANNELSYNC, GOP_BIT11, GOP_BIT11);
2421 break;
2422 case MS_DRV_IP0_SEL_GOP1:
2423 u16RegVal = GOP_BIT15 ;
2424 if(E_GOP1 == (muxValue &GOP_MUX0_MASK))
2425 u16RegVal |= IPMUX0_BLENDING_ENABLE;//mux0
2426 else
2427 u16RegVal |= IPMUX1_BLENDING_ENABLE;//mux1
2428 u16RegVal |= GOP_BIT3; //Disable Sub IP blending
2429 u16RegMsk = GOP_REG_WORD_MASK;
2430 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_SC1_CHANNELSYNC, GOP_BIT11, GOP_BIT11);
2431 break;
2432 case MS_DRV_IP0_SEL_GOP2:
2433 u16RegVal = GOP_BIT15 ;
2434 if(E_GOP2 == (muxValue &GOP_MUX0_MASK))
2435 u16RegVal |= IPMUX0_BLENDING_ENABLE;//mux0
2436 else
2437 u16RegVal |= IPMUX1_BLENDING_ENABLE;//mux1
2438 u16RegVal |= GOP_BIT3; //Disable Sub IP blending
2439 u16RegMsk = GOP_REG_WORD_MASK;
2440 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_SC1_CHANNELSYNC, GOP_BIT11, GOP_BIT11);
2441 break;
2442 case MS_DRV_NIP_SEL_GOP0:
2443 if(E_GOP0 == (muxValue &GOP_MUX0_MASK))
2444 {
2445 u16RegVal = ~IPMUX0_BLENDING_ENABLE;//mux0
2446 u16RegMsk = IPMUX0_BLENDING_ENABLE;
2447 }
2448 else
2449 {
2450 u16RegVal = ~IPMUX1_BLENDING_ENABLE;//mux1
2451 u16RegMsk = IPMUX1_BLENDING_ENABLE;
2452 }
2453 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_SC_CHANNELSYNC, GOP_BIT11, GOP_BIT11);
2454 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_SC1_CHANNELSYNC, GOP_BIT11, GOP_BIT11);
2455 break;
2456 case MS_DRV_NIP_SEL_GOP1:
2457 if(E_GOP1 == (muxValue &GOP_MUX0_MASK))
2458 {
2459 u16RegVal = ~IPMUX0_BLENDING_ENABLE;//mux0
2460 u16RegMsk = IPMUX0_BLENDING_ENABLE;
2461 }
2462 else
2463 {
2464 u16RegVal = ~IPMUX1_BLENDING_ENABLE;//mux1
2465 u16RegMsk = IPMUX1_BLENDING_ENABLE;
2466 }
2467 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_SC_CHANNELSYNC, GOP_BIT11, GOP_BIT11);
2468 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_SC1_CHANNELSYNC, GOP_BIT11, GOP_BIT11);
2469 break;
2470 case MS_DRV_NIP_SEL_GOP2:
2471 if(E_GOP2 == (muxValue &GOP_MUX0_MASK))
2472 {
2473 u16RegVal = ~IPMUX0_BLENDING_ENABLE;//mux0
2474 u16RegMsk = IPMUX0_BLENDING_ENABLE;
2475 }
2476 else
2477 {
2478 u16RegVal = ~IPMUX1_BLENDING_ENABLE;//mux1
2479 u16RegMsk = IPMUX1_BLENDING_ENABLE;
2480 }
2481 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_SC_CHANNELSYNC, GOP_BIT11, GOP_BIT11);
2482 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_SC1_CHANNELSYNC, GOP_BIT11, GOP_BIT11);
2483 break;
2484 case MS_DRV_MVOP_SEL:
2485 u16RegVal = GOP_BIT15 ;
2486 u16RegVal |= IPMUX0_BLENDING_ENABLE; //mux0
2487 u16RegVal |= GOP_BIT3; //Disable Sub IP blending
2488 u16RegMsk = GOP_REG_WORD_MASK;
2489 break;
2490 default:
2491 GOP_H_ERR("[%s] ERROR invalid source select\n",__FUNCTION__);
2492 break;
2493 }
2494 if(0 != u16RegMsk)
2495 {
2496 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_SC_CHANNELSYNC, u16RegVal, u16RegMsk);
2497 }
2498 }
2499
2500
HAL_GOP_DWIN_SetSourceSel(GOP_CTX_HAL_LOCAL * pGOPHalLocal,DRV_GOP_DWIN_SRC_SEL enSrcSel)2501 GOP_Result HAL_GOP_DWIN_SetSourceSel(GOP_CTX_HAL_LOCAL *pGOPHalLocal, DRV_GOP_DWIN_SRC_SEL enSrcSel)
2502 {
2503 return GOP_FUN_NOT_SUPPORTED;
2504 }
2505
2506
HAL_GOP_GetDWINMIU(GOP_CTX_HAL_LOCAL * pGOPHalLocal)2507 MS_U8 HAL_GOP_GetDWINMIU(GOP_CTX_HAL_LOCAL *pGOPHalLocal)
2508 {
2509 return GOP_FUN_NOT_SUPPORTED;
2510 }
HAL_GOP_SetDWINMIU(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_U8 miu)2511 GOP_Result HAL_GOP_SetDWINMIU(GOP_CTX_HAL_LOCAL *pGOPHalLocal, MS_U8 miu)
2512 {
2513 return GOP_FUN_NOT_SUPPORTED;
2514 }
2515
HAL_GOP_DWIN_EnableR2YCSC(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_BOOL bEnable)2516 GOP_Result HAL_GOP_DWIN_EnableR2YCSC(GOP_CTX_HAL_LOCAL *pGOPHalLocal, MS_BOOL bEnable)
2517 {
2518 return GOP_FUN_NOT_SUPPORTED;
2519 }
2520
HAL_GOP_VE_SetOutputTiming(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_U32 u32mode)2521 GOP_Result HAL_GOP_VE_SetOutputTiming(GOP_CTX_HAL_LOCAL *pGOPHalLocal, MS_U32 u32mode)
2522 {
2523 return GOP_FUN_NOT_SUPPORTED;
2524 }
2525
HAL_GOP_MIXER_SetOutputTiming(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_U32 u32mode,GOP_DRV_MixerTiming * pTM)2526 GOP_Result HAL_GOP_MIXER_SetOutputTiming(GOP_CTX_HAL_LOCAL *pGOPHalLocal, MS_U32 u32mode, GOP_DRV_MixerTiming *pTM)
2527 {
2528 return GOP_FUN_NOT_SUPPORTED;
2529 }
2530
HAL_GOP_MIXER_EnableVfilter(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_BOOL bEn)2531 GOP_Result HAL_GOP_MIXER_EnableVfilter(GOP_CTX_HAL_LOCAL *pGOPHalLocal, MS_BOOL bEn)
2532 {
2533 return GOP_FUN_NOT_SUPPORTED;
2534 }
2535
HAL_GOP_GWIN_EnableTileMode(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_U8 u8win,MS_BOOL bEnable,E_GOP_TILE_DATA_TYPE tilemode)2536 GOP_Result HAL_GOP_GWIN_EnableTileMode(GOP_CTX_HAL_LOCAL *pGOPHalLocal, MS_U8 u8win, MS_BOOL bEnable, E_GOP_TILE_DATA_TYPE tilemode)
2537 {
2538 return GOP_FUN_NOT_SUPPORTED;
2539 }
2540
2541
HAL_GOP_SetUVSwap(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_U8 u8GOPNum,MS_BOOL bEn)2542 GOP_Result HAL_GOP_SetUVSwap(GOP_CTX_HAL_LOCAL *pGOPHalLocal, MS_U8 u8GOPNum,MS_BOOL bEn)
2543 {
2544 MS_U32 u32BankOffSet =0;
2545
2546 _GetBnkOfstByGop(u8GOPNum, &u32BankOffSet);
2547
2548 if (bEn)
2549 HAL_GOP_Write16Reg(pGOPHalLocal, u32BankOffSet+GOP_4G_YUV_SWAP, GOP_BIT14, GOP_BIT14);
2550 else
2551 HAL_GOP_Write16Reg(pGOPHalLocal, u32BankOffSet+GOP_4G_YUV_SWAP, ~GOP_BIT14, GOP_BIT14);
2552
2553 return GOP_SUCCESS;
2554 }
2555
HAL_GOP_SetYCSwap(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_U8 u8GOPNum,MS_BOOL bEn)2556 GOP_Result HAL_GOP_SetYCSwap(GOP_CTX_HAL_LOCAL *pGOPHalLocal, MS_U8 u8GOPNum,MS_BOOL bEn)
2557 {
2558 MS_U32 u32BankOffSet =0;
2559
2560 _GetBnkOfstByGop(u8GOPNum, &u32BankOffSet);
2561
2562 if (bEn)
2563 HAL_GOP_Write16Reg(pGOPHalLocal, u32BankOffSet+GOP_4G_YUV_SWAP, GOP_BIT15, GOP_BIT15);
2564 else
2565 HAL_GOP_Write16Reg(pGOPHalLocal, u32BankOffSet+GOP_4G_YUV_SWAP, 0x0, GOP_BIT15);
2566
2567 return GOP_SUCCESS;
2568 }
2569
HAL_GOP_GWIN_GetNewAlphaMode(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_U8 u8win,MS_BOOL * pEnable)2570 GOP_Result HAL_GOP_GWIN_GetNewAlphaMode(GOP_CTX_HAL_LOCAL *pGOPHalLocal, MS_U8 u8win, MS_BOOL* pEnable)
2571 {
2572 MS_U16 u16Val =0x0;
2573 if (u8win < GOP1_GwinIdBase)
2574 {
2575 HAL_GOP_Read16Reg(pGOPHalLocal, GOP_4G_GWIN_ALPHA01(u8win), &u16Val);
2576 *pEnable = (MS_BOOL)(u16Val>>15);
2577 }
2578 else if (u8win < GOP2_GwinIdBase)
2579 {
2580 HAL_GOP_Read16Reg(pGOPHalLocal, GOP_2G_GWIN_ALPHA01(u8win - MAX_GOP0_GWIN), &u16Val);
2581 *pEnable = (MS_BOOL)(u16Val>>15);
2582 }
2583 else if (u8win < GOP3_GwinIdBase)
2584 {
2585 HAL_GOP_Read16Reg(pGOPHalLocal, GOP_1G_GWIN_ALPHA01, &u16Val);
2586 *pEnable = (MS_BOOL)(u16Val>>15);
2587 }
2588 else if (u8win < GOP4_GwinIdBase)
2589 {
2590 HAL_GOP_Read16Reg(pGOPHalLocal, GOP_1GX_GWIN_ALPHA01, &u16Val);
2591 *pEnable = (MS_BOOL)(u16Val>>15);
2592 }
2593 else if (u8win < GOP5_GwinIdBase)
2594 {
2595 HAL_GOP_Read16Reg(pGOPHalLocal, GOP_1GS0_GWIN_ALPHA01, &u16Val);
2596 *pEnable = (MS_BOOL)(u16Val>>15);
2597 }
2598 else
2599 {
2600 GOP_H_ERR("%s Not support this GWIN num%d!!!\n",__FUNCTION__, u8win);
2601 return GOP_INVALID_PARAMETERS;
2602 }
2603
2604 return GOP_SUCCESS;
2605 }
2606
HAL_GOP_GWIN_SetNewAlphaMode(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_U8 u8win,MS_BOOL bEnable)2607 GOP_Result HAL_GOP_GWIN_SetNewAlphaMode(GOP_CTX_HAL_LOCAL *pGOPHalLocal, MS_U8 u8win, MS_BOOL bEnable)
2608 {
2609 MS_U16 u16Val = bEnable << 15;
2610 if (u8win < GOP1_GwinIdBase)
2611 {
2612 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_4G_GWIN_ALPHA01(u8win), u16Val, GOP_BIT15);
2613 }
2614 else if (u8win < GOP2_GwinIdBase)
2615 {
2616 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_2G_GWIN_ALPHA01(u8win - MAX_GOP0_GWIN), u16Val, GOP_BIT15);
2617 }
2618 else if (u8win < GOP3_GwinIdBase)
2619 {
2620 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_1G_GWIN_ALPHA01, u16Val, GOP_BIT15);
2621 }
2622 else if (u8win < GOP4_GwinIdBase)
2623 {
2624 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_1GX_GWIN_ALPHA01, u16Val, GOP_BIT15);
2625 }
2626 else if (u8win < GOP5_GwinIdBase)
2627 {
2628 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_1GS0_GWIN_ALPHA01, u16Val, GOP_BIT15);
2629 }
2630 else
2631 {
2632 GOP_H_ERR("%s Not support this GWIN num%d!!!\n",__FUNCTION__, u8win);
2633 return GOP_INVALID_PARAMETERS;
2634 }
2635 return GOP_SUCCESS;
2636 }
2637
HAL_GOP_GWiN_Set3DOSD_Sub(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_U8 u8GOP,MS_U8 u8Gwin,MS_PHY u32SubAddr)2638 GOP_Result HAL_GOP_GWiN_Set3DOSD_Sub(GOP_CTX_HAL_LOCAL *pGOPHalLocal,MS_U8 u8GOP ,MS_U8 u8Gwin, MS_PHY u32SubAddr)
2639 {
2640 MS_U16 u16Reg = 0;
2641 MS_U32 u32WordBase = 0;
2642 MS_U32 u32BankOffSet=0;
2643
2644 _GetBnkOfstByGop(u8GOP, &u32BankOffSet);
2645
2646 HAL_GOP_Read16Reg(pGOPHalLocal, u32BankOffSet + GOP_4G_BANK_FWR, &u16Reg);
2647
2648 if(u16Reg & GOP_BIT7)
2649 {
2650 u32WordBase = 1;
2651 }
2652 else
2653 {
2654 u32WordBase = GOP_WordUnit;
2655 }
2656
2657 u32SubAddr /= u32WordBase;
2658
2659 if(u8GOP == E_GOP2)
2660 {
2661 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_1G_3DOSD_SUB_RBLK_L, u32SubAddr&GOP_REG_WORD_MASK ,GOP_REG_WORD_MASK );
2662 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_1G_3DOSD_SUB_RBLK_H, u32SubAddr>>16 ,GOP_REG_WORD_MASK );
2663 }
2664 else if(u8GOP == E_GOP3)
2665 {
2666 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_1GX_3DOSD_SUB_RBLK_L, u32SubAddr&GOP_REG_WORD_MASK ,GOP_REG_WORD_MASK );
2667 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_1GX_3DOSD_SUB_RBLK_H, u32SubAddr>>16 ,GOP_REG_WORD_MASK );
2668
2669 }
2670 else if(u8GOP == E_GOP4)
2671 {
2672 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_1GS0_3DOSD_SUB_RBLK_L, u32SubAddr&GOP_REG_WORD_MASK ,GOP_REG_WORD_MASK );
2673 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_1GS0_3DOSD_SUB_RBLK_H, u32SubAddr>>16 ,GOP_REG_WORD_MASK );
2674 }
2675 else if(u8GOP == E_GOP1)
2676 {
2677 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_2G_3DOSD_SUB_RBLK_L(u8Gwin - MAX_GOP0_GWIN), u32SubAddr&GOP_REG_WORD_MASK ,GOP_REG_WORD_MASK );
2678 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_2G_3DOSD_SUB_RBLK_H(u8Gwin - MAX_GOP0_GWIN), u32SubAddr>>16 ,GOP_REG_WORD_MASK );
2679 }
2680 else //gop0
2681 {
2682 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_4G_3DOSD_SUB_RBLK_L(u8Gwin), u32SubAddr&GOP_REG_WORD_MASK ,GOP_REG_WORD_MASK );
2683 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_4G_3DOSD_SUB_RBLK_H(u8Gwin), u32SubAddr>>16 ,GOP_REG_WORD_MASK );
2684 }
2685
2686 return GOP_SUCCESS;
2687
2688 }
2689
2690 //------------------------------------------------------------------------------
2691 /// Set VE output with OSD
2692 /// @return none
2693 //------------------------------------------------------------------------------
HAL_GOP_VE_SetOSDEnable(MS_BOOL bEnable,EN_VE_OSD_ENABLE eOSD,MS_U8 gopNum)2694 GOP_Result HAL_GOP_VE_SetOSDEnable(MS_BOOL bEnable, EN_VE_OSD_ENABLE eOSD, MS_U8 gopNum)
2695 {
2696 #ifndef MSOS_TYPE_LINUX_KERNEL
2697 MS_U32 u32Reg = GOP_VE_TVS_OSD_EN;
2698 MS_U16 u16Val = BIT(2)|BIT(3);
2699
2700 if( EN_OSD_0 == eOSD)
2701 {
2702 u32Reg = GOP_VE_TVS_OSD_EN;
2703 }
2704 else if( EN_OSD_1 == eOSD)
2705 {
2706 u32Reg = GOP_VE_TVS_OSD1_EN;
2707 }
2708
2709 if(bEnable) // enable OSD
2710 {
2711 MApi_VE_W2BYTE_MSK(MS_VE_REG_BANK_3F, u32Reg, ~u16Val, u16Val);
2712 MApi_VE_W2BYTE_MSK(MS_VE_REG_BANK_3F, u32Reg, BIT(5), BIT(5));
2713 MApi_VE_W2BYTE_MSK(MS_VE_REG_BANK_3F, u32Reg, BIT(1), BIT(1));
2714 MApi_VE_W2BYTE_MSK(MS_VE_REG_BANK_3F, u32Reg, BIT(0), BIT(0));
2715 }
2716 else // disable OSD
2717 {
2718 MApi_VE_W2BYTE_MSK(MS_VE_REG_BANK_3F, u32Reg, 0x0, BIT(0));
2719 }
2720 #endif
2721 return GOP_SUCCESS;
2722 }
2723
HAL_GOP_SetGOPToVE(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_U8 gopNum,MS_BOOL bEn)2724 GOP_Result HAL_GOP_SetGOPToVE(GOP_CTX_HAL_LOCAL *pGOPHalLocal, MS_U8 gopNum, MS_BOOL bEn )
2725 {
2726 MS_U16 regval = 0x0;
2727
2728 HAL_GOP_Read16Reg(pGOPHalLocal, GOP_MUX4_MIX_VE, ®val);
2729 // there are only 2 mux, the 3rd gop will be set to 2nd mux(osd1).
2730 if((gopNum != (regval&(GOP_BIT6|GOP_BIT7|GOP_BIT8)>>6)) && (gopNum != ((regval&(GOP_BIT9|GOP_BIT10|GOP_BIT11))>>9)))
2731 {
2732 // if have to overwrite one, overwriting INIT VALUE is better.
2733 if (VE_MUX_INIT_VALUE == ((regval&(GOP_BIT6|GOP_BIT7|GOP_BIT8))>>6))
2734 {
2735 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_MUX4_MIX_VE, (gopNum<<6), (GOP_BIT6|GOP_BIT7|GOP_BIT8));
2736 HAL_GOP_VE_SetOSDEnable(bEn, EN_OSD_0, gopNum);
2737 }
2738 else
2739 {
2740 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_MUX4_MIX_VE, (gopNum<<9), (GOP_BIT9|GOP_BIT10|GOP_BIT11));
2741 HAL_GOP_VE_SetOSDEnable(bEn, EN_OSD_1, gopNum);
2742 }
2743 }
2744 else if(gopNum != ((regval&(GOP_BIT9|GOP_BIT10|GOP_BIT11))>>9))
2745 {
2746 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_MUX4_MIX_VE, (gopNum<<9), (GOP_BIT9|GOP_BIT10|GOP_BIT11));
2747 HAL_GOP_VE_SetOSDEnable(bEn, EN_OSD_1, gopNum);
2748 }
2749 else
2750 {
2751 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_MUX4_MIX_VE, (gopNum<<6) , (GOP_BIT6|GOP_BIT7|GOP_BIT8));
2752 HAL_GOP_VE_SetOSDEnable(bEn, EN_OSD_0, gopNum);
2753 }
2754 return GOP_SUCCESS;
2755
2756 }
2757
HAL_GOP_GetVideoTimingMirrorType(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_BOOL bHorizontal)2758 E_GOP_VIDEOTIMING_MIRRORTYPE HAL_GOP_GetVideoTimingMirrorType(GOP_CTX_HAL_LOCAL *pGOPHalLocal, MS_BOOL bHorizontal)
2759 {
2760 E_GOP_VIDEOTIMING_MIRRORTYPE enMirrorType = E_GOP_VIDEOTIMING_MIRROR_BYSCALER;
2761 MS_U16 u16MVOPMirrorCfg = 0;
2762 MS_U16 u16ScalerMirrorCfg = 0;
2763
2764 HAL_GOP_Read16Reg(pGOPHalLocal, GOP_MVOP_MIRRORCFG, &u16MVOPMirrorCfg);
2765 HAL_GOP_Read16Reg(pGOPHalLocal, GOP_SC_MIRRORCFG, &u16ScalerMirrorCfg);
2766 if(bHorizontal) // Horizontal
2767 {
2768 if(u16MVOPMirrorCfg & GOP_BIT1)
2769 {
2770 enMirrorType = E_GOP_VIDEOTIMING_MIRROR_BYMVOP;
2771 }
2772 else if(u16ScalerMirrorCfg & GOP_BIT12)
2773 {
2774 enMirrorType = E_GOP_VIDEOTIMING_MIRROR_BYSCALER;
2775 }
2776 }
2777 else //vertical
2778 {
2779 if(u16MVOPMirrorCfg & GOP_BIT0)
2780 {
2781 enMirrorType = E_GOP_VIDEOTIMING_MIRROR_BYMVOP;
2782 }
2783 else if(u16ScalerMirrorCfg & GOP_BIT13)
2784 {
2785 enMirrorType = E_GOP_VIDEOTIMING_MIRROR_BYSCALER;
2786 }
2787 }
2788 return enMirrorType;
2789 }
2790
HAL_GOP_3D_SetMiddle(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_U8 u8GOP,MS_U16 u16Middle)2791 GOP_Result HAL_GOP_3D_SetMiddle(GOP_CTX_HAL_LOCAL *pGOPHalLocal,MS_U8 u8GOP,MS_U16 u16Middle)
2792 {
2793 MS_U32 u32BankOffSet =0;
2794
2795 _GetBnkOfstByGop(u8GOP, &u32BankOffSet);
2796 HAL_GOP_Write16Reg(pGOPHalLocal,u32BankOffSet+GOP_4G_3D_MIDDLE, u16Middle, GOP_REG_WORD_MASK);
2797 return GOP_SUCCESS;
2798 }
2799
HAL_GOP_OC_SetOCEn(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_U8 u8GOP,MS_BOOL bOCEn)2800 GOP_Result HAL_GOP_OC_SetOCEn(GOP_CTX_HAL_LOCAL *pGOPHalLocal, MS_U8 u8GOP, MS_BOOL bOCEn)
2801 {
2802 MS_U8 i=0, eGopMux=0, FRCMuxOffset=0;
2803 MS_U16 u16Val=0;
2804 MS_U16 u16Mux[MAX_GOP_MUX];
2805
2806 HAL_GOP_Read16Reg(pGOPHalLocal, GOP_MUX, &u16Val);
2807 u16Mux[0] =( u16Val & GOP_MUX0_MASK);
2808 u16Mux[1] =( u16Val & GOP_MUX1_MASK) >> (GOP_MUX_SHIFT*1);
2809 u16Mux[2] =( u16Val & GOP_MUX2_MASK) >> (GOP_MUX_SHIFT*2);
2810 u16Mux[3] =( u16Val & GOP_MUX3_MASK) >> (GOP_MUX_SHIFT*3);
2811 u16Mux[4] =( u16Val & GOP_MUX4_MASK) >> (GOP_MUX_SHIFT*4);
2812
2813 switch(u8GOP)
2814 {
2815 case E_GOP0:
2816 case E_GOP1:
2817 case E_GOP2:
2818 case E_GOP3:
2819 case E_GOP4:
2820 for(i=0; i<MAX_GOP_MUX; i++)
2821 {
2822 if(u8GOP == u16Mux[i])
2823 {
2824 eGopMux = i;
2825 if(eGopMux == 4)
2826 {
2827 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_MUX_4K2K, bOCEn<<15, GOP_BIT15);
2828 }
2829 else
2830 {
2831 FRCMuxOffset = 12 + eGopMux;
2832 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_MUX_IPVOP, bOCEn<<FRCMuxOffset, 1<<FRCMuxOffset);
2833 }
2834 }
2835 }
2836 break;
2837 default:
2838 return GOP_FAIL;
2839 break;
2840 }
2841
2842 return GOP_SUCCESS;
2843 }
2844
HAL_GOP_OC_SetOCInfo(GOP_CTX_HAL_LOCAL * pGOPHalLocal,DRV_GOP_OC_INFO * pOCinfo)2845 GOP_Result HAL_GOP_OC_SetOCInfo(GOP_CTX_HAL_LOCAL *pGOPHalLocal, DRV_GOP_OC_INFO* pOCinfo)
2846 {
2847 return GOP_FUN_NOT_SUPPORTED;
2848 }
2849
HAL_GOP_OC_Get_MIU_Sel(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_U8 * MIUId)2850 GOP_Result HAL_GOP_OC_Get_MIU_Sel(GOP_CTX_HAL_LOCAL *pGOPHalLocal, MS_U8 *MIUId)
2851 {
2852 return GOP_FUN_NOT_SUPPORTED;
2853 }
2854
HAL_GOP_DWIN_SetRingBuffer(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_U32 u32RingSize,MS_U32 u32BufSize)2855 GOP_Result HAL_GOP_DWIN_SetRingBuffer(GOP_CTX_HAL_LOCAL *pGOPHalLocal, MS_U32 u32RingSize,MS_U32 u32BufSize)
2856 {
2857 return GOP_FUN_NOT_SUPPORTED;
2858 }
2859
HAL_GOP_AdjustField(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_U8 GopNum,DRV_GOPDstType eDstType)2860 GOP_Result HAL_GOP_AdjustField(GOP_CTX_HAL_LOCAL *pGOPHalLocal, MS_U8 GopNum, DRV_GOPDstType eDstType)
2861 {
2862 return GOP_FUN_NOT_SUPPORTED;
2863 }
2864
2865 /********************************************************************************/
2866 ///Test Pattern
2867 /********************************************************************************/
HAL_GOP_TestPattern_IsVaild(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_U8 u8GopNum)2868 GOP_Result HAL_GOP_TestPattern_IsVaild(GOP_CTX_HAL_LOCAL *pGOPHalLocal, MS_U8 u8GopNum)
2869 {
2870 if(u8GopNum == pGOPHalLocal->pGopChipPro->GOP_TestPattern_Vaild)
2871 {
2872 return GOP_SUCCESS;
2873 }
2874 else
2875 {
2876 return GOP_FAIL;
2877 }
2878
2879 }
2880
2881
2882 /********************************************************************************/
2883 ///GOP Scaling down (internal)
2884 /********************************************************************************/
2885
HAL_GOP_EnableScalingDownSram(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_U8 u8GOP,MS_BOOL bEn)2886 MS_BOOL HAL_GOP_EnableScalingDownSram(GOP_CTX_HAL_LOCAL *pGOPHalLocal,MS_U8 u8GOP,MS_BOOL bEn)
2887 {
2888 MS_U16 u16MG_mask=0;
2889 MS_U16 u16Val=0;
2890 MS_U16 u16LB_mask=0;
2891 MS_U16 u16enable=0;
2892
2893 if(u8GOP==0)
2894 {
2895 u16MG_mask=CKG_GOPG0_MG_MASK;
2896 u16Val=GOP_BIT2;
2897 u16LB_mask=CKG_LB_SRAM1_MASK;
2898 u16enable=GOP_BIT2;
2899 }
2900 else if(u8GOP==2)
2901 {
2902 u16MG_mask=CKG_GOPG2_MG_MASK;
2903 u16Val=GOP_BIT6;
2904 u16LB_mask=CKG_LB_SRAM2_MASK;
2905 u16enable=GOP_BIT6;
2906 }
2907 else
2908 {
2909 GOP_H_ERR("[%s] Error message GOP not support scaling down!!",__FUNCTION__);
2910 return GOP_FAIL;
2911 }
2912 if(bEn==TRUE)
2913 {
2914 HAL_GOP_Write16Reg(pGOPHalLocal, CKG_GOPG0_MG, u16Val, u16MG_mask);
2915 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_LB_SRAMCLK, u16enable, u16LB_mask);
2916 }
2917 else
2918 {
2919 HAL_GOP_Write16Reg(pGOPHalLocal, CKG_GOPG0_MG, 0, u16MG_mask);
2920 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_LB_SRAMCLK, 0, u16LB_mask);
2921 }
2922 return TRUE;
2923 }
2924
HAL_GOP_HScalingDown(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_U8 u8GOP,MS_BOOL bEnable,MS_U16 src,MS_U16 dst)2925 GOP_Result HAL_GOP_HScalingDown(GOP_CTX_HAL_LOCAL *pGOPHalLocal,MS_U8 u8GOP, MS_BOOL bEnable,MS_U16 src, MS_U16 dst)
2926 {
2927 MS_U32 ratio;
2928 MS_U32 u32BankOffSet=0xFFFF;
2929 MS_U16 u16VScalReg;
2930
2931 _GetBnkOfstByGop(u8GOP, &u32BankOffSet);
2932 if(bEnable ==TRUE)
2933 {
2934 HAL_GOP_Read16Reg(pGOPHalLocal, u32BankOffSet+GOP_4G_VSTRCH, &u16VScalReg);
2935 if( u16VScalReg != 0x1000 ) //Not support H/V scaling up and down at same time.
2936 {
2937 HAL_GOP_Write16Reg(pGOPHalLocal, u32BankOffSet+GOP_4G_HSTRCH, 0x1000 , GOP_REG_WORD_MASK);
2938 GOP_H_WARN("[%s] Warning message about GOP not support H/V scaling up and down at same time!!!!",__FUNCTION__);
2939 }
2940 //Set scaling down ratio
2941 ratio = (dst * 0x100000) / src;
2942 HAL_GOP_Write32Reg(pGOPHalLocal, u32BankOffSet+GOP_4G_SCALING_HRATIO_L, ratio);
2943 }
2944 else
2945 {
2946 HAL_GOP_Write32Reg(pGOPHalLocal, u32BankOffSet+GOP_4G_SCALING_HRATIO_L, 0);
2947 }
2948
2949 if(g_GopChipPro.bGOPWithScaleDown[u8GOP] ==TRUE)
2950 {
2951 HAL_GOP_EnableScalingDownSram(pGOPHalLocal, u8GOP, bEnable);
2952 }
2953 HAL_GOP_Write16Reg(pGOPHalLocal, u32BankOffSet+GOP_4G_SCALING_CFG, bEnable , GOP_BIT0);
2954 HAL_GOP_Write16Reg(pGOPHalLocal, u32BankOffSet+GOP_4G_SCALING_H_OUTPUTSIZE, dst, GOP_REG_WORD_MASK);
2955
2956 return GOP_SUCCESS;
2957
2958 }
2959
HAL_GOP_VScalingDown(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_U8 u8GOP,MS_BOOL bEnable,MS_U16 src,MS_U16 dst)2960 GOP_Result HAL_GOP_VScalingDown(GOP_CTX_HAL_LOCAL *pGOPHalLocal,MS_U8 u8GOP, MS_BOOL bEnable,MS_U16 src, MS_U16 dst)
2961 {
2962 MS_U32 ratio =0;
2963 MS_U32 u32BankOffSet=0xFFFF;
2964 MS_U16 u16HScalReg;
2965
2966 _GetBnkOfstByGop(u8GOP, &u32BankOffSet);
2967 if(bEnable ==TRUE)
2968 {
2969 HAL_GOP_Read16Reg(pGOPHalLocal, u32BankOffSet+GOP_4G_HSTRCH, &u16HScalReg);
2970 if( u16HScalReg != 0x1000 ) //Not support H/V scaling up and down at same time.
2971 {
2972 HAL_GOP_Write16Reg(pGOPHalLocal, u32BankOffSet+GOP_4G_VSTRCH, 0x1000 , GOP_REG_WORD_MASK);
2973 GOP_H_WARN("[%s] Warning message about GOP not support H/V scaling up and down at same time!!!!",__FUNCTION__);
2974 }
2975 ratio = (dst * 0x100000) / src;
2976 HAL_GOP_Write32Reg(pGOPHalLocal, u32BankOffSet+GOP_4G_SCALING_VRATIO_L, ratio);
2977 }
2978 else
2979 {
2980 HAL_GOP_Write32Reg(pGOPHalLocal, u32BankOffSet+GOP_4G_SCALING_VRATIO_L, 0);
2981 }
2982
2983 if(g_GopChipPro.bGOPWithScaleDown[u8GOP] ==TRUE)
2984 {
2985 HAL_GOP_EnableScalingDownSram(pGOPHalLocal, u8GOP, bEnable);
2986 }
2987 HAL_GOP_Write16Reg(pGOPHalLocal, u32BankOffSet+GOP_4G_SCALING_CFG, (bEnable<<4) , GOP_BIT4);
2988 HAL_GOP_Write16Reg(pGOPHalLocal, u32BankOffSet+GOP_4G_SVM_VEND, dst, GOP_REG_WORD_MASK);
2989
2990 return GOP_SUCCESS;
2991
2992 }
2993
HAL_GOP_DeleteWinHVSize(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_U8 u8GOP,MS_U16 u16HSize,MS_U16 u16VSize)2994 GOP_Result HAL_GOP_DeleteWinHVSize(GOP_CTX_HAL_LOCAL *pGOPHalLocal,MS_U8 u8GOP, MS_U16 u16HSize, MS_U16 u16VSize)
2995 {
2996 MS_U32 u32BankOffSet=0;
2997
2998 _GetBnkOfstByGop(u8GOP, &u32BankOffSet);
2999 HAL_GOP_Write16Reg(pGOPHalLocal, u32BankOffSet + GOP_4G_BANK_HVAILDSIZE, u16HSize, GOP_REG_WORD_MASK);
3000 HAL_GOP_Write16Reg(pGOPHalLocal, u32BankOffSet + GOP_4G_BANK_VVAILDSIZE, u16VSize, GOP_REG_WORD_MASK);
3001 return GOP_SUCCESS;
3002 }
3003
HAL_GOP_DumpGOPReg(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_U32 u32GopIdx,MS_U16 u16BankIdx,MS_U16 u16Addr,MS_U16 * u16Val)3004 GOP_Result HAL_GOP_DumpGOPReg(GOP_CTX_HAL_LOCAL *pGOPHalLocal, MS_U32 u32GopIdx, MS_U16 u16BankIdx, MS_U16 u16Addr, MS_U16* u16Val)
3005 {
3006 MS_U32 u32BankOffSet=0;
3007 _GetBnkOfstByGop(u32GopIdx, &u32BankOffSet);
3008
3009 if (u32GopIdx < MAX_GOP_SUPPORT)
3010 {
3011 HAL_GOP_Read16Reg(pGOPHalLocal, (u32BankOffSet+ (u16BankIdx<<16) + u16Addr +GOP_4G_CTRL0), u16Val);
3012 }
3013 else
3014 {
3015 GOP_H_DBUG("[%s][%d] Data is zero!!!\n",__FUNCTION__,__LINE__);
3016 *u16Val = 0;
3017 }
3018 return GOP_SUCCESS;
3019 }
3020
HAL_GOP_RestoreGOPReg(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_U32 u32GopIdx,MS_U16 u16BankIdx,MS_U16 u16Addr,MS_U16 u16Val)3021 GOP_Result HAL_GOP_RestoreGOPReg(GOP_CTX_HAL_LOCAL *pGOPHalLocal, MS_U32 u32GopIdx, MS_U16 u16BankIdx, MS_U16 u16Addr, MS_U16 u16Val)
3022 {
3023 MS_U32 u32BankOffSet=0;
3024 _GetBnkOfstByGop(u32GopIdx, &u32BankOffSet);
3025
3026 if (u32GopIdx < MAX_GOP_SUPPORT)
3027 {
3028 HAL_GOP_Write16Reg(pGOPHalLocal, (u32BankOffSet+ (u16BankIdx<<16) + u16Addr +GOP_4G_CTRL0), u16Val, GOP_REG_WORD_MASK);
3029 }
3030 else
3031 {
3032 GOP_H_DBUG("[%s][%d] Data is zero!!!\n",__FUNCTION__,__LINE__);
3033 }
3034 return GOP_SUCCESS;
3035 }
3036
HAL_GOP_PowerState(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_U32 u32PowerState,GFLIP_REGS_SAVE_AREA * pGOP_STRPrivate)3037 GOP_Result HAL_GOP_PowerState(GOP_CTX_HAL_LOCAL *pGOPHalLocal, MS_U32 u32PowerState, GFLIP_REGS_SAVE_AREA* pGOP_STRPrivate)
3038 {
3039 switch(u32PowerState)
3040 {
3041 case E_POWER_SUSPEND:
3042 {
3043 //CLK
3044 HAL_GOP_Read16Reg(pGOPHalLocal, GOP_GOPCLK, &(pGOP_STRPrivate->CKG_GopReg[0]));
3045 HAL_GOP_Read16Reg(pGOPHalLocal, GOP_GOP2CLK, &(pGOP_STRPrivate->CKG_GopReg[1]));
3046 HAL_GOP_Read16Reg(pGOPHalLocal, GOP_GOP3CLK, &(pGOP_STRPrivate->CKG_GopReg[2]));
3047 HAL_GOP_Read16Reg(pGOPHalLocal, GOP_GOP4CLK, &(pGOP_STRPrivate->CKG_GopReg[3]));
3048 HAL_GOP_Read16Reg(pGOPHalLocal, GOP_SRAMCLK, &(pGOP_STRPrivate->CKG_GopReg[4]));
3049 HAL_GOP_Read16Reg(pGOPHalLocal, GOP_LB_SRAMCLK, &(pGOP_STRPrivate->CKG_GopReg[5]));
3050
3051 //SRAM
3052 HAL_GOP_Read16Reg(pGOPHalLocal, CKG_GOPG0_SCALING, &(pGOP_STRPrivate->GS_GopReg[0]));
3053 HAL_GOP_Read16Reg(pGOPHalLocal, CKG_GOPG0_MG, &(pGOP_STRPrivate->GS_GopReg[1]));
3054 // HAL_GOP_Read16Reg(pGOPHalLocal, GOP_SC_GOPSC_SRAM_CTRL, &(pGOP_STRPrivate->GS_GopReg[2]));
3055
3056 //XC
3057 HAL_GOP_Read16Reg(pGOPHalLocal, GOP_SC_BANKSEL, &(pGOP_STRPrivate->XC_GopReg[0]));
3058 HAL_GOP_Read16Reg(pGOPHalLocal, GOP_SC_CHANNELSYNC, &(pGOP_STRPrivate->XC_GopReg[1]));
3059 HAL_GOP_Read16Reg(pGOPHalLocal, GOP_SC_GOPEN, &(pGOP_STRPrivate->XC_GopReg[2]));
3060 HAL_GOP_Read16Reg(pGOPHalLocal, GOP_SC_IP_SYNC, &(pGOP_STRPrivate->XC_GopReg[3]));
3061 HAL_GOP_Read16Reg(pGOPHalLocal, GOP_SC_IP2GOP_SRCSEL, &(pGOP_STRPrivate->XC_GopReg[4]));
3062 HAL_GOP_Read16Reg(pGOPHalLocal, GOP_SC_OSD_CHECK_ALPHA, &(pGOP_STRPrivate->XC_GopReg[5]));
3063 HAL_GOP_Read16Reg(pGOPHalLocal, GOP_SC_VOPNBL, &(pGOP_STRPrivate->XC_GopReg[6]));
3064 HAL_GOP_Read16Reg(pGOPHalLocal, GOP_SC_GOPENMODE1, &(pGOP_STRPrivate->XC_GopReg[7]));
3065 HAL_GOP_Read16Reg(pGOPHalLocal, GOP_SC_MIRRORCFG, &(pGOP_STRPrivate->XC_GopReg[8]));
3066 HAL_GOP_Read16Reg(pGOPHalLocal, GOP_SC_OCMIXER, &(pGOP_STRPrivate->XC_GopReg[9]));
3067 HAL_GOP_Read16Reg(pGOPHalLocal, GOP_SC_OCMISC, &(pGOP_STRPrivate->XC_GopReg[10]));
3068 HAL_GOP_Read16Reg(pGOPHalLocal, GOP_SC_OCALPHA, &(pGOP_STRPrivate->XC_GopReg[11]));
3069 // HAL_GOP_Read16Reg(pGOPHalLocal, GOP_SC_GOPSC_SRAM_CTRL, &(pGOP_STRPrivate->XC_GopReg[12]));
3070 HAL_GOP_Read16Reg(pGOPHalLocal, GOP_SC1_CHANNELSYNC, &(pGOP_STRPrivate->XC_GopReg[13]));
3071 }
3072 break;
3073 case E_POWER_RESUME:
3074 {
3075 //CLK
3076 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_GOPCLK, pGOP_STRPrivate->CKG_GopReg[0], GOP_REG_WORD_MASK);
3077 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_GOP2CLK, pGOP_STRPrivate->CKG_GopReg[1], GOP_REG_WORD_MASK);
3078 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_GOP3CLK, pGOP_STRPrivate->CKG_GopReg[2], GOP_REG_WORD_MASK);
3079 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_GOP4CLK, pGOP_STRPrivate->CKG_GopReg[3], GOP_REG_WORD_MASK);
3080 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_SRAMCLK, pGOP_STRPrivate->CKG_GopReg[4], GOP_REG_WORD_MASK);
3081 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_LB_SRAMCLK, pGOP_STRPrivate->CKG_GopReg[5], GOP_REG_WORD_MASK);
3082
3083 //SRAM
3084 HAL_GOP_Write16Reg(pGOPHalLocal, CKG_GOPG0_SCALING, pGOP_STRPrivate->GS_GopReg[0], GOP_REG_WORD_MASK);
3085 HAL_GOP_Write16Reg(pGOPHalLocal, CKG_GOPG0_MG, pGOP_STRPrivate->GS_GopReg[1], GOP_REG_WORD_MASK);
3086 // HAL_GOP_Write16Reg(pGOPHalLocal, GOP_SC_GOPSC_SRAM_CTRL, pGOP_STRPrivate->GS_GopReg[2], GOP_REG_WORD_MASK);
3087
3088 //XC
3089 //HAL_GOP_Write16Reg(pGOPHalLocal, GOP_SC_BANKSEL, pGOP_STRPrivate->XC_GopReg[0], GOP_REG_WORD_MASK);
3090 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_SC_CHANNELSYNC, pGOP_STRPrivate->XC_GopReg[1], GOP_BIT11);
3091 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_SC_GOPEN, pGOP_STRPrivate->XC_GopReg[2], GOP_REG_WORD_MASK);
3092 //HAL_GOP_Write16Reg(pGOPHalLocal, GOP_SC_IP_SYNC, pGOP_STRPrivate->XC_GopReg[3], GOP_REG_WORD_MASK);
3093 //HAL_GOP_Write16Reg(pGOPHalLocal, GOP_SC_IP2GOP_SRCSEL, pGOP_STRPrivate->XC_GopReg[4], GOP_BIT15);
3094 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_SC_OSD_CHECK_ALPHA, pGOP_STRPrivate->XC_GopReg[5], GOP_BIT6);
3095 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_SC_VOPNBL, pGOP_STRPrivate->XC_GopReg[6], GOP_BIT5);
3096 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_SC_GOPENMODE1, pGOP_STRPrivate->XC_GopReg[7], GOP_REG_WORD_MASK);
3097 //HAL_GOP_Write16Reg(pGOPHalLocal, GOP_SC_MIRRORCFG, pGOP_STRPrivate->XC_GopReg[8], GOP_REG_WORD_MASK);
3098 //HAL_GOP_Write16Reg(pGOPHalLocal, GOP_SC_OCMIXER, pGOP_STRPrivate->XC_GopReg[9], GOP_REG_WORD_MASK);
3099 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_SC_OCMISC, pGOP_STRPrivate->XC_GopReg[10], GOP_BIT2);
3100 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_SC_OCALPHA, pGOP_STRPrivate->XC_GopReg[11], GOP_BIT2);
3101 // HAL_GOP_Write16Reg(pGOPHalLocal, GOP_SC_GOPSC_SRAM_CTRL, pGOP_STRPrivate->XC_GopReg[12], GOP_REG_WORD_MASK);
3102 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_SC1_CHANNELSYNC, pGOP_STRPrivate->XC_GopReg[13], GOP_BIT11);
3103 }
3104 break;
3105 default:
3106 break;
3107 }
3108 return GOP_SUCCESS;
3109 }
HAL_GOP_GWIN_SetGPUTileMode(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_U8 gwinid,EN_DRV_GOP_GPU_TILE_MODE tile_mode)3110 GOP_Result HAL_GOP_GWIN_SetGPUTileMode(GOP_CTX_HAL_LOCAL *pGOPHalLocal,MS_U8 gwinid, EN_DRV_GOP_GPU_TILE_MODE tile_mode)
3111 {
3112 return GOP_FUN_NOT_SUPPORTED;
3113 }
3114
HAL_GOP_EnableTLB(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_U8 u8GOP,MS_BOOL bEnable)3115 GOP_Result HAL_GOP_EnableTLB(GOP_CTX_HAL_LOCAL *pGOPHalLocal,MS_U8 u8GOP, MS_BOOL bEnable)
3116 {
3117 MS_U32 u32BankOffSet=0xFFFF;
3118
3119 _GetBnkOfstByGop(u8GOP, &u32BankOffSet);
3120 HAL_GOP_Write16Reg(pGOPHalLocal, u32BankOffSet+GOP_4G_SRAM_BORROW, bEnable?GOP_BIT10:0, GOP_BIT10);
3121 return GOP_SUCCESS;
3122 }
3123
HAL_GOP_SetTLBAddr(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_U8 u8GOP,MS_PHY u64TLBAddr,MS_U32 u32size)3124 GOP_Result HAL_GOP_SetTLBAddr(GOP_CTX_HAL_LOCAL *pGOPHalLocal, MS_U8 u8GOP, MS_PHY u64TLBAddr, MS_U32 u32size)
3125 {
3126 MS_U32 u32BankOffSet=0xFFFF;
3127 _GetBnkOfstByGop(u8GOP, &u32BankOffSet);
3128 HAL_GOP_Write16Reg(pGOPHalLocal, u32BankOffSet+REG_TLB_TAG_ADDR_L, u32size&GOP_REG_WORD_MASK, GOP_REG_WORD_MASK);
3129 HAL_GOP_Write16Reg(pGOPHalLocal, u32BankOffSet+REG_TLB_TAG_ADDR_H, u32size>>16, GOP_REG_WORD_MASK);
3130
3131 HAL_GOP_Write16Reg(pGOPHalLocal, u32BankOffSet+REG_TLB_BASE_ADDR_L, u64TLBAddr&GOP_REG_WORD_MASK, GOP_REG_WORD_MASK);
3132 HAL_GOP_Write16Reg(pGOPHalLocal, u32BankOffSet+REG_TLB_BASE_ADDR_H, u64TLBAddr>>16, GOP_REG_WORD_MASK);
3133 return GOP_SUCCESS;
3134 }
3135
HAL_GOP_SetTLBSubAddr(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_U8 u8GOP,MS_PHY u64TLBAddr)3136 GOP_Result HAL_GOP_SetTLBSubAddr(GOP_CTX_HAL_LOCAL *pGOPHalLocal, MS_U8 u8GOP, MS_PHY u64TLBAddr)
3137 {
3138 MS_U32 u32BankOffSet=0xFFFF;
3139 _GetBnkOfstByGop(u8GOP, &u32BankOffSet);
3140
3141 HAL_GOP_Write16Reg(pGOPHalLocal, u32BankOffSet+REG_TLB_BASE_ADDR_RVIEW_L, u64TLBAddr&GOP_REG_WORD_MASK, GOP_REG_WORD_MASK);
3142 HAL_GOP_Write16Reg(pGOPHalLocal, u32BankOffSet+REG_TLB_BASE_ADDR_RVIEW_H, u64TLBAddr>>16, GOP_REG_WORD_MASK);
3143
3144 return GOP_SUCCESS;
3145 }
3146
HAL_GOP_Set_GWIN_INTERNAL_MIU(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_U8 u8GOP,MS_U8 miusel)3147 GOP_Result HAL_GOP_Set_GWIN_INTERNAL_MIU(GOP_CTX_HAL_LOCAL *pGOPHalLocal, MS_U8 u8GOP,MS_U8 miusel)
3148 {
3149 MS_U32 u32BankOffSet=0xFFFF;
3150 _GetBnkOfstByGop(u8GOP, &u32BankOffSet);
3151
3152 HAL_GOP_Write16Reg(pGOPHalLocal, u32BankOffSet+GOP_4G_MIU_SEL, miusel<<0, GOP_BIT0|GOP_BIT1 );//GWIN Palette MIU Select
3153 HAL_GOP_Write16Reg(pGOPHalLocal, u32BankOffSet+GOP_4G_MIU_SEL, miusel<<2, GOP_BIT2|GOP_BIT3 );//GWIN MIU Select
3154 HAL_GOP_Write16Reg(pGOPHalLocal, u32BankOffSet+GOP_4G_MIU_SEL, miusel<<4, GOP_BIT4|GOP_BIT5 );//GWIN_3D MIU Select
3155
3156 return GOP_SUCCESS;
3157 }
3158
HAL_GOP_Set_MIU(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_U8 u8GOP,MS_U8 miusel)3159 GOP_Result HAL_GOP_Set_MIU(GOP_CTX_HAL_LOCAL *pGOPHalLocal, MS_U8 u8GOP,MS_U8 miusel)
3160 {
3161 MS_U32 u32BankOffSet=0xFFFF;
3162 MS_U16 mask_shift=0xFF;
3163 MS_U8 u8_mainGop = INVAILD_GOP_NUM, u8_combinedGop = INVAILD_GOP_NUM;
3164 MS_U32 u32CombineBankOffSet=0xFFFF;
3165
3166 _GetBnkOfstByGop(u8GOP, &u32BankOffSet);
3167
3168
3169 if(pGOPHalLocal->pGopChipPro->bInternalMIUSelect[u8GOP]==TRUE)
3170 {
3171 HAL_GOP_Write16Reg(pGOPHalLocal, u32BankOffSet+GOP_4G_MIU_SEL, miusel<<0, (GOP_BIT0|GOP_BIT1));//GWIN Palette MIU Select
3172 HAL_GOP_Write16Reg(pGOPHalLocal, u32BankOffSet+GOP_4G_MIU_SEL, miusel<<2, (GOP_BIT2|GOP_BIT3));//GWIN MIU Select
3173 HAL_GOP_Write16Reg(pGOPHalLocal, u32BankOffSet+GOP_4G_MIU_SEL, miusel<<4, (GOP_BIT4|GOP_BIT5));//GWIN_3D MIU Select
3174 }
3175 else
3176 {
3177 switch(u8GOP)
3178 {
3179 case E_GOP0:
3180 mask_shift = GOP_MIU_CLIENT_GOP0;
3181 break;
3182 case E_GOP1:
3183 mask_shift = GOP_MIU_CLIENT_GOP1;
3184 break;
3185 case E_GOP2:
3186 mask_shift = GOP_MIU_CLIENT_GOP2;
3187 break;
3188 case E_GOP3:
3189 mask_shift = GOP_MIU_CLIENT_GOP3;
3190 break;
3191 case E_GOP4:
3192 mask_shift = GOP_MIU_CLIENT_GOP4;
3193 break;
3194 case E_GOP_Dwin:
3195 mask_shift = GOP_MIU_CLIENT_DWIN;
3196 break;
3197 default:
3198 mask_shift = 0xFF;
3199 MS_CRITICAL_MSG(GOP_H_DBUG("ERROR gop miu client\n"));
3200 break;
3201 }
3202
3203 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_MIU_GROUP1, miusel<<mask_shift, 1<<mask_shift );
3204 #ifdef GOP_MIU_GROUP2
3205 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_MIU_GROUP2, (miusel>>1)<<mask_shift, 1<<mask_shift );
3206 #endif
3207
3208 }
3209
3210 if( FALSE == Hal_get4K120CombinedGOP(pGOPHalLocal, u8GOP, &u8_mainGop, &u8_combinedGop) )
3211 {
3212 GOP_H_ERR("Skipped [%s] Line %d !!", __FUNCTION__, __LINE__);
3213 return GOP_FAIL;
3214 }
3215 if (pGOPHalLocal->pHALShared->GOP_Dst[u8_mainGop] == E_DRV_GOP_DST_OP_DUAL_RATE)
3216 {
3217 if(u8GOP != u8_mainGop)
3218 u8GOP = u8_mainGop;
3219 else
3220 u8GOP = u8_combinedGop;
3221 _GetBnkOfstByGop(u8GOP, &u32CombineBankOffSet);
3222
3223 if(pGOPHalLocal->pGopChipPro->bInternalMIUSelect[u8GOP]==TRUE)
3224 {
3225 HAL_GOP_Write16Reg(pGOPHalLocal, u32CombineBankOffSet + GOP_4G_MIU_SEL, miusel<<0, GOP_BIT0|GOP_BIT1 );//GWIN Palette MIU Select
3226 HAL_GOP_Write16Reg(pGOPHalLocal, u32CombineBankOffSet + GOP_4G_MIU_SEL, miusel<<2, GOP_BIT2|GOP_BIT3 );//GWIN MIU Select
3227 HAL_GOP_Write16Reg(pGOPHalLocal, u32CombineBankOffSet + GOP_4G_MIU_SEL, miusel<<4, GOP_BIT4|GOP_BIT5 );//GWIN_3D MIU Select
3228 }
3229 else
3230 {
3231 switch(u8GOP)
3232 {
3233 case E_GOP0:
3234 mask_shift = GOP_MIU_CLIENT_GOP0;
3235 break;
3236 case E_GOP1:
3237 mask_shift = GOP_MIU_CLIENT_GOP1;
3238 break;
3239 case E_GOP2:
3240 mask_shift = GOP_MIU_CLIENT_GOP2;
3241 break;
3242 case E_GOP3:
3243 mask_shift = GOP_MIU_CLIENT_GOP3;
3244 break;
3245 case E_GOP4:
3246 mask_shift = GOP_MIU_CLIENT_GOP4;
3247 break;
3248 case E_GOP_Dwin:
3249 mask_shift = GOP_MIU_CLIENT_DWIN;
3250 break;
3251 default:
3252 mask_shift = 0xFF;
3253 MS_CRITICAL_MSG(GOP_H_DBUG("ERROR gop miu client\n"));
3254 break;
3255 }
3256 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_MIU_GROUP1, miusel<<mask_shift, 1<<mask_shift );
3257 #ifdef GOP_MIU_GROUP2
3258 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_MIU_GROUP2, (miusel>>1)<<mask_shift, 1<<mask_shift );
3259 #endif
3260
3261 }
3262
3263 }
3264
3265
3266 return GOP_SUCCESS;
3267 }
3268
HAL_GOP_IsHDREnabled(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_BOOL * pbHDREnable)3269 GOP_Result HAL_GOP_IsHDREnabled(GOP_CTX_HAL_LOCAL *pGOPHalLocal, MS_BOOL *pbHDREnable)
3270 {
3271 *pbHDREnable= FALSE;
3272 return GOP_FUN_NOT_SUPPORTED;
3273 }
3274
Hal_get4K120CombinedGOP(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_U8 u8GOP,MS_U8 * main_gop,MS_U8 * sub_gop)3275 static MS_BOOL Hal_get4K120CombinedGOP(
3276 GOP_CTX_HAL_LOCAL *pGOPHalLocal,
3277 MS_U8 u8GOP,
3278 MS_U8 * main_gop,
3279 MS_U8 * sub_gop)
3280 {
3281 if ((NULL == main_gop) || (NULL == sub_gop))
3282 {
3283 return FALSE;
3284 }
3285
3286 if (u8GOP >= MAX_GOP_SUPPORT)
3287 {
3288 GOP_H_ERR("[%s][%d] Out of GOP support!!! GOP=%d\n",__FUNCTION__,__LINE__ ,u8GOP);
3289 return FALSE;
3290 }
3291
3292 *main_gop = gop_4k120_pairs[u8GOP].mainGop;
3293 *sub_gop = gop_4k120_pairs[u8GOP].subGop;
3294
3295 return TRUE;
3296 }
3297
Hal_SetCropWindow(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_U8 u8GOP,EN_GOP_CROP_CTL crop_mode)3298 GOP_Result Hal_SetCropWindow(
3299 GOP_CTX_HAL_LOCAL *pGOPHalLocal,
3300 MS_U8 u8GOP,
3301 EN_GOP_CROP_CTL crop_mode
3302 )
3303 {
3304 MS_U32 u32MainBankOffSet=0xFFFF;
3305 MS_U32 u32CombineBankOffSet=0xFFFF;
3306 MS_U8 u8_mainGop, u8_combinedGop;
3307 MS_U16 crop_hstart;
3308 MS_U16 crop_hend;
3309 MS_U16 crop_vstart;
3310 MS_U16 crop_vend;
3311 MS_U16 gop_stretch_width = 0x0;
3312 MS_U16 gop_stretch_height = 0x0;
3313 MS_U16 u16HScalingRatio = 0x0;
3314 MS_U16 u16VScalingRatio = 0x0;
3315
3316 if (FALSE == Hal_get4K120CombinedGOP(pGOPHalLocal, u8GOP, &u8_mainGop, &u8_combinedGop))
3317 {
3318 GOP_H_ERR("Skipped [%s] Line %d !!", __FUNCTION__, __LINE__);
3319 return GOP_INVALID_PARAMETERS;
3320 }
3321
3322 if (u8GOP != u8_mainGop)
3323 {
3324 return GOP_ENUM_NOT_SUPPORTED;
3325 }
3326
3327 if (E_GOP4 == u8_mainGop)
3328 {
3329 // no crop for GOP4
3330 return GOP_ENUM_NOT_SUPPORTED;
3331 }
3332
3333 _GetBnkOfstByGop(u8_mainGop, &u32MainBankOffSet);
3334 _GetBnkOfstByGop(u8_combinedGop, &u32CombineBankOffSet);
3335
3336 if (EN_GOP_CROP_DISABLE == crop_mode)
3337 {
3338 HAL_GOP_Write16Reg(pGOPHalLocal, u32MainBankOffSet + GOP_4G_BANK_FWR, 0, GOP_BIT4);
3339 HAL_GOP_Write16Reg(pGOPHalLocal, u32CombineBankOffSet + GOP_4G_BANK_FWR, 0, GOP_BIT4);
3340 }
3341 else
3342 {
3343 HAL_GOP_Write16Reg(pGOPHalLocal, u32MainBankOffSet + GOP_4G_BANK_FWR, 0, GOP_BIT5); // use precal mode
3344
3345 HAL_GOP_Read16Reg(pGOPHalLocal, u32MainBankOffSet + GOP_4G_STRCH_HSZ, &gop_stretch_width);
3346 HAL_GOP_Read16Reg(pGOPHalLocal, u32MainBankOffSet + GOP_4G_STRCH_VSZ, &gop_stretch_height);
3347 HAL_GOP_Read16Reg(pGOPHalLocal, u32MainBankOffSet + GOP_4G_HSTRCH, &u16HScalingRatio);
3348 HAL_GOP_Read16Reg(pGOPHalLocal, u32MainBankOffSet + GOP_4G_VSTRCH, &u16VScalingRatio);
3349
3350 // crop left part
3351 crop_hstart = 0x0;
3352 crop_hend = (u16HScalingRatio != 0) ? ((SCALING_MULITPLIER / u16HScalingRatio) * gop_stretch_width) - 1 : 0x77F;
3353 crop_vstart = 0x0;
3354 crop_vend = (u16VScalingRatio != 0) ? ((SCALING_MULITPLIER / u16VScalingRatio) * gop_stretch_height) : 0x870;
3355
3356 HAL_GOP_Write16Reg(pGOPHalLocal, u32MainBankOffSet + GOP_4G_CROP_HSTART, crop_hstart, GOP_REG_WORD_MASK);
3357 HAL_GOP_Write16Reg(pGOPHalLocal, u32MainBankOffSet + GOP_4G_CROP_HEND, crop_hend, GOP_REG_WORD_MASK);
3358 HAL_GOP_Write16Reg(pGOPHalLocal, u32MainBankOffSet + GOP_4G_CROP_VSTART, crop_vstart, GOP_REG_WORD_MASK);
3359 HAL_GOP_Write16Reg(pGOPHalLocal, u32MainBankOffSet + GOP_4G_CROP_VEND, crop_vend, GOP_REG_WORD_MASK);
3360
3361 // crop left part
3362 crop_hstart = (u16HScalingRatio != 0) ? ((SCALING_MULITPLIER / u16HScalingRatio) * gop_stretch_width) : 0x780;
3363 crop_hend = (u16HScalingRatio != 0) ? ((SCALING_MULITPLIER / u16HScalingRatio) * gop_stretch_width * 2) - 1: 0xeff;
3364 crop_vstart = 0x0;
3365 crop_vend = (u16VScalingRatio != 0) ? ((SCALING_MULITPLIER / u16VScalingRatio) * gop_stretch_height) : 0x870;
3366 HAL_GOP_Write16Reg(pGOPHalLocal, u32CombineBankOffSet + GOP_4G_CROP_HSTART, crop_hstart, GOP_REG_WORD_MASK);
3367 HAL_GOP_Write16Reg(pGOPHalLocal, u32CombineBankOffSet + GOP_4G_CROP_HEND, crop_hend, GOP_REG_WORD_MASK);
3368 HAL_GOP_Write16Reg(pGOPHalLocal, u32CombineBankOffSet + GOP_4G_CROP_VSTART, crop_vstart, GOP_REG_WORD_MASK);
3369 HAL_GOP_Write16Reg(pGOPHalLocal, u32CombineBankOffSet + GOP_4G_CROP_VEND, crop_vend, GOP_REG_WORD_MASK);
3370
3371 // crop enable
3372 HAL_GOP_Write16Reg(pGOPHalLocal, u32MainBankOffSet + GOP_4G_BANK_FWR, GOP_BIT4, GOP_BIT4);
3373 HAL_GOP_Write16Reg(pGOPHalLocal, u32CombineBankOffSet + GOP_4G_BANK_FWR, GOP_BIT4, GOP_BIT4);
3374 }
3375
3376 return GOP_SUCCESS;
3377 }
3378
Hal_Ctrl4K120GopMode(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_U8 u8GOP,MS_BOOL bEnable)3379 static GOP_Result Hal_Ctrl4K120GopMode(
3380 GOP_CTX_HAL_LOCAL *pGOPHalLocal,
3381 MS_U8 u8GOP,
3382 MS_BOOL bEnable
3383 )
3384 {
3385 MS_U32 u32MainBankOffSet=0xFFFF;
3386 MS_U32 u32SubBankOffSet=0xFFFF;
3387 MS_U8 u8_mainGop = INVAILD_GOP_NUM, u8_combinedGop = INVAILD_GOP_NUM;
3388 MS_U8 miuClient4MainGop = 0, miuClient4SubGop = 0;
3389
3390 if( FALSE == Hal_get4K120CombinedGOP(pGOPHalLocal, u8GOP, &u8_mainGop, &u8_combinedGop) )
3391 {
3392 GOP_H_ERR("Skipped [%s] Line %d !!", __FUNCTION__, __LINE__);
3393 return GOP_FAIL;
3394 }
3395
3396 _GetBnkOfstByGop(u8_mainGop, &u32MainBankOffSet);
3397 _GetBnkOfstByGop(u8_combinedGop, &u32SubBankOffSet);
3398
3399 // enable GOP to 4K120 mode
3400 if ((E_GOP0 == u8_mainGop) || (E_GOP2 == u8_mainGop))
3401 {
3402 HAL_GOP_Write16Reg(pGOPHalLocal, u32MainBankOffSet + GOP_4G_MIU_SEL, (TRUE == bEnable) ? GOP_BIT8 : ~GOP_BIT8, GOP_BIT8);
3403 }
3404
3405 if (E_GOP3 == u8_combinedGop)
3406 {
3407 if (TRUE == bEnable)
3408 {
3409 // set GOP3 v-stretch method to duplicate mode
3410 HAL_GOP_Write16Reg(pGOPHalLocal, u32SubBankOffSet + GOP_4G_YUV_SWAP, 0, GOP_BIT9);
3411 }
3412 else if (FALSE == bEnable)
3413 {
3414 // restore GOP3 v-stretch method to duplicate mode
3415 HAL_GOP_Write16Reg(pGOPHalLocal, u32SubBankOffSet + GOP_4G_YUV_SWAP, GOP_BIT9, GOP_BIT9);
3416 }
3417 }
3418
3419 if ((E_GOP0 == u8_mainGop) || (E_GOP2 == u8_mainGop))
3420 {
3421 // crop trigger & GOP trigger tie together
3422 HAL_GOP_Write16Reg(pGOPHalLocal, u32MainBankOffSet + GOP_4G_BOT_HS, GOP_BIT12, GOP_BIT12);
3423 }
3424
3425 if ((bEnable == TRUE) && (E_GOP1 == u8_combinedGop))
3426 {
3427 HAL_GOP_Write16Reg(pGOPHalLocal, u32SubBankOffSet+GOP_4G_CTRL1, 0x4100, GOP_REG_HW_MASK);
3428 }
3429
3430 #ifdef GOP_SUPPORT_SPLIT_MODE
3431 if (E_GOP4 == u8_mainGop)
3432 {
3433 if ((bEnable == TRUE))
3434 {
3435 MS_U16 gwin_width, gwin_height;
3436 MS_U16 gwin_hstart, gwin_hend;
3437 MS_U16 gwin_vstart, gwin_vend;
3438
3439 HAL_GOP_Read16Reg(pGOPHalLocal, u32MainBankOffSet + GOP_1GS0_HSTR, &gwin_hstart);
3440 HAL_GOP_Read16Reg(pGOPHalLocal, u32MainBankOffSet + GOP_1GS0_HEND, &gwin_hend);
3441 HAL_GOP_Read16Reg(pGOPHalLocal, u32MainBankOffSet + GOP_1GS0_VSTR, &gwin_vstart);
3442 HAL_GOP_Read16Reg(pGOPHalLocal, u32MainBankOffSet + GOP_1GS0_VEND, &gwin_vend);
3443
3444 gwin_width = (gwin_hend > gwin_hstart) ? gwin_hend - gwin_hstart : 0;
3445 gwin_height = (gwin_vend > gwin_vstart) ? gwin_vend - gwin_vstart : 0;
3446
3447 // change the mouse moving method to split shift mode
3448 // 1. gwin size must smaller than 512 * 256
3449 if (gwin_width > GOP4_SPLITMODE_MAX_HSIZE)
3450 {
3451 gwin_hstart = 0;
3452 gwin_hend = GOP4_SPLITMODE_MAX_HSIZE;
3453 gwin_width = GOP4_SPLITMODE_MAX_HSIZE;
3454
3455 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_1GS0_HSTR, gwin_hstart, GOP_REG_WORD_MASK);
3456 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_1GS0_HEND, gwin_hend, GOP_REG_WORD_MASK);
3457 }
3458 if (gwin_height > GOP4_SPLITMODE_MAX_VSIZE)
3459 {
3460 gwin_vstart = 0;
3461 gwin_vend = GOP4_SPLITMODE_MAX_VSIZE;
3462 gwin_height = GOP4_SPLITMODE_MAX_VSIZE;
3463
3464 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_1GS0_HSTR, gwin_hstart, GOP_REG_WORD_MASK);
3465 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_1GS0_HEND, gwin_hend, GOP_REG_WORD_MASK);
3466 }
3467
3468 // 2. move to gwin hstart = 0 because pipe shift tie with GWIN position.
3469 gwin_hend -= gwin_hstart;
3470 gwin_hstart = 0;
3471 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_1GS0_HSTR, gwin_hstart, GOP_REG_WORD_MASK);
3472 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_1GS0_HEND, gwin_hend, GOP_REG_WORD_MASK);
3473
3474 // 2. sync GOP4 stretch window & gwin size
3475 HAL_GOP_Write16Reg(pGOPHalLocal, u32MainBankOffSet + GOP_4G_STRCH_HSZ, GOP_SPLIT_SUPPORT_MAXW/GOP_STRETCH_WIDTH_UNIT, GOP_REG_WORD_MASK);
3476
3477 // 3. garband = 0
3478 HAL_GOP_Write16Reg(pGOPHalLocal, u32MainBankOffSet + GOP_4G_SLPIT_GUARDBAND, 0, GOP_REG_WORD_MASK);
3479
3480 // 4. each L/R size of OP, unit: 2pix (when 2p engine), reg_op_hsize = target timing / 2
3481 // but 4k@120 always on 2P mode
3482 HAL_GOP_Write16Reg(pGOPHalLocal, u32MainBankOffSet + GOP_4G_SPLIT_LRSZ, (pGOPHalLocal->pHALShared->u16GopSplitMode_LRWIDTH[u8GOP] >> 1), GOP_REG_WORD_MASK);
3483
3484 // 5. enable split mode
3485 HAL_GOP_Write16Reg(pGOPHalLocal, u32MainBankOffSet + GOP_4G_MULTI_ALPHA, GOP_BIT15, GOP_BIT15);
3486 }
3487 else
3488 {
3489 // 5. disable split mode
3490 HAL_GOP_Write16Reg(pGOPHalLocal, u32MainBankOffSet + GOP_4G_MULTI_ALPHA, 0x0, GOP_BIT15);
3491 }
3492 }
3493
3494 #endif
3495
3496 if (TRUE == bEnable)
3497 {
3498 // if on 4K@120 mode, we need to sync the MIU client
3499 miuClient4MainGop = HAL_GOP_GetMIUDst(pGOPHalLocal, u8_mainGop);
3500 miuClient4SubGop = HAL_GOP_GetMIUDst(pGOPHalLocal, u8_combinedGop);
3501 if (miuClient4MainGop != miuClient4SubGop)
3502 {
3503 HAL_GOP_Set_MIU(pGOPHalLocal, u8_combinedGop, miuClient4MainGop);
3504 }
3505 }
3506
3507 return GOP_SUCCESS;
3508 }
3509
HAL_GOP_SetGopGwinHVPixel(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_U8 u8GOP,MS_U8 u8win,MS_U16 hstart,MS_U16 hend,MS_U16 vstart,MS_U16 vend)3510 GOP_Result HAL_GOP_SetGopGwinHVPixel(GOP_CTX_HAL_LOCAL *pGOPHalLocal, MS_U8 u8GOP, MS_U8 u8win, MS_U16 hstart, MS_U16 hend, MS_U16 vstart, MS_U16 vend)
3511 {
3512 GOP_Result ret = GOP_SUCCESS;
3513
3514 switch(u8GOP)
3515 {
3516 case E_GOP0:
3517 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_4G_HSTR(u8win), hstart, GOP_REG_WORD_MASK);
3518 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_4G_HEND(u8win), hend, GOP_REG_WORD_MASK);
3519 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_4G_VSTR(u8win), vstart, GOP_REG_WORD_MASK);
3520 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_4G_VEND(u8win), vend, GOP_REG_WORD_MASK);
3521 break;
3522
3523 case E_GOP1:
3524 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_2G_HSTR(u8win), hstart, GOP_REG_WORD_MASK);
3525 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_2G_HEND(u8win), hend, GOP_REG_WORD_MASK);
3526 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_2G_VSTR(u8win), vstart, GOP_REG_WORD_MASK); // 1 pixel
3527 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_2G_VEND(u8win), vend, GOP_REG_WORD_MASK); // 1 pixel
3528 break;
3529
3530 case E_GOP2:
3531 case E_GOP3:
3532 HAL_GOP_Write16Reg(pGOPHalLocal, (u8win==GOP2_Gwin0Id)?GOP_1G_HSTR:GOP_1GX_HSTR, hstart, GOP_REG_WORD_MASK); // word pixels
3533 HAL_GOP_Write16Reg(pGOPHalLocal, (u8win==GOP2_Gwin0Id)?GOP_1G_HEND:GOP_1GX_HEND, hend, GOP_REG_WORD_MASK); // word pixels
3534 HAL_GOP_Write16Reg(pGOPHalLocal, (u8win==GOP2_Gwin0Id)?GOP_1G_VSTR:GOP_1GX_VSTR, vstart, GOP_REG_WORD_MASK); // 1 pixel
3535 HAL_GOP_Write16Reg(pGOPHalLocal, (u8win==GOP2_Gwin0Id)?GOP_1G_VEND:GOP_1GX_VEND, vend, GOP_REG_WORD_MASK); // 1 pixel
3536 break;
3537
3538 case E_GOP4:
3539 if (pGOPHalLocal->pHALShared->GOP_Dst[u8GOP] == E_DRV_GOP_DST_OP_DUAL_RATE)
3540 {
3541 MS_U32 u32BankOffSet;
3542 _GetBnkOfstByGop(u8GOP, &u32BankOffSet);
3543
3544 // read the gwin hstart+hend might be a bad method
3545 // using varaiable directly
3546 MS_U16 win_hsz = (hend > hstart) ? hend - hstart : 0;
3547 MS_U16 win_vsz = (vend > vstart) ? vend - vstart : 0;
3548 MS_U16 gwin_hstart, gwin_hend;
3549 MS_U16 gwin_hsz;
3550 MS_U16 u16GopHScaleRatio;
3551
3552 if ((win_hsz > GOP4_SPLITMODE_MAX_HSIZE) || (win_vsz > GOP4_SPLITMODE_MAX_VSIZE))
3553 {
3554 // not support bigger than GOP4_SPLITMODE_MAX_HSIZE
3555 GOP_H_DBUG("cursor not support bigger than size : (%d, %d), set value : (%d, %d) \n", GOP4_SPLITMODE_MAX_HSIZE, GOP4_SPLITMODE_MAX_VSIZE, win_hsz, win_vsz);
3556 break;
3557 }
3558
3559 HAL_GOP_Read16Reg(pGOPHalLocal, GOP_1GS0_HSTR, &gwin_hstart);
3560 HAL_GOP_Read16Reg(pGOPHalLocal, GOP_1GS0_HSTR, &gwin_hend);
3561 gwin_hsz = (gwin_hend > gwin_hstart) ? gwin_hend - gwin_hstart : 0;
3562
3563 if (win_hsz != gwin_hsz) // gwin size changed
3564 {
3565 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_1GS0_HSTR, 0, GOP_REG_WORD_MASK);
3566 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_1GS0_HEND, win_hsz, GOP_REG_WORD_MASK);
3567 }
3568
3569 HAL_GOP_Read16Reg(pGOPHalLocal, u32BankOffSet + GOP_4G_HSTRCH, &u16GopHScaleRatio);
3570 hstart = (MS_U16)(((MS_U32)hstart * SCALING_MULITPLIER) / u16GopHScaleRatio);
3571 HAL_GOP_Write16Reg(pGOPHalLocal, u32BankOffSet + GOP_4G_SLPIT_SHIFT_PIPE, hstart, GOP_REG_WORD_MASK);
3572
3573 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_1GS0_VSTR, vstart, GOP_REG_WORD_MASK); // 1 pixel
3574 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_1GS0_VEND, vend, GOP_REG_WORD_MASK); // 1 pixel
3575 }
3576 else
3577 {
3578 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_1GS0_HSTR, hstart, GOP_REG_WORD_MASK);
3579 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_1GS0_HEND, hend, GOP_REG_WORD_MASK);
3580 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_1GS0_VSTR, vstart, GOP_REG_WORD_MASK); // 1 pixel
3581 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_1GS0_VEND, vend, GOP_REG_WORD_MASK); // 1 pixel
3582 }
3583 break;
3584
3585 default:
3586 GOP_H_DBUG("invalid Gwin number:%d\n",u8win);
3587 break;
3588 }
3589
3590 return ret;
3591 }
3592
_findMuxNumberByGOP(GOP_CTX_HAL_LOCAL * pGOPHalLocal,DRV_GOPDstType dst_type,MS_U8 u8Gop)3593 static MS_U16 _findMuxNumberByGOP(GOP_CTX_HAL_LOCAL *pGOPHalLocal, DRV_GOPDstType dst_type, MS_U8 u8Gop)
3594 {
3595 MS_U16 ret_mux = INVALID_GOP_MUX_VAL;
3596
3597 if (E_DRV_GOP_DST_OP_DUAL_RATE == dst_type)
3598 {
3599 MS_U16 finding_mux_value = 0xFFFF;
3600 MS_U16 muxValue;
3601
3602 HAL_GOP_Read16Reg(pGOPHalLocal, GOP_MUX4_4K120, &muxValue);
3603
3604 if (E_GOP0 == u8Gop)
3605 {
3606 finding_mux_value = GOP_4K120MUX_MUX0;
3607 }
3608 else if (E_GOP2 == u8Gop)
3609 {
3610 finding_mux_value = GOP_4K120MUX_MUX1;
3611 }
3612 else if (E_GOP4 == u8Gop)
3613 {
3614 finding_mux_value = GOP_4K120MUX_MUX2;
3615 }
3616
3617 if (finding_mux_value == ((muxValue & GOP_4K120_MUX0_MASK) >> (GOP_4K120_MUX_SHIFT*0)))
3618 {
3619 ret_mux = GOP_4K120MUX_MUX0;
3620 }
3621 else if (finding_mux_value == ((muxValue & GOP_4K120_MUX1_MASK) >> (GOP_4K120_MUX_SHIFT*1)))
3622 {
3623 ret_mux = GOP_4K120MUX_MUX1;
3624 }
3625 else if (finding_mux_value == ((muxValue & GOP_4K120_MUX2_MASK) >> (GOP_4K120_MUX_SHIFT*2)))
3626 {
3627 ret_mux = GOP_4K120MUX_MUX2;
3628 }
3629 }
3630
3631 return ret_mux;
3632 }
3633
HAL_GOP_GetIPInterlace(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_BOOL * bInterlace)3634 GOP_Result HAL_GOP_GetIPInterlace(GOP_CTX_HAL_LOCAL *pGOPHalLocal, MS_BOOL *bInterlace)
3635 {
3636 MS_U16 reg_val = 0;
3637
3638 // Note: Kastor XC use hand-shake mode, this register is differ to Kano's
3639 HAL_GOP_Read16Reg(pGOPHalLocal, GOP_SC_IP_MAIN_USR_INTERLACE, ®_val);
3640 if(reg_val & BIT(1))
3641 *bInterlace = TRUE;
3642 else
3643 *bInterlace = FALSE;
3644 return GOP_SUCCESS;
3645 }
3646
HAL_GOP_AFBC_GetCore(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_U8 u8GOP,MS_U8 * u8Core)3647 GOP_Result HAL_GOP_AFBC_GetCore(GOP_CTX_HAL_LOCAL *pGOPHalLocal, MS_U8 u8GOP,MS_U8* u8Core)
3648 {
3649 if(u8GOP==0)
3650 {
3651 *u8Core=0;
3652 }
3653 else
3654 {
3655 *u8Core=1;
3656 }
3657 return GOP_SUCCESS;
3658 }
3659
3660 #ifdef GOP_CMDQ_ENABLE
_SetCommandQueueIntMasked(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_U32 u32GopIdx,MS_BOOL bMasked)3661 static MS_BOOL _SetCommandQueueIntMasked(GOP_CTX_HAL_LOCAL *pGOPHalLocal, MS_U32 u32GopIdx, MS_BOOL bMasked)
3662 {
3663 MS_U32 u32FireBankOffSet = 0;
3664 _GetBnkOfstByGop(u32GopIdx, &u32FireBankOffSet);
3665 MsOS_DelayTask(1);
3666
3667 if(bMasked)
3668 HAL_GOP_Write16Reg(pGOPHalLocal, u32FireBankOffSet+GOP_4G_MULTI_ALPHA, GOP_BIT4, GOP_BIT4);//reset mask
3669 else
3670 HAL_GOP_Write16Reg(pGOPHalLocal, u32FireBankOffSet+GOP_4G_MULTI_ALPHA, 0, GOP_BIT4); //reset nable detect
3671
3672 return GOP_SUCCESS;
3673 }
3674
HAL_GOP_CMDQ_WriteCommand(GOP_CTX_HAL_LOCAL * pGOPHalLocal,CAF_Struct * cmdq_struct,MS_U32 * number,MS_U32 u32addr,MS_U16 u16val,MS_U16 mask)3675 GOP_Result HAL_GOP_CMDQ_WriteCommand(GOP_CTX_HAL_LOCAL *pGOPHalLocal,CAF_Struct *cmdq_struct,MS_U32 *number,MS_U32 u32addr, MS_U16 u16val, MS_U16 mask)
3676 {
3677 MS_U16 u16xcSubbank=0;
3678 MS_U32 bank;
3679 MS_U32 direct_addr;
3680
3681 switch (u32addr & 0xFF00)
3682 {
3683 case GOP_REG_BASE:
3684 {
3685 bank = (u32addr & 0xFF0000) >> 8;
3686
3687 if(bank==0xE00)//GOP4: 0x121B00
3688 {
3689 bank=GOP_REG_GOP4_BK_OFFSET;
3690 }
3691 else if(bank==0xF00)//GWIN4: 0x121E00
3692 {
3693 bank=GOP_REG_GOP4_GW_OFFSET;
3694 }
3695 else if(bank==0x1000) //GOP4_ST
3696 {
3697 bank=GOP_REG_GOP4_ST_OFFSET;
3698 }
3699
3700 if(bank==0x3100)//AFBC
3701 {
3702 direct_addr = AFBC_REG_BASE + (u32addr & 0xFF); //Direct_Base + addr_offset
3703 }
3704 else
3705 {
3706 direct_addr = GOP_REG_DIRECT_BASE + bank + (u32addr & 0xFF);
3707 }
3708 cmdq_struct[(*number)].destionation_address = (direct_addr&0xFFFFFF);
3709 cmdq_struct[(*number)].destionation_value = u16val;
3710 cmdq_struct[(*number)].mask = ((~mask)&0xFFFF);
3711 cmdq_struct[(*number)].operation = 0x57;
3712 (*number)++;
3713 break;
3714 }
3715 case SC1_REG_BASE:
3716 u16xcSubbank = (u32addr & 0xFF0000)>>8 ;
3717 direct_addr = SC1_DIRREG_BASE + u16xcSubbank+ (u32addr & 0xFF);
3718
3719 cmdq_struct[(*number)].destionation_address = (direct_addr&0xFFFFFF);
3720 cmdq_struct[(*number)].destionation_value = u16val;
3721 cmdq_struct[(*number)].mask = ((~mask)&0xFFFF);
3722 cmdq_struct[(*number)].operation = 0x57;
3723 (*number)++;
3724 break;
3725 case GE_REG_BASE:
3726 case CKG_REG_BASE:
3727 case MIU_REG_BASE:
3728 {
3729 cmdq_struct[(*number)].destionation_address = (u32addr&0xFFFFF)+0x100000;
3730 cmdq_struct[(*number)].destionation_value = u16val;
3731 cmdq_struct[(*number)].mask = ((~mask)&0xFFFF);
3732 cmdq_struct[(*number)].operation = 0x57;
3733 (*number)++;
3734 break;
3735 }
3736 #ifdef GOP_MIU_GROUP2
3737 case (MIU2_REG_BASE & 0xFF00):
3738 {
3739 direct_addr = MIU2_REG_BASE + (u32addr & 0xFF); //Direct_Base + addr_offset
3740
3741 cmdq_struct[(*number)].destionation_address = (direct_addr&0xFFFFFF);
3742 cmdq_struct[(*number)].destionation_value = u16val;
3743 cmdq_struct[(*number)].mask = ((~mask)&0xFFFF);
3744 cmdq_struct[(*number)].operation = 0x57;
3745 (*number)++;
3746 break;
3747 }
3748 #endif
3749 default:
3750 {
3751 //Gop lib current do not support this HW ip base
3752 GOP_ASSERT(0);
3753 break;
3754 }
3755
3756 }
3757 return GOP_SUCCESS;
3758 }
HAL_GOP_CMDQ_BegineDraw(GOP_CTX_HAL_LOCAL * pGOPHalLocal,CAF_Struct * target,MS_U32 * number,MS_U32 * u32GopIdx)3759 GOP_Result HAL_GOP_CMDQ_BegineDraw(GOP_CTX_HAL_LOCAL *pGOPHalLocal,CAF_Struct *target,MS_U32 *number, MS_U32 *u32GopIdx)
3760 {
3761 MS_U32 u32BankOffSet;
3762 MS_U16 u16RegVal1 = 0;
3763 MS_BOOL bCheckValidGop = FALSE;
3764 MS_U8 u8CheckTimeCnt = 0;
3765 MS_U8 u8CurrentCmdGop = 0;
3766
3767 while (!bCheckValidGop && (u8CheckTimeCnt < (GOPG3_GOP_CMDQ_INT_3 - GOPG0_GOP_CMDQ_INT_0 + 2)))
3768 {
3769 if (u8CurrentCmdGop > (GOPG3_GOP_CMDQ_INT_3 - GOPG0_GOP_CMDQ_INT_0))
3770 {
3771 u8CurrentCmdGop = 0;
3772 }
3773 _GetBnkOfstByGop(u8CurrentCmdGop, &u32BankOffSet);
3774 HAL_GOP_Read16Reg(pGOPHalLocal, u32BankOffSet + GOP_4G_CTRL0, &u16RegVal1);
3775 if ((u16RegVal1 & GOP_BIT0) != 0) // gop not init, cmdq won't work
3776 {
3777 bCheckValidGop = FALSE;
3778 }
3779 else
3780 {
3781 bCheckValidGop = TRUE;
3782 break;
3783 }
3784
3785 // if current gop not init, use next gop instead, check order 0->2->1->3
3786 switch (u8CurrentCmdGop)
3787 {
3788 case 0:
3789 u8CurrentCmdGop = 2;
3790 break;
3791 case 1:
3792 u8CurrentCmdGop = 0;
3793 break;
3794 case 2:
3795 u8CurrentCmdGop = 3;
3796 break;
3797 case 3:
3798 u8CurrentCmdGop = 1;
3799 break;
3800 default:
3801 u8CurrentCmdGop = 0;
3802 break;
3803 }
3804 u8CheckTimeCnt++;
3805 }
3806 if (!bCheckValidGop)
3807 {
3808 GOP_H_DBUG("[%s] Error message no avalible gop can support current cmdq!!\n",__FUNCTION__);
3809 }
3810
3811 *u32GopIdx = u8CurrentCmdGop;
3812 _SetCommandQueueIntMasked(pGOPHalLocal, *u32GopIdx, TRUE);
3813 MDrv_CMDQ_Gen_WaitTrigger_Bus_Command(&(target[(*number)]),GOPG0_GOP_CMDQ_INT_0 + u8CurrentCmdGop,FALSE);
3814 (*number)++;
3815 return GOP_SUCCESS;
3816 }
HAL_GOP_CMDQ_EndDraw(GOP_CTX_HAL_LOCAL * pGOPHalLocal,CAF_Struct * target,MS_U32 * number,MS_U32 u32GopIdx)3817 GOP_Result HAL_GOP_CMDQ_EndDraw(GOP_CTX_HAL_LOCAL *pGOPHalLocal,CAF_Struct *target,MS_U32 *number, MS_U32 u32GopIdx)
3818 {
3819 CH_Struct ch_fire;
3820 MS_U32 Receive_Return_Value = 0,u32BankOffSet = 0,timer1 = 0x0,timer2 = 0x0;
3821 MS_U16 u16ret = 0,u16ret1 = 0;
3822
3823 _GetBnkOfstByGop(0, &u32BankOffSet);
3824 HAL_GOP_Read16Reg(pGOPHalLocal,u32BankOffSet+GOP_4G_BG_CLR(1),&u16ret);
3825 HAL_GOP_CMDQ_WriteCommand(pGOPHalLocal,target,number,u32BankOffSet+GOP_4G_BG_CLR(1),u16ret+1,0xFFFF);//current GOP force write dis
3826 #if 0 //for Debug
3827 int i = 0;
3828 for(i=0;i<(*number);i++)
3829 {
3830 GOP_H_INFO("\33[0;36m [%d]op = %d, addr = %lx,value = %x,mask = %x\33[m \n",i,target[i].operation,target[i].destionation_address,target[i].destionation_value,target[i].mask);
3831 }
3832 #endif
3833 ch_fire.Command_Number = *number;
3834 ch_fire.Pointer_To_CAFArray = target;
3835 Receive_Return_Value = MDrv_CMDQ_Receive(&ch_fire);
3836 if(Receive_Return_Value == DRVCMDQ_CMDQ_FULL)
3837 {
3838 Receive_Return_Value = 0;
3839 MDrv_CMDQ_Printf_Crash_Command();
3840 }
3841
3842 _SetCommandQueueIntMasked(pGOPHalLocal, u32GopIdx, FALSE);
3843
3844 HAL_GOP_Read16Reg(pGOPHalLocal,u32BankOffSet+GOP_4G_BG_CLR(1),&u16ret1);
3845 timer1 = MsOS_GetSystemTime();
3846 timer2 = MsOS_GetSystemTime();
3847 while( u16ret1 != (u16ret+1) && ((timer2 - timer1)<100))
3848 {
3849 HAL_GOP_Read16Reg(pGOPHalLocal,u32BankOffSet+GOP_4G_BG_CLR(1),&u16ret1);
3850 MsOS_DelayTask(1);
3851 timer2 = MsOS_GetSystemTime();
3852 }
3853 if(u16ret1 != (u16ret+1))
3854 {
3855 GOP_H_DBUG("\33[0;36m %s:%d timeout = %ld org = %d target = %d\33[m \n",__FUNCTION__,__LINE__,(timer2 - timer1),u16ret1,(u16ret+1));
3856 MDrv_CMDQ_Printf_Crash_Command();
3857 }
3858 return GOP_SUCCESS;
3859 }
3860
HAL_GOP_CMDQ_SetGOPACK(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_U8 gop)3861 GOP_Result HAL_GOP_CMDQ_SetGOPACK(GOP_CTX_HAL_LOCAL *pGOPHalLocal,MS_U8 gop)
3862 {
3863 CAF_Struct fire_struct[24];
3864 MS_U32 u32BankOffSet;
3865 MS_U32 number = 0;
3866 MS_U16 u16RegVal1 = 0,u16RegVal2 = 0,u16RegVal3 = 0,u16MiuClient = 0;
3867 MS_U32 fireGOP=0;
3868
3869 _GetBnkOfstByGop(gop, &u32BankOffSet);
3870
3871 HAL_GOP_Read16Reg(pGOPHalLocal, GOP_MIU_GROUP1, &u16RegVal1);
3872 #ifdef GOP_MIU_GROUP2
3873 HAL_GOP_Read16Reg(pGOPHalLocal, GOP_MIU_GROUP2, &u16RegVal3);
3874 #endif
3875 HAL_GOP_Read16Reg(pGOPHalLocal, u32BankOffSet+GOP_4G_BANK_FWR,&u16RegVal2);
3876 HAL_GOP_CMDQ_BegineDraw(pGOPHalLocal,fire_struct,&number,&fireGOP);
3877
3878 switch(gop)
3879 {
3880 case E_GOP0:
3881 {
3882 u16MiuClient = GOP_MIU_CLIENT_GOP0;
3883 break;
3884 }
3885 case E_GOP1:
3886 {
3887 u16MiuClient = GOP_MIU_CLIENT_GOP1;
3888 break;
3889 }
3890 case E_GOP2:
3891 {
3892 u16MiuClient = GOP_MIU_CLIENT_GOP2;
3893 break;
3894 }
3895 case E_GOP3:
3896 {
3897 u16MiuClient = GOP_MIU_CLIENT_GOP3;
3898 break;
3899 }
3900 case E_GOP4:
3901 {
3902 u16MiuClient = GOP_MIU_CLIENT_GOP4;
3903 break;
3904 }
3905 default:
3906 {
3907 GOP_ASSERT(0);
3908 break;
3909 }
3910 }
3911 if(bMIUSelect[gop] == TRUE)
3912 {
3913 if(u16MIUSelect[gop] == 0)
3914 {
3915 u16RegVal1 &= ~(1<<u16MiuClient);
3916 u16RegVal3 &= ~(1<<u16MiuClient);
3917 }
3918 else if(u16MIUSelect[gop] == 1)
3919 {
3920 u16RegVal1 |= (1<<u16MiuClient);
3921 u16RegVal3 &= ~(1<<u16MiuClient);
3922 }
3923 else if(u16MIUSelect[gop] == 2)
3924 {
3925 u16RegVal1 &= ~(1<<u16MiuClient);
3926 u16RegVal3 |= (1<<u16MiuClient);
3927 }
3928 else if(u16MIUSelect[gop] == 3)
3929 {
3930 u16RegVal1 |= (1<<u16MiuClient);
3931 u16RegVal3 |= (1<<u16MiuClient);
3932 }
3933 bMIUSelect[gop] = FALSE;
3934 }
3935
3936 if(bAFBCMIUSelect[gop] == TRUE)
3937 {
3938 bAFBCMIUSelect[gop] = FALSE;
3939 }
3940 HAL_GOP_CMDQ_WriteCommand(pGOPHalLocal,fire_struct,&number,u32BankOffSet+GOP_4G_BANK_FWR,(u16RegVal2|(GOP_BIT0)) ,0xFFFF);//current GOP force write en
3941 HAL_GOP_CMDQ_WriteCommand(pGOPHalLocal,fire_struct,&number,u32BankOffSet+GOP_4G_BANK_FWR,(u16RegVal2&(~GOP_BIT0)) ,0xFFFF);//current GOP force write en
3942 HAL_GOP_CMDQ_WriteCommand(pGOPHalLocal,fire_struct,&number,GOP_MIU_GROUP1,u16RegVal1,0xFFFF);
3943
3944 if(g_GopChipPro.bAFBC_Merge_GOP_Trig ==FALSE)
3945 {
3946 if(bAFBCMIUSelect[gop] == TRUE)
3947 {
3948 HAL_GOP_CMDQ_WriteCommand(pGOPHalLocal,fire_struct,&number,REG_AFBC_MIU,u16AFBCMIUSelect[gop]<<4, 0xFFFF);
3949 bAFBCMIUSelect[gop] = FALSE;
3950 }
3951 HAL_GOP_CMDQ_WriteCommand(pGOPHalLocal,fire_struct,&number,REG_AFBC_MIU,u16AFBCMIUSelect[gop]<<4, 0xFFFF);
3952 HAL_GOP_CMDQ_WriteCommand(pGOPHalLocal,fire_struct,&number,REG_AFBC_TRIGGER,GOP_BIT1, 0xFFFF);
3953 HAL_GOP_CMDQ_WriteCommand(pGOPHalLocal,fire_struct,&number,REG_AFBC_TRIGGER,GOP_BIT0, 0xFFFF);
3954 }
3955 #ifdef GOP_MIU_GROUP2
3956 HAL_GOP_CMDQ_WriteCommand(pGOPHalLocal,fire_struct,&number,GOP_MIU_GROUP2,u16RegVal3,0xFFFF);
3957 #endif
3958
3959 HAL_GOP_CMDQ_EndDraw(pGOPHalLocal,fire_struct,&number,fireGOP);
3960 return GOP_SUCCESS;
3961 }
3962
HAL_GOP_CMDQ_SetGOPACKMask(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_U16 u16GopMask)3963 GOP_Result HAL_GOP_CMDQ_SetGOPACKMask(GOP_CTX_HAL_LOCAL *pGOPHalLocal,MS_U16 u16GopMask)
3964 {
3965 CAF_Struct fire_struct[24];
3966 MS_U32 u32BankOffSet=0;
3967 MS_U32 number = 0;
3968 MS_U8 gop=0;
3969 MS_U16 u16RegVal1=0,u16RegVal2=0,u16RegVal3 = 0,u16MiuClient = 0;
3970 MS_U32 fireGOP=0;
3971 MS_U16 bMiuChanged = FALSE;
3972 MS_U32 u32MainBankOffSet=0xFFFF;
3973 MS_U32 u32SubBankOffSet=0xFFFF;
3974 MS_U8 u8_mainGop = INVAILD_GOP_NUM, u8_combinedGop = INVAILD_GOP_NUM;
3975
3976 HAL_GOP_Read16Reg(pGOPHalLocal, GOP_MIU_GROUP1, &u16RegVal1);
3977 #ifdef GOP_MIU_GROUP2
3978 HAL_GOP_Read16Reg(pGOPHalLocal, GOP_MIU_GROUP2, &u16RegVal3);
3979 #endif
3980 HAL_GOP_CMDQ_BegineDraw(pGOPHalLocal,fire_struct,&number,&fireGOP);
3981
3982 for(gop = 0; gop<MAX_GOP_SUPPORT; gop++)
3983 {
3984 switch(gop)
3985 {
3986 case E_GOP0:
3987 {
3988 u16MiuClient = GOP_MIU_CLIENT_GOP0;
3989 break;
3990 }
3991 case E_GOP1:
3992 {
3993 u16MiuClient = GOP_MIU_CLIENT_GOP1;
3994 break;
3995 }
3996 case E_GOP2:
3997 {
3998 u16MiuClient = GOP_MIU_CLIENT_GOP2;
3999 break;
4000 }
4001 case E_GOP3:
4002 {
4003 u16MiuClient = GOP_MIU_CLIENT_GOP3;
4004 break;
4005 }
4006 case E_GOP4:
4007 {
4008 u16MiuClient = GOP_MIU_CLIENT_GOP4;
4009 break;
4010 }
4011 default:
4012 {
4013 continue;
4014 }
4015 }
4016
4017 if( FALSE == Hal_get4K120CombinedGOP(pGOPHalLocal, gop, &u8_mainGop, &u8_combinedGop) )
4018 {
4019 GOP_H_ERR("Skipped [%s] Line %d !!", __FUNCTION__, __LINE__);
4020 return GOP_FAIL;
4021 }
4022 _GetBnkOfstByGop(u8_mainGop, &u32MainBankOffSet);
4023 _GetBnkOfstByGop(u8_combinedGop, &u32SubBankOffSet);
4024
4025 if ((gop == u8_combinedGop) && (pGOPHalLocal->pHALShared->GOP_Dst[u8_mainGop] == E_DRV_GOP_DST_OP_DUAL_RATE))
4026 {
4027 continue;
4028 }
4029
4030 if( ( u16GopMask & (1<<gop) ) )
4031 {
4032 _GetBnkOfstByGop(gop, &u32BankOffSet);
4033 if(bMIUSelect[gop] == TRUE)
4034 {
4035 if(u16MIUSelect[gop] == 0)
4036 {
4037 u16RegVal1 &= ~(1<<u16MiuClient);
4038 u16RegVal3 &= ~(1<<u16MiuClient);
4039 }
4040 else if(u16MIUSelect[gop] == 1)
4041 {
4042 u16RegVal1 |= (1<<u16MiuClient);
4043 u16RegVal3 &= ~(1<<u16MiuClient);
4044 }
4045 else if(u16MIUSelect[gop] == 2)
4046 {
4047 u16RegVal1 &= ~(1<<u16MiuClient);
4048 u16RegVal3 |= (1<<u16MiuClient);
4049 }
4050 else if(u16MIUSelect[gop] == 3)
4051 {
4052 u16RegVal1 |= (1<<u16MiuClient);
4053 u16RegVal3 |= (1<<u16MiuClient);
4054 }
4055 bMIUSelect[gop] = FALSE;
4056 bMiuChanged = TRUE;
4057 }
4058
4059 if (pGOPHalLocal->pHALShared->GOP_Dst[u8_mainGop] == E_DRV_GOP_DST_OP_DUAL_RATE)
4060 {
4061 HAL_GOP_Read16Reg(pGOPHalLocal, u32BankOffSet+GOP_4G_BANK_FWR,&u16RegVal2);
4062 HAL_GOP_CMDQ_WriteCommand(pGOPHalLocal,fire_struct,&number,u32MainBankOffSet+GOP_4G_BANK_FWR,(u16RegVal2|(GOP_BIT0)) ,0xFFFF);//current GOP force write en
4063 HAL_GOP_CMDQ_WriteCommand(pGOPHalLocal,fire_struct,&number,u32MainBankOffSet+GOP_4G_BANK_FWR,(u16RegVal2&(~GOP_BIT0)) ,0xFFFF);//current GOP force write en
4064 HAL_GOP_CMDQ_WriteCommand(pGOPHalLocal,fire_struct,&number,u32SubBankOffSet+GOP_4G_BANK_FWR,(u16RegVal2|(GOP_BIT0)) ,0xFFFF);//current GOP force write en
4065 HAL_GOP_CMDQ_WriteCommand(pGOPHalLocal,fire_struct,&number,u32SubBankOffSet+GOP_4G_BANK_FWR,(u16RegVal2&(~GOP_BIT0)) ,0xFFFF);//current GOP force write en
4066 }
4067 else
4068 {
4069 HAL_GOP_Read16Reg(pGOPHalLocal, u32BankOffSet+GOP_4G_BANK_FWR,&u16RegVal2);
4070 HAL_GOP_CMDQ_WriteCommand(pGOPHalLocal,fire_struct,&number,u32BankOffSet+GOP_4G_BANK_FWR,(u16RegVal2|(GOP_BIT0)) ,0xFFFF);//current GOP force write en
4071 HAL_GOP_CMDQ_WriteCommand(pGOPHalLocal,fire_struct,&number,u32BankOffSet+GOP_4G_BANK_FWR,(u16RegVal2&(~GOP_BIT0)) ,0xFFFF);//current GOP force write en
4072 }
4073 }
4074 if(bAFBCMIUSelect[gop] == TRUE)
4075 {
4076 bAFBCMIUSelect[gop] = FALSE;
4077 }
4078 }
4079
4080 if (TRUE == bMiuChanged)
4081 {
4082 HAL_GOP_CMDQ_WriteCommand(pGOPHalLocal,fire_struct,&number,GOP_MIU_GROUP1,u16RegVal1,0xFFFF);
4083 #ifdef GOP_MIU_GROUP2
4084 HAL_GOP_CMDQ_WriteCommand(pGOPHalLocal,fire_struct,&number,GOP_MIU_GROUP2,u16RegVal3,0xFFFF);
4085 #endif
4086 }
4087
4088 HAL_GOP_CMDQ_EndDraw(pGOPHalLocal,fire_struct,&number,fireGOP);
4089 return GOP_SUCCESS;
4090 }
4091 #endif
4092
HAL_GOP_SetDbgLevel(EN_GOP_DEBUG_LEVEL level)4093 GOP_Result HAL_GOP_SetDbgLevel(EN_GOP_DEBUG_LEVEL level)
4094 {
4095 u32GOPDbgLevel_hal= level;
4096 return GOP_SUCCESS;
4097 }
4098
4099