1 //<MStar Software> 2 //****************************************************************************** 3 // MStar Software 4 // Copyright (c) 2010 - 2012 MStar Semiconductor, Inc. All rights reserved. 5 // All software, firmware and related documentation herein ("MStar Software") are 6 // intellectual property of MStar Semiconductor, Inc. ("MStar") and protected by 7 // law, including, but not limited to, copyright law and international treaties. 8 // Any use, modification, reproduction, retransmission, or republication of all 9 // or part of MStar Software is expressly prohibited, unless prior written 10 // permission has been granted by MStar. 11 // 12 // By accessing, browsing and/or using MStar Software, you acknowledge that you 13 // have read, understood, and agree, to be bound by below terms ("Terms") and to 14 // comply with all applicable laws and regulations: 15 // 16 // 1. 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MStar hereby reserves the 91 // rights to any and all damages, losses, costs and expenses resulting therefrom. 92 // 93 //////////////////////////////////////////////////////////////////////////////// 94 95 #ifndef _REG_GOP_H_ 96 #define _REG_GOP_H_ 97 98 //------------------------------------------------------------------------------------------------- 99 // Hardware Capability 100 //------------------------------------------------------------------------------------------------- 101 102 103 //------------------------------------------------------------------------------------------------- 104 // Macro and Define 105 //------------------------------------------------------------------------------------------------- 106 //---------------------------------------------------------------------------- 107 // HW IP Reg Base Adr 108 //---------------------------------------------------------------------------- 109 #define GOP_REG_BASE 0x1F00UL 110 #define GE_REG_BASE 0x2800UL 111 #define SC1_REG_BASE 0x2F00UL 112 #define CKG_REG_BASE 0x0B00UL 113 #define MIU0_REG_BASE 0x0600UL 114 #define MIU_REG_BASE 0x1200UL 115 #define MIU2_REG_BASE 0x162000 116 #define MVOP_REG_BASE 0x1400UL 117 #define SC1_DIRREG_BASE 0x130000UL 118 119 //---------------------------------------------------------------------------- 120 // Scaler Reg 121 //---------------------------------------------------------------------------- 122 #define XC_REG(bk, reg) (SC1_REG_BASE+((MS_U32)(bk)<<16) + (reg) * 2) 123 124 #define REG_SC_BK00_00_L XC_REG(0x00, 0x00) 125 #define REG_SC_BK00_05_L XC_REG(0x00, 0x05) 126 #define REG_SC_BK00_06_L XC_REG(0x00, 0x06) 127 #define REG_SC_BK01_02_L XC_REG(0x01, 0x02) 128 #define REG_SC_BK02_5F_L XC_REG(0x02, 0x5F) 129 #define REG_SC_BK0F_2B_L XC_REG(0x0F, 0x2B) 130 #define REG_SC_BK10_23_L XC_REG(0x10, 0x23) 131 #define REG_SC_BK10_5B_L XC_REG(0x10, 0x5B) 132 #define REG_SC_BK12_03_L XC_REG(0x12, 0x03) 133 #define REG_SC_BK37_22_L XC_REG(0x37, 0x22) 134 #define REG_SC_BK37_24_L XC_REG(0x37, 0x24) 135 #define REG_SC_BK37_28_L XC_REG(0x37, 0x28) 136 #define REG_SC_BK3D_0D_L XC_REG(0x3D, 0x0D) 137 #define REG_SC_BK40_22_L XC_REG(0x40, 0x22) 138 #define REG_SC_BK40_23_L XC_REG(0x40, 0x23) 139 #define REG_SC_BK40_24_L XC_REG(0x40, 0x24) 140 #define REG_SC_BK40_25_L XC_REG(0x40, 0x25) 141 #define REG_SC_BK7F_10_L XC_REG(0x7F, 0x10) 142 143 #define GOP_SC_BANKSEL REG_SC_BK00_00_L 144 #define GOP_SC_CHANNELSYNC REG_SC_BK00_05_L 145 #define GOP_SC_GOPEN REG_SC_BK00_06_L 146 #define GOP_SC_IP_SYNC REG_SC_BK01_02_L 147 #define GOP_SC_IP2GOP_SRCSEL REG_SC_BK02_5F_L 148 #define GOP_SC_OSD_CHECK_ALPHA REG_SC_BK0F_2B_L 149 #define GOP_SC_VOPNBL REG_SC_BK10_23_L 150 #define GOP_SC_GOPENMODE1 REG_SC_BK10_5B_L 151 #define GOP_SC_MIRRORCFG REG_SC_BK12_03_L 152 #define GOP_SC_OCMIXER REG_SC_BK37_22_L 153 #define GOP_SC_OCMISC REG_SC_BK37_24_L 154 #define GOP_SC_OCALPHA REG_SC_BK37_28_L 155 #define GOP_SC_GOPSC_SRAM_CTRL REG_SC_BK3D_0D_L 156 #define GOP_SC_FRC_LAYER1_L_EN REG_SC_BK40_22_L 157 #define GOP_SC_FRC_LAYER1_R_EN REG_SC_BK40_23_L 158 #define GOP_SC_FRC_LAYER2_L_EN REG_SC_BK40_24_L 159 #define GOP_SC_FRC_LAYER2_R_EN REG_SC_BK40_25_L 160 #define GOP_SC_MIU_SEL REG_SC_BK7F_10_L 161 162 //---------------------------------------------------------------------------- 163 // MVOP Reg 164 //---------------------------------------------------------------------------- 165 #define GOP_MVOP_MIRRORCFG (MVOP_REG_BASE+(0x3B*2)) 166 167 168 //---------------------------------------------------------------------------- 169 // GE Reg 170 //---------------------------------------------------------------------------- 171 #define GOP_GE_FMT_BLT (GE_REG_BASE+(0x01*2)) 172 #define GOP_GE_EN_CMDQ BIT(0) 173 #define GOP_GE_EN_VCMDQ BIT(1) 174 175 #define GOP_GE_VQ_FIFO_STATUS_L (GE_REG_BASE+(0x04*2)) 176 #define GOP_GE_VQ_FIFO_STATUS_H (GE_REG_BASE+(0x05*2)) 177 178 #define GOP_GE_STATUS (GE_REG_BASE+(0x07*2)) 179 #define GOP_GE_BUSY BIT(0) 180 #define GOP_GE_CMDQ1_STATUS BMASK(7:3) 181 #define GOP_GE_CMDQ2_STATUS BMASK(15:11) 182 183 #define GOP_GE_TAG (GE_REG_BASE+(0x2C*2)) 184 185 #define GOP_GE_DBBASE0 (GE_REG_BASE+(0x26*2)) 186 #define GOP_GE_DBBASE1 (GE_REG_BASE+(0x27*2)) 187 #define GOP_GE_DBPIT (GE_REG_BASE+(0x33*2)) 188 #define GOP_GE_FBFMT (GE_REG_BASE+(0x34*2)) 189 #define GOP_GE_SRCW (GE_REG_BASE+(0x6e*2)) 190 #define GOP_GE_SRCH (GE_REG_BASE+(0x6f*2)) 191 192 193 //---------------------------------------------------------------------------- 194 // ChipTop Reg 195 //---------------------------------------------------------------------------- 196 /* GOP0 and GOP1 CLK */ 197 #define GOP_GOPCLK (CKG_REG_BASE+(0x40<<1)) 198 #define CKG_GOPG0_DISABLE_CLK ~(GOP_BIT0) 199 #define CKG_GOPG0_ODCLK (0 << 2) 200 #define CKG_GOPG0_IDCLK2 (1 << 2) 201 #define CKG_GOPG0_IDCLK1 (2 << 2) 202 #define CKG_GOPG0_OCC_FRCCLK (3 << 2) 203 #define CKG_GOPG0_FCLK (8 << 2) 204 #define CKG_GOPG0_DISABLE_CLK_MASK (GOP_BIT0) 205 #define CKG_GOPG0_MASK (GOP_BIT5 | GOP_BIT4 | GOP_BIT3 | GOP_BIT2) 206 207 #define CKG_GOPG1_DISABLE_CLK ~(GOP_BIT8) 208 #define CKG_GOPG1_ODCLK (0 << 10) 209 #define CKG_GOPG1_IDCLK2 (1 << 10) 210 #define CKG_GOPG1_IDCLK1 (2 << 10) 211 #define CKG_GOPG1_OCC_FRCCLK (3 << 10) 212 #define CKG_GOPG1_FCLK (8 << 10) 213 #define CKG_GOPG1_DISABLE_CLK_MASK (GOP_BIT8) 214 #define CKG_GOPG1_MASK (GOP_BIT13 | GOP_BIT12 | GOP_BIT11 | GOP_BIT10) 215 216 #define CKG_GOPG0_SCALING (CKG_REG_BASE+0x88) 217 #define CKG_GOPG0_MG (CKG_REG_BASE+0xFE) 218 #define CKG_GOPG0_MG_MASK (GOP_BIT3 | GOP_BIT2) 219 #define CKG_GOPG2_MG_MASK (GOP_BIT7 | GOP_BIT6) 220 221 /* GOP2 and GOPDWIN CLK */ 222 #define GOP_GOP2CLK (CKG_REG_BASE+(0x41<<1)) 223 #define CKG_GOPG2_DISABLE_CLK ~(GOP_BIT0) 224 #define CKG_GOPG2_ODCLK (0<<2) 225 #define CKG_GOPG2_IDCLK2 (1 << 2) 226 #define CKG_GOPG2_IDCLK1 (2 << 2) 227 #define CKG_GOPG2_OCC_FRCCLK (3 << 2) 228 #define CKG_GOPG2_FCLK (8 << 2) 229 #define CKG_GOPG2_DISABLE_CLK_MASK (GOP_BIT0) 230 #define CKG_GOPG2_MASK (GOP_BIT5 |GOP_BIT4 | GOP_BIT3 | GOP_BIT2) 231 232 #define CKG_GOPD_CLK_IDCLK2 (0 << 10) 233 #define CKG_GOPD_CLK_ODCLK (1 << 10) 234 #define CKG_GOPD_CLK_DC0CLK (2 << 10) 235 #define CKG_GOPD_CLK_SUBDC0CLK (3 << 10) 236 #define CKG_GOPD_MASK (GOP_BIT12 | GOP_BIT11 | GOP_BIT10) 237 238 239 /* GOP3 CLK*/ 240 #define GOP_GOP3CLK (CKG_REG_BASE+(0x42<<1)) 241 #define CKG_GOPG3_ODCLK (0<<2) 242 #define CKG_GOPG3_IDCLK2 (1 << 2) 243 #define CKG_GOPG3_IDCLK1 (2 << 2) 244 #define CKG_GOPG3_OCC_FRCCLK (3 << 2) 245 #define CKG_GOPG3_FCLK (8 << 2) 246 #define CKG_GOPG3_DISABLE_CLK_MASK (GOP_BIT0) 247 #define CKG_GOPG3_MASK (GOP_BIT5 | GOP_BIT4 | GOP_BIT3 | GOP_BIT2) 248 #define CKG_GOPD_DISABLE_CLK ~(GOP_BIT8) 249 250 251 /* GOP4 CLK*/ 252 #define GOP_GOP4CLK (CKG_REG_BASE+(0x7E<<1)) 253 #define CKG_GOPG4_ODCLK (0 << 10) 254 #define CKG_GOPG4_IDCLK2 (1 << 10) 255 #define CKG_GOPG4_IDCLK1 (2 << 10) 256 #define CKG_GOPG4_OCC_FRCCLK (3 << 10) 257 #define CKG_GOPG4_FCLK (8 << 10) 258 #define CKG_GOPG4_DISABLE_CLK_MASK (GOP_BIT8) 259 #define CKG_GOPG4_MASK (GOP_BIT13 |GOP_BIT12 | GOP_BIT11 | GOP_BIT10) 260 261 262 /* SRAM CLK */ 263 #define GOP_SRAMCLK (CKG_REG_BASE+(0x43<<1)) 264 #define CKG_SRAM0_DISABLE_CLK (GOP_BIT0) 265 #define CKG_SRAM1_DISABLE_CLK (GOP_BIT8) 266 #define CKG_SRAM0_MASK (GOP_BIT0|GOP_BIT1) 267 #define CKG_SRAM1_MASK (GOP_BIT8|GOP_BIT9) 268 269 /* LINE BUFFER SRAM CLK */ 270 #define GOP_LB_SRAMCLK (CKG_REG_BASE+(0x45<<1)) 271 #define CKG_LB_SRAM1_DISABLE_CLK (GOP_BIT0) /*GOP1*/ 272 #define CKG_LB_SRAM2_DISABLE_CLK (GOP_BIT4) /*GOP2*/ 273 #define CKG_LB_SRAM1_MASK (GOP_BIT2|GOP_BIT3) 274 #define CKG_LB_SRAM2_MASK (GOP_BIT6|GOP_BIT7) 275 //---------------------------------------------------------------------------- 276 // MIU Reg 277 //---------------------------------------------------------------------------- 278 #define GOP_CLIENT_REG 0x7D 279 #define GOP_MIU_GROUP (MIU0_REG_BASE+(GOP_CLIENT_REG*2)) 280 #define GOP_MIU_GROUP1 (MIU_REG_BASE+(GOP_CLIENT_REG*2)) 281 282 /*Define each gop miu clint bit*/ 283 #define GOP_MIU_CLIENT_DWIN 0xFF 284 #define GOP_MIU_CLIENT_GOP0 0x5 285 #define GOP_MIU_CLIENT_GOP1 0x6 286 #define GOP_MIU_CLIENT_GOP2 0x7 287 #define GOP_MIU_CLIENT_GOP3 0xFF 288 #define GOP_MIU_CLIENT_GOP4 0xFF 289 #define GOP_MIU_CLIENT_GOP5 0xFF 290 291 //---------------------------------------------------------------------------- 292 // VE Reg 293 //---------------------------------------------------------------------------- 294 #define GOP_VE_TVS_OSD_EN 0x60 295 #define GOP_VE_TVS_OSD1_EN 0x61 296 297 //---------------------------------------------------------------------------- 298 // GOP Reg 299 //---------------------------------------------------------------------------- 300 #define GOP_REG(bk, reg) (GOP_REG_BASE+((MS_U32)(bk)<<16) + (reg) * 2) 301 #define __GOP_REG(reg) (GOP_REG_BASE+(reg) * 2) 302 #define GOP_REG_DIRECT_BASE (0x120200) 303 #define GOP_REG_GOP4_BK_OFFSET 0x1900 304 #define GOP_REG_GOP4_GW_OFFSET 0x1C00 305 #define GOP_REG_GOP4_ST_OFFSET 0x1D00 306 307 #define GOP_REG_VAL(x) (1<<x) 308 309 //MUX Setting 310 #define GOP_MUX_SHIFT 0x3 311 #define GOP_REGMUX_MASK BMASK((GOP_MUX_SHIFT-1):0) 312 #define GOP_MUX0_MASK (GOP_REGMUX_MASK<<(GOP_MUX_SHIFT*0)) 313 #define GOP_MUX1_MASK (GOP_REGMUX_MASK<<(GOP_MUX_SHIFT*1)) 314 #define GOP_MUX2_MASK (GOP_REGMUX_MASK<<(GOP_MUX_SHIFT*2)) 315 #define GOP_MUX3_MASK (GOP_REGMUX_MASK<<(GOP_MUX_SHIFT*3)) 316 #define GOP_MUX4_MASK (GOP_REGMUX_MASK<<(GOP_MUX_SHIFT*4)) 317 318 //IP and VOP MUX Setting 319 #define GOP_IP_MAIN_MUX_SHIFT 0 320 #define GOP_IP_MAIN_MUX_MASK (BMASK((GOP_MUX_SHIFT-1):0))<<GOP_IP_MAIN_MUX_SHIFT 321 #define GOP_IP_SUB_MUX_SHIFT 3 322 #define GOP_IP_SUB_MUX_MASK (BMASK((GOP_MUX_SHIFT-1):0))<<GOP_IP_SUB_MUX_SHIFT 323 #define GOP_IP_VOP0_MUX_SHIFT 6 324 #define GOP_IP_VOP0_MUX_MASK (BMASK((GOP_MUX_SHIFT-1):0))<<GOP_IP_VOP0_MUX_SHIFT 325 #define GOP_IP_VOP1_MUX_SHIFT 9 326 #define GOP_IP_VOP1_MUX_MASK (BMASK((GOP_MUX_SHIFT-1):0))<<GOP_IP_VOP1_MUX_SHIFT 327 328 329 //IP and VOP MUX Setting 330 #define GOP_Mix_MUX0_SHIFT 0 331 #define GOP_Mix_MUX0_MASK (BMASK((GOP_MUX_SHIFT-1):0))<<GOP_Mix_MUX0_SHIFT 332 #define GOP_Mix_MUX1_SHIFT 3 333 #define GOP_Mix_MUX1_MASK (BMASK((GOP_MUX_SHIFT-1):0))<<GOP_Mix_MUX1_SHIFT 334 #define GOP_VE0_MUX_SHIFT 6 335 #define GOP_VE0_MUX_MASK (BMASK((GOP_MUX_SHIFT-1):0))<<GOP_VE0_MUX_SHIFT 336 #define GOP_VE1_MUX_SHIFT 9 337 #define GOP_VE1_MUX_MASK (BMASK((GOP_MUX_SHIFT-1):0))<<GOP_VE1_MUX_SHIFT 338 339 340 //4k2k FRC MUX Setting 341 #define GOP_FRC_MUX_SHIFT 0x3 342 #define GOP_FRC_REGMUX_MASK BMASK((GOP_MUX_SHIFT-1):0) 343 #define GOP_FRC_MUX0_MASK (GOP_REGMUX_MASK<<(GOP_MUX_SHIFT*0)) 344 #define GOP_FRC_MUX1_MASK (GOP_REGMUX_MASK<<(GOP_MUX_SHIFT*1)) 345 #define GOP_FRC_MUX2_MASK (GOP_REGMUX_MASK<<(GOP_MUX_SHIFT*2)) 346 #define GOP_FRC_MUX3_MASK (GOP_REGMUX_MASK<<(GOP_MUX_SHIFT*3)) 347 348 //DIP Setting 349 #define GOP_DIP_MUX_SHIFT 12 350 #define GOP_DIP_MUX_MASK (BMASK((GOP_MUX_SHIFT-1):0))<<GOP_DIP_MUX_SHIFT 351 352 #define GOP_BANK_OFFSET 0x3 353 #define GOP_4G_OFST 0x0 354 #define GOP_2G_OFST (0x1*GOP_BANK_OFFSET) 355 #define GOP_1G_OFST (0x2*GOP_BANK_OFFSET) 356 #define GOP_1GX_OFST (0x3*GOP_BANK_OFFSET) 357 #define GOP_DW_OFST (0x4*GOP_BANK_OFFSET) 358 #define GOP_1GS0_OFST 0xE 359 #define GOP_1GS1_OFST 0x11 360 361 #define GOP_OFFSET_WR 8 362 #define GOP_VAL_WR GOP_REG_VAL(GOP_OFFSET_WR) 363 #define GOP_OFFSET_FWR 9 364 #define GOP_VAL_FWR GOP_REG_VAL(GOP_OFFSET_FWR) 365 #define GOP_OFFSET_FCLR 11 366 #define GOP_VAL_FCL GOP_REG_VAL(GOP_OFFSET_FCLR) 367 #define GOP4G_OFFSET_WR_ACK 12 368 #define GOP4G_VAL_WR_ACK GOP_REG_VAL(GOP4G_OFFSET_WR_ACK) 369 #define GOP2G_OFFSET_WR_ACK 13 370 #define GOP2G_VAL_WR_ACK GOP_REG_VAL(GOP2G_OFFSET_WR_ACK) 371 #define GOPD_OFFSET_WR_ACK 14 372 #define GOPD_VAL_WR_ACK GOP_REG_VAL(GOPD_OFFSET_WR_ACK) 373 #define GOP1G_OFFSET_WR_ACK 15 374 #define GOP1G_VAL_WR_ACK GOP_REG_VAL(GOPD_OFFSET_WR_ACK) 375 #define GOP_VAL_ACK(x) GOP_REG_VAL(GOP4G_OFFSET_WR_ACK+x) 376 377 #define GOP_4G_CTRL0 GOP_REG(GOP_4G_OFST, 0x00) 378 #define GOP_4G_CTRL1 GOP_REG(GOP_4G_OFST, 0x01) 379 #define GOP_4G_RATE GOP_REG(GOP_4G_OFST, 0x02) 380 #define GOP_4G_PALDATA_L GOP_REG(GOP_4G_OFST, 0x03) 381 #define GOP_4G_PALDATA_H GOP_REG(GOP_4G_OFST, 0x04) 382 #define GOP_4G_PALCTRL GOP_REG(GOP_4G_OFST, 0x05) 383 #define GOP_4G_REGDMA_END GOP_REG(GOP_4G_OFST, 0x06) 384 #define GOP_4G_REGDMA_STR GOP_REG(GOP_4G_OFST, 0x07) 385 #define GOP_4G_INT GOP_REG(GOP_4G_OFST, 0x08) 386 #define GOP_4G_HWSTATE GOP_REG(GOP_4G_OFST, 0x09) 387 #define GOP_4G_SVM_HSTR GOP_REG(GOP_4G_OFST, 0x0a) 388 #define GOP_4G_SVM_HEND GOP_REG(GOP_4G_OFST, 0x0b) 389 #define GOP_4G_SVM_VSTR GOP_REG(GOP_4G_OFST, 0x0c) 390 #define GOP_4G_SVM_VEND GOP_REG(GOP_4G_OFST, 0x0d) 391 #define GOP_4G_RDMA_HT GOP_REG(GOP_4G_OFST, 0x0e) 392 #define GOP_4G_HS_PIPE GOP_REG(GOP_4G_OFST, 0x0f) 393 #define GOP_4G_SLOW GOP_REG(GOP_4G_OFST, 0x10) 394 #define GOP_4G_BRI GOP_REG(GOP_4G_OFST, 0x11) 395 #define GOP_4G_CON GOP_REG(GOP_4G_OFST, 0x12) 396 #define GOP_4G_BW GOP_REG(GOP_4G_OFST, 0x19) 397 #define GOP_4G_NEW_BW GOP_REG(GOP_4G_OFST, 0x1C) 398 #define GOP_4G_SRAM_BORROW GOP_REG(GOP_4G_OFST, 0x1D) 399 #define GOP_4G_3D_MIDDLE GOP_REG(GOP_4G_OFST, 0x1E) 400 #define GOP_4G_MIU_SEL GOP_REG(GOP_4G_OFST, 0x1F) 401 #define GOP_4G_PRI0 GOP_REG(GOP_4G_OFST, 0x20) 402 #define GOP_4G_BOT_HS GOP_REG(GOP_4G_OFST, 0x23) 403 #define GOP_4G_TRSCLR_L GOP_REG(GOP_4G_OFST, 0x24) 404 #define GOP_4G_TRSCLR_H GOP_REG(GOP_4G_OFST, 0x25) 405 #define GOP_4G_YUV_SWAP GOP_REG(GOP_4G_OFST, 0x28) 406 #define GOP_4G_STRCH_HSZ GOP_REG(GOP_4G_OFST, 0x30) 407 #define GOP_4G_STRCH_VSZ GOP_REG(GOP_4G_OFST, 0x31) 408 #define GOP_4G_STRCH_HSTR GOP_REG(GOP_4G_OFST, 0x32) 409 #define GOP_4G_STRCH_VSTR GOP_REG(GOP_4G_OFST, 0x34) 410 #define GOP_4G_HSTRCH GOP_REG(GOP_4G_OFST, 0x35) 411 #define GOP_4G_VSTRCH GOP_REG(GOP_4G_OFST, 0x36) 412 #define GOP_4G_HSTRCH_INI GOP_REG(GOP_4G_OFST, 0x38) 413 #define GOP_4G_VSTRCH_INI GOP_REG(GOP_4G_OFST, 0x39) 414 #define GOP_4G_HVSTRCHMD GOP_REG(GOP_4G_OFST, 0x3a) 415 #define GOP_4G_OLDADDR GOP_REG(GOP_4G_OFST, 0x3b) 416 #define GOP_4G_MULTI_ALPHA GOP_REG(GOP_4G_OFST, 0x3c) 417 #define GOP_4G_HW_USAGE GOP_REG(GOP_4G_OFST, 0x40) 418 #define GOP_4G_BANK_FWR GOP_REG(GOP_4G_OFST, 0x50) 419 #define GOP_4G_BANK_HVAILDSIZE GOP_REG(GOP_4G_OFST, 0x52) 420 #define GOP_4G_BANK_VVAILDSIZE GOP_REG(GOP_4G_OFST, 0x53) 421 #define GOP_4G_SCALING_H_OUTPUTSIZE GOP_REG(GOP_4G_OFST, 0x56) 422 #define GOP_4G_SCALING_HRATIO_L GOP_REG(GOP_4G_OFST, 0x59) //GOP scaling down ratio dst / out * 2^20 423 #define GOP_4G_SCALING_HRATIO_H GOP_REG(GOP_4G_OFST, 0x5A) 424 #define GOP_4G_SCALING_CFG GOP_REG(GOP_4G_OFST, 0x5B) 425 #define GOP_4G_SCALING_VRATIO_L GOP_REG(GOP_4G_OFST, 0x5C) //GOP scaling down ratio dst / out * 2^20 426 #define GOP_4G_SCALING_VRATIO_H GOP_REG(GOP_4G_OFST, 0x5D) 427 428 429 #define GOP_4G_RBLK0_VOFFL GOP_REG(GOP_4G_OFST, 0x60) 430 #define GOP_4G_RBLK0_VOFFH GOP_REG(GOP_4G_OFST, 0x61) 431 #define GOP_4G_RBLK1_VOFFL GOP_REG(GOP_4G_OFST, 0x62) 432 #define GOP_4G_RBLK1_VOFFH GOP_REG(GOP_4G_OFST, 0x63) 433 #define GOP_4G_RBLK2_VOFFL GOP_REG(GOP_4G_OFST, 0x64) 434 #define GOP_4G_RBLK2_VOFFH GOP_REG(GOP_4G_OFST, 0x65) 435 #define GOP_4G_RBLK3_VOFFL GOP_REG(GOP_4G_OFST, 0x66) 436 #define GOP_4G_RBLK3_VOFFH GOP_REG(GOP_4G_OFST, 0x67) 437 #define GOP_4G_RBLK0_HOFF GOP_REG(GOP_4G_OFST, 0x70) 438 #define GOP_4G_RBLK1_HOFF GOP_REG(GOP_4G_OFST, 0x71) 439 #define GOP_4G_RBLK2_HOFF GOP_REG(GOP_4G_OFST, 0x72) 440 #define GOP_4G_RBLK3_HOFF GOP_REG(GOP_4G_OFST, 0x73) 441 #define GOP_4G_REGDMA_EN GOP_REG(GOP_4G_OFST, 0x78) 442 #define GOP_MUX_IPVOP __GOP_REG(0x77) 443 #define GOP_MUX4_MIX_VE __GOP_REG(0x7B) 444 #define GOP_BAK_SEL_EX __GOP_REG(0x7C) 445 #define GOP_MUX_4K2K __GOP_REG(0x7D) 446 #define GOP_MUX __GOP_REG(0x7e) 447 #define GOP_BAK_SEL __GOP_REG(0x7f) 448 449 #define GOP_4G_GWIN0_CTRL(id) GOP_REG(GOP_4G_OFST+1, 0x00 + (0x20*((id)%MAX_GOP0_GWIN))) 450 #define GOP_4G_DRAM_RBLK_L(id) GOP_REG(GOP_4G_OFST+1, 0x01 + (0x20*((id)%MAX_GOP0_GWIN))) 451 #define GOP_4G_DRAM_RBLK_H(id) GOP_REG(GOP_4G_OFST+1, 0x02 + (0x20*((id)%MAX_GOP0_GWIN))) 452 #define GOP_4G_DEL_PIXEL(id) GOP_REG(GOP_4G_OFST+1, 0x03 + (0x20*((id)%MAX_GOP1_GWIN))) 453 #define GOP_4G_HSTR(id) GOP_REG(GOP_4G_OFST+1, 0x04 + (0x20*((id)%MAX_GOP0_GWIN))) 454 #define GOP_4G_HEND(id) GOP_REG(GOP_4G_OFST+1, 0x05 + (0x20*((id)%MAX_GOP0_GWIN))) 455 #define GOP_4G_VSTR(id) GOP_REG(GOP_4G_OFST+1, 0x06 + (0x20*((id)%MAX_GOP0_GWIN))) 456 #define GOP_4G_GWIN_MIDDLE(id) GOP_REG(GOP_4G_OFST+1, 0x07 + (0x20*((id)%MAX_GOP0_GWIN))) 457 #define GOP_4G_VEND(id) GOP_REG(GOP_4G_OFST+1, 0x08 + (0x20*((id)%MAX_GOP0_GWIN))) 458 #define GOP_4G_DRAM_RBLK_HSIZE(id) GOP_REG(GOP_4G_OFST+1, 0x09 + (0x20*((id)%MAX_GOP0_GWIN))) 459 #define GOP_4G_GWIN_ALPHA01(id) GOP_REG(GOP_4G_OFST+1, 0x0A + (0x20*((id)%MAX_GOP0_GWIN))) 460 #define GOP_4G_DRAM_VSTR_L(id) GOP_REG(GOP_4G_OFST+1, 0x0C + (0x20*((id)%MAX_GOP0_GWIN))) 461 #define GOP_4G_DRAM_VSTR_H(id) GOP_REG(GOP_4G_OFST+1, 0x0D + (0x20*((id)%MAX_GOP0_GWIN))) 462 #define GOP_4G_DRAM_HSTR(id) GOP_REG(GOP_4G_OFST+1, 0x0E + (0x20*((id)%MAX_GOP0_GWIN))) 463 #define GOP_4G_DRAM_RBLK_SIZE_L(id) GOP_REG(GOP_4G_OFST+1, 0x10 + (0x20*((id)%MAX_GOP0_GWIN))) 464 #define GOP_4G_DRAM_RBLK_SIZE_H(id) GOP_REG(GOP_4G_OFST+1, 0x11 + (0x20*((id)%MAX_GOP0_GWIN))) 465 #define GOP_4G_DRAM_RLEN_L(id) GOP_REG(GOP_4G_OFST+1, 0x12 + (0x20*((id)%MAX_GOP0_GWIN))) 466 #define GOP_4G_DRAM_RLEN_H(id) GOP_REG(GOP_4G_OFST+1, 0x13 + (0x20*((id)%MAX_GOP0_GWIN))) 467 #define GOP_4G_DRAM_HVSTOP_L(id) GOP_REG(GOP_4G_OFST+1, 0x14 + (0x20*((id)%MAX_GOP0_GWIN))) 468 #define GOP_4G_DRAM_HVSTOP_H(id) GOP_REG(GOP_4G_OFST+1, 0x15 + (0x20*((id)%MAX_GOP0_GWIN))) 469 #define GOP_4G_DRAM_FADE(id) GOP_REG(GOP_4G_OFST+1, 0x16 + (0x20*((id)%MAX_GOP0_GWIN))) 470 #define GOP_4G_BG_CLR(id) GOP_REG(GOP_4G_OFST+1, 0x18 + (0x20*((id)%MAX_GOP0_GWIN))) 471 #define GOP_4G_BG_HSTR(id) GOP_REG(GOP_4G_OFST+1, 0x19 + (0x20*((id)%MAX_GOP0_GWIN))) 472 #define GOP_4G_BG_HEND(id) GOP_REG(GOP_4G_OFST+1, 0x1a + (0x20*((id)%MAX_GOP0_GWIN))) 473 #define GOP_4G_BG_VSTR(id) GOP_REG(GOP_4G_OFST+1, 0x1C + (0x20*((id)%MAX_GOP0_GWIN))) 474 #define GOP_4G_BG_VEND(id) GOP_REG(GOP_4G_OFST+1, 0x1D + (0x20*((id)%MAX_GOP0_GWIN))) 475 #define GOP_4G_3DOSD_SUB_RBLK_L(id) GOP_REG(GOP_4G_OFST+1, 0x1E + (0x20*((id)%MAX_GOP0_GWIN))) 476 #define GOP_4G_3DOSD_SUB_RBLK_H(id) GOP_REG(GOP_4G_OFST+1, 0x1F + (0x20*((id)%MAX_GOP0_GWIN))) 477 478 479 #define GOP_2G_CTRL0 GOP_REG(GOP_2G_OFST, 0x00) 480 #define GOP_2G_CTRL1 GOP_REG(GOP_2G_OFST, 0x01) 481 #define GOP_2G_RATE GOP_REG(GOP_2G_OFST, 0x02) 482 #define GOP_2G_PALDATA_L GOP_REG(GOP_2G_OFST, 0x03) 483 #define GOP_2G_PALDATA_H GOP_REG(GOP_2G_OFST, 0x04) 484 #define GOP_2G_PALCTRL GOP_REG(GOP_2G_OFST, 0x05) 485 #define GOP_2G_REGDMA_END GOP_REG(GOP_2G_OFST, 0x06) 486 #define GOP_2G_REGDMA_STR GOP_REG(GOP_2G_OFST, 0x07) 487 #define GOP_2G_INT GOP_REG(GOP_2G_OFST, 0x08) 488 #define GOP_2G_HWSTATE GOP_REG(GOP_2G_OFST, 0x09) 489 #define GOP_2G_RDMA_HT GOP_REG(GOP_2G_OFST, 0x0e) 490 #define GOP_2G_HS_PIPE GOP_REG(GOP_2G_OFST, 0x0f) 491 #define GOP_2G_SLOW GOP_REG(GOP_2G_OFST, 0x10) 492 #define GOP_2G_BRI GOP_REG(GOP_2G_OFST, 0x11) 493 #define GOP_2G_CON GOP_REG(GOP_2G_OFST, 0x12) 494 #define GOP_2G_BW GOP_REG(GOP_2G_OFST, 0x19) 495 #define GOP_2G_3D_MIDDLE GOP_REG(GOP_2G_OFST, 0x1E) 496 #define GOP_2G_PRI0 GOP_REG(GOP_2G_OFST, 0x20) 497 #define GOP_2G_TRSCLR_L GOP_REG(GOP_2G_OFST, 0x24) 498 #define GOP_2G_TRSCLR_H GOP_REG(GOP_2G_OFST, 0x25) 499 #define GOP_2G_STRCH_HSZ GOP_REG(GOP_2G_OFST, 0x30) 500 #define GOP_2G_STRCH_VSZ GOP_REG(GOP_2G_OFST, 0x31) 501 #define GOP_2G_STRCH_HSTR GOP_REG(GOP_2G_OFST, 0x32) 502 #define GOP_2G_STRCH_VSTR GOP_REG(GOP_2G_OFST, 0x34) 503 #define GOP_2G_HSTRCH GOP_REG(GOP_2G_OFST, 0x35) 504 #define GOP_2G_VSTRCH GOP_REG(GOP_2G_OFST, 0x36) 505 #define GOP_2G_HSTRCH_INI GOP_REG(GOP_2G_OFST, 0x38) 506 #define GOP_2G_VSTRCH_INI GOP_REG(GOP_2G_OFST, 0x39) 507 #define GOP_2G_HVStrch_MD GOP_REG(GOP_2G_OFST, 0x3a) 508 #define GOP_2G_OLDADDR GOP_REG(GOP_2G_OFST, 0x3b) 509 #define GOP_2G_MULTI_ALPHA GOP_REG(GOP_2G_OFST, 0x3c) 510 #define GOP_2G_REGDMA_EN GOP_REG(GOP_2G_OFST, 0x78) 511 512 513 #define GOP_2G_GWIN0_CTRL(id) GOP_REG(GOP_2G_OFST+1, 0x00 + (0x20*((id)%MAX_GOP1_GWIN))) 514 #define GOP_2G_GWIN_CTRL(id) GOP_REG(GOP_2G_OFST+1, 0x00 + (0x20*((id)%MAX_GOP1_GWIN))) 515 #define GOP_2G_DRAM_RBLK_L(id) GOP_REG(GOP_2G_OFST+1, 0x01 + (0x20*((id)%MAX_GOP1_GWIN))) 516 #define GOP_2G_DRAM_RBLK_H(id) GOP_REG(GOP_2G_OFST+1, 0x02 + (0x20*((id)%MAX_GOP1_GWIN))) 517 #define GOP_2G_DEL_PIXEL(id) GOP_REG(GOP_2G_OFST+1, 0x03 + (0x20*((id)%MAX_GOP1_GWIN))) 518 #define GOP_2G_HSTR(id) GOP_REG(GOP_2G_OFST+1, 0x04 + (0x20*((id)%MAX_GOP1_GWIN))) 519 #define GOP_2G_HEND(id) GOP_REG(GOP_2G_OFST+1, 0x05 + (0x20*((id)%MAX_GOP1_GWIN))) 520 #define GOP_2G_VSTR(id) GOP_REG(GOP_2G_OFST+1, 0x06 + (0x20*((id)%MAX_GOP1_GWIN))) 521 #define GOP_2G_VEND(id) GOP_REG(GOP_2G_OFST+1, 0x08 + (0x20*((id)%MAX_GOP1_GWIN))) 522 #define GOP_2G_DRAM_RBLK_HSIZE(id) GOP_REG(GOP_2G_OFST+1, 0x09 + (0x20*((id)%MAX_GOP1_GWIN))) 523 #define GOP_2G_GWIN_ALPHA01(id) GOP_REG(GOP_2G_OFST+1, 0x0A + (0x20*((id)%MAX_GOP1_GWIN))) 524 #define GOP_2G_DRAM_VSTR_L(id) GOP_REG(GOP_2G_OFST+1, 0x0C + (0x20*((id)%MAX_GOP1_GWIN))) 525 #define GOP_2G_DRAM_VSTR_H(id) GOP_REG(GOP_2G_OFST+1, 0x0D + (0x20*((id)%MAX_GOP1_GWIN))) 526 #define GOP_2G_DRAM_FADE(id) GOP_REG(GOP_2G_OFST+1, 0x16 + (0x20*((id)%MAX_GOP1_GWIN))) 527 #define GOP_2G_3DOSD_SUB_RBLK_L(id) GOP_REG(GOP_2G_OFST+1, 0x1E + (0x20*((id)%MAX_GOP1_GWIN))) 528 #define GOP_2G_3DOSD_SUB_RBLK_H(id) GOP_REG(GOP_2G_OFST+1, 0x1F + (0x20*((id)%MAX_GOP1_GWIN))) 529 530 // DWIN reg 531 #define GOP_DW_CTL0_EN GOP_REG(GOP_DW_OFST, 0x00) 532 #define GOP_DWIN_EN (0x00) 533 #define GOP_DWIN_EN_VAL GOP_REG_VAL(GOP_DWIN_EN) 534 #define GOP_DWIN_SHOT (0x07) 535 #define GOP_DWIN_SHOT_VAL GOP_REG_VAL(GOP_DWIN_SHOT) 536 537 #define GOP_DW_LSTR_WBE GOP_REG(GOP_DW_OFST, 0x01) 538 #define GOP_DW_INT_MASK GOP_REG(GOP_DW_OFST, 0x02) 539 #define GOP_DW_DEBUG GOP_REG(GOP_DW_OFST, 0x03) 540 #define GOP_DW_ALPHA GOP_REG(GOP_DW_OFST, 0x04) 541 #define GOP_DW_BW GOP_REG(GOP_DW_OFST, 0x05) 542 #define GOP_DW_VSTR GOP_REG(GOP_DW_OFST, 0x10) 543 #define GOP_DW_HSTR GOP_REG(GOP_DW_OFST, 0x11) 544 #define GOP_DW_VEND GOP_REG(GOP_DW_OFST, 0x12) 545 #define GOP_DW_HEND GOP_REG(GOP_DW_OFST, 0x13) 546 #define GOP_DW_HSIZE GOP_REG(GOP_DW_OFST, 0x14) 547 #define GOP_DW_JMPLEN GOP_REG(GOP_DW_OFST, 0x15) 548 #define GOP_DW_DSTR_L GOP_REG(GOP_DW_OFST, 0x16) 549 #define GOP_DW_DSTR_H GOP_REG(GOP_DW_OFST, 0x17) 550 #define GOP_DW_UB_L GOP_REG(GOP_DW_OFST, 0x18) 551 #define GOP_DW_UB_H GOP_REG(GOP_DW_OFST, 0x19) 552 553 #define GOP_DW_PON_DSTR_L GOP_REG(GOP_DW_OFST, 0x1a) 554 #define GOP_DW_PON_DSTR_H GOP_REG(GOP_DW_OFST, 0x1b) 555 #define GOP_DW_PON_UB_L GOP_REG(GOP_DW_OFST, 0x1c) 556 #define GOP_DW_PON_UB_H GOP_REG(GOP_DW_OFST, 0x1d) 557 #define GOP_DW_FRAME_CTRL GOP_REG(GOP_DW_OFST, 0x30) 558 559 #define GOP_1G_CTRL0 GOP_REG(GOP_1G_OFST, 0x00) 560 #define GOP_1G_CTRL1 GOP_REG(GOP_1G_OFST, 0x01) 561 #define GOP_1G_RATE GOP_REG(GOP_1G_OFST, 0x02) 562 #define GOP_1G_PALDATA_L GOP_REG(GOP_1G_OFST, 0x03) 563 #define GOP_1G_PALDATA_H GOP_REG(GOP_1G_OFST, 0x04) 564 #define GOP_1G_PALCTRL GOP_REG(GOP_1G_OFST, 0x05) 565 #define GOP_1G_REGDMA_END GOP_REG(GOP_1G_OFST, 0x06) 566 #define GOP_1G_REGDMA_STR GOP_REG(GOP_1G_OFST, 0x07) 567 #define GOP_1G_INT GOP_REG(GOP_1G_OFST, 0x08) 568 #define GOP_1G_HWSTATE GOP_REG(GOP_1G_OFST, 0x09) 569 #define GOP_1G_RDMA_HT GOP_REG(GOP_1G_OFST, 0x0e) 570 #define GOP_1G_HS_PIPE GOP_REG(GOP_1G_OFST, 0x0f) 571 #define GOP_1G_BRI GOP_REG(GOP_1G_OFST, 0x11) 572 #define GOP_1G_CON GOP_REG(GOP_1G_OFST, 0x12) 573 #define GOP_1G_BW GOP_REG(GOP_1G_OFST, 0x19) 574 #define GOP_1G_3D_MIDDLE GOP_REG(GOP_1G_OFST, 0x1E) 575 #define GOP_1G_TRSCLR_L GOP_REG(GOP_1G_OFST, 0x24) 576 #define GOP_1G_TRSCLR_H GOP_REG(GOP_1G_OFST, 0x25) 577 #define GOP_1G_STRCH_HSZ GOP_REG(GOP_1G_OFST, 0x30) 578 #define GOP_1G_STRCH_VSZ GOP_REG(GOP_1G_OFST, 0x31) 579 #define GOP_1G_STRCH_HSTR GOP_REG(GOP_1G_OFST, 0x32) 580 #define GOP_1G_STRCH_VSTR GOP_REG(GOP_1G_OFST, 0x34) 581 #define GOP_1G_HSTRCH GOP_REG(GOP_1G_OFST, 0x35) 582 #define GOP_1G_HSTRCH_INI GOP_REG(GOP_1G_OFST, 0x38) 583 #define GOP_1G_VSTRCH_INI GOP_REG(GOP_1G_OFST, 0x39) 584 #define GOP_1G_HStrch_MD GOP_REG(GOP_1G_OFST, 0x3a) 585 #define GOP_1G_OLDADDR GOP_REG(GOP_1G_OFST, 0x3b) 586 #define GOP_1G_MULTI_ALPHA GOP_REG(GOP_1G_OFST, 0x3c) 587 588 #define GOP_1G_GWIN0_CTRL GOP_REG(GOP_1G_OFST+1, 0x0) 589 #define GOP_1G_DRAM_RBLK_L GOP_REG(GOP_1G_OFST+1, 0x1) 590 #define GOP_1G_DRAM_RBLK_H GOP_REG(GOP_1G_OFST+1, 0x2) 591 #define GOP_1G_DEL_PIXEL GOP_REG(GOP_1G_OFST+1, 0x3) 592 #define GOP_1G_HSTR GOP_REG(GOP_1G_OFST+1, 0x4) 593 #define GOP_1G_HEND GOP_REG(GOP_1G_OFST+1, 0x5) 594 #define GOP_1G_VSTR GOP_REG(GOP_1G_OFST+1, 0x6) 595 #define GOP_1G_VEND GOP_REG(GOP_1G_OFST+1, 0x8) 596 #define GOP_1G_DRAM_RBLK_HSIZE GOP_REG(GOP_1G_OFST+1, 0x9) 597 #define GOP_1G_GWIN_ALPHA01 GOP_REG(GOP_1G_OFST+1, 0xA) 598 #define GOP_1G_DRAM_VSTR_L GOP_REG(GOP_1G_OFST+1, 0x0C) 599 #define GOP_1G_DRAM_VSTR_H GOP_REG(GOP_1G_OFST+1, 0x0D) 600 #define GOP_1G_DRAM_FADE GOP_REG(GOP_1G_OFST+1, 0x16) 601 #define GOP_1G_3DOSD_SUB_RBLK_L GOP_REG(GOP_1G_OFST+1, 0x1E) 602 #define GOP_1G_3DOSD_SUB_RBLK_H GOP_REG(GOP_1G_OFST+1, 0x1F) 603 604 #define GOP_1GX_CTRL0 GOP_REG(GOP_1GX_OFST, 0x00) 605 #define GOP_1GX_CTRL1 GOP_REG(GOP_1GX_OFST, 0x01) 606 #define GOP_1GX_RATE GOP_REG(GOP_1GX_OFST, 0x02) 607 #define GOP_1GX_PALDATA_L GOP_REG(GOP_1GX_OFST, 0x03) 608 #define GOP_1GX_PALDATA_H GOP_REG(GOP_1GX_OFST, 0x04) 609 #define GOP_1GX_PALCTRL GOP_REG(GOP_1GX_OFST, 0x05) 610 #define GOP_1GX_REGDMA_END GOP_REG(GOP_1GX_OFST, 0x06) 611 #define GOP_1GX_REGDMA_STR GOP_REG(GOP_1GX_OFST, 0x07) 612 #define GOP_1GX_INT GOP_REG(GOP_1GX_OFST, 0x08) 613 #define GOP_1GX_HWSTATE GOP_REG(GOP_1GX_OFST, 0x09) 614 #define GOP_1GX_RDMA_HT GOP_REG(GOP_1GX_OFST, 0x0e) 615 #define GOP_1GX_HS_PIPE GOP_REG(GOP_1GX_OFST, 0x0f) 616 #define GOP_1GX_BRI GOP_REG(GOP_1GX_OFST, 0x11) 617 #define GOP_1GX_CON GOP_REG(GOP_1GX_OFST, 0x12) 618 #define GOP_1GX_BW GOP_REG(GOP_1GX_OFST, 0x19) 619 #define GOP_1GX_3D_MIDDLE GOP_REG(GOP_1GX_OFST, 0x1E) 620 #define GOP_1GX_TRSCLR_L GOP_REG(GOP_1GX_OFST, 0x24) 621 #define GOP_1GX_TRSCLR_H GOP_REG(GOP_1GX_OFST, 0x25) 622 #define GOP_1GX_STRCH_HSZ GOP_REG(GOP_1GX_OFST, 0x30) 623 #define GOP_1GX_STRCH_VSZ GOP_REG(GOP_1GX_OFST, 0x31) 624 #define GOP_1GX_STRCH_HSTR GOP_REG(GOP_1GX_OFST, 0x32) 625 #define GOP_1GX_STRCH_VSTR GOP_REG(GOP_1GX_OFST, 0x34) 626 #define GOP_1GX_HSTRCH GOP_REG(GOP_1GX_OFST, 0x35) 627 #define GOP_1GX_HSTRCH_INI GOP_REG(GOP_1GX_OFST, 0x38) 628 #define GOP_1GX_VSTRCH_INI GOP_REG(GOP_1GX_OFST, 0x39) 629 #define GOP_1GX_HStrch_MD GOP_REG(GOP_1GX_OFST, 0x3a) 630 #define GOP_1GX_OLDADDR GOP_REG(GOP_1GX_OFST, 0x3b) 631 #define GOP_1GX_MULTI_ALPHA GOP_REG(GOP_1GX_OFST, 0x3c) 632 633 #define GOP_1GX_GWIN0_CTRL GOP_REG(GOP_1GX_OFST+1, 0x00) 634 #define GOP_1GX_DRAM_RBLK_L GOP_REG(GOP_1GX_OFST+1, 0x01) 635 #define GOP_1GX_DRAM_RBLK_H GOP_REG(GOP_1GX_OFST+1, 0x02) 636 #define GOP_1GX_DEL_PIXEL GOP_REG(GOP_1GX_OFST+1, 0x03) 637 #define GOP_1GX_HSTR GOP_REG(GOP_1GX_OFST+1, 0x04) 638 #define GOP_1GX_HEND GOP_REG(GOP_1GX_OFST+1, 0x05) 639 #define GOP_1GX_VSTR GOP_REG(GOP_1GX_OFST+1, 0x06) 640 #define GOP_1GX_VEND GOP_REG(GOP_1GX_OFST+1, 0x08) 641 #define GOP_1GX_DRAM_RBLK_HSIZE GOP_REG(GOP_1GX_OFST+1, 0x09) 642 #define GOP_1GX_GWIN_ALPHA01 GOP_REG(GOP_1GX_OFST+1, 0x0A) 643 #define GOP_1GX_DRAM_VSTR_L GOP_REG(GOP_1GX_OFST+1, 0x0C) 644 #define GOP_1GX_DRAM_VSTR_H GOP_REG(GOP_1GX_OFST+1, 0x0D) 645 #define GOP_1GX_DRAM_FADE GOP_REG(GOP_1GX_OFST+1, 0x16) 646 #define GOP_1GX_3DOSD_SUB_RBLK_L GOP_REG(GOP_1GX_OFST+1, 0x1E) 647 #define GOP_1GX_3DOSD_SUB_RBLK_H GOP_REG(GOP_1GX_OFST+1, 0x1F) 648 649 #define GOP_1GS0_CTRL0 GOP_REG(GOP_1GS0_OFST, 0x00) 650 #define GOP_1GS0_CTRL1 GOP_REG(GOP_1GS0_OFST, 0x01) 651 #define GOP_1GS0_RATE GOP_REG(GOP_1GS0_OFST, 0x02) 652 #define GOP_1GS0_PALDATA_L GOP_REG(GOP_1GS0_OFST, 0x03) 653 #define GOP_1GS0_PALDATA_H GOP_REG(GOP_1GS0_OFST, 0x04) 654 #define GOP_1GS0_PALCTRL GOP_REG(GOP_1GS0_OFST, 0x05) 655 #define GOP_1GS0_REGDMA_END GOP_REG(GOP_1GS0_OFST, 0x06) 656 #define GOP_1GS0_REGDMA_STR GOP_REG(GOP_1GS0_OFST, 0x07) 657 #define GOP_1GS0_INT GOP_REG(GOP_1GS0_OFST, 0x08) 658 #define GOP_1GS0_HWSTATE GOP_REG(GOP_1GS0_OFST, 0x09) 659 #define GOP_1GS0_RDMA_HT GOP_REG(GOP_1GS0_OFST, 0x0e) 660 #define GOP_1GS0_HS_PIPE GOP_REG(GOP_1GS0_OFST, 0x0f) 661 #define GOP_1GS0_BRI GOP_REG(GOP_1GS0_OFST, 0x11) 662 #define GOP_1GS0_CON GOP_REG(GOP_1GS0_OFST, 0x12) 663 #define GOP_1GS0_BW GOP_REG(GOP_1GS0_OFST, 0x19) 664 #define GOP_1GS0_TRSCLR_L GOP_REG(GOP_1GS0_OFST, 0x24) 665 #define GOP_1GS0_TRSCLR_H GOP_REG(GOP_1GS0_OFST, 0x25) 666 #define GOP_1GS0_STRCH_HSZ GOP_REG(GOP_1GS0_OFST, 0x30) 667 #define GOP_1GS0_STRCH_VSZ GOP_REG(GOP_1GS0_OFST, 0x31) 668 #define GOP_1GS0_STRCH_HSTR GOP_REG(GOP_1GS0_OFST, 0x32) 669 #define GOP_1GS0_STRCH_VSTR GOP_REG(GOP_1GS0_OFST, 0x34) 670 #define GOP_1GS0_HSTRCH GOP_REG(GOP_1GS0_OFST, 0x35) 671 #define GOP_1GS0_HSTRCH_INI GOP_REG(GOP_1GS0_OFST, 0x38) 672 #define GOP_1GS0_VSTRCH_INI GOP_REG(GOP_1GS0_OFST, 0x39) 673 #define GOP_1GS0_HVStrch_MD GOP_REG(GOP_1GS0_OFST, 0x3a) 674 #define GOP_1GS0_OLDADDR GOP_REG(GOP_1GS0_OFST, 0x3b) 675 #define GOP_1GS0_MULTI_ALPHA GOP_REG(GOP_1GS0_OFST, 0x3c) 676 677 #define GOP_1GS0_GWIN0_CTRL GOP_REG(GOP_1GS0_OFST+1, 0x00) 678 #define GOP_1GS0_DRAM_RBLK_L GOP_REG(GOP_1GS0_OFST+1, 0x01) 679 #define GOP_1GS0_DRAM_RBLK_H GOP_REG(GOP_1GS0_OFST+1, 0x02) 680 #define GOP_1GS0_DEL_PIXEL GOP_REG(GOP_1GS0_OFST+1, 0x03) 681 #define GOP_1GS0_HSTR GOP_REG(GOP_1GS0_OFST+1, 0x04) 682 #define GOP_1GS0_HEND GOP_REG(GOP_1GS0_OFST+1, 0x05) 683 #define GOP_1GS0_VSTR GOP_REG(GOP_1GS0_OFST+1, 0x06) 684 #define GOP_1GS0_VEND GOP_REG(GOP_1GS0_OFST+1, 0x08) 685 #define GOP_1GS0_DRAM_RBLK_HSIZE GOP_REG(GOP_1GS0_OFST+1, 0x09) 686 #define GOP_1GS0_GWIN_ALPHA01 GOP_REG(GOP_1GS0_OFST+1, 0x0A) 687 #define GOP_1GS0_DRAM_VSTR_L GOP_REG(GOP_1GS0_OFST+1, 0x0C) 688 #define GOP_1GS0_DRAM_VSTR_H GOP_REG(GOP_1GS0_OFST+1, 0x0D) 689 #define GOP_1GS0_DRAM_FADE GOP_REG(GOP_1GS0_OFST+1, 0x16) 690 #define GOP_1GS0_3DOSD_SUB_RBLK_L GOP_REG(GOP_1GS0_OFST+1, 0x1E) 691 #define GOP_1GS0_3DOSD_SUB_RBLK_H GOP_REG(GOP_1GS0_OFST+1, 0x1F) 692 693 #define GOP_1GS1_CTRL0 GOP_REG(GOP_1GS1_OFST, 0x00) 694 #define GOP_1GS1_CTRL1 GOP_REG(GOP_1GS1_OFST, 0x01) 695 #define GOP_1GS1_RATE GOP_REG(GOP_1GS1_OFST, 0x02) 696 #define GOP_1GS1_PALDATA_L GOP_REG(GOP_1GS1_OFST, 0x03) 697 #define GOP_1GS1_PALDATA_H GOP_REG(GOP_1GS1_OFST, 0x04) 698 #define GOP_1GS1_PALCTRL GOP_REG(GOP_1GS1_OFST, 0x05) 699 #define GOP_1GS1_REGDMA_END GOP_REG(GOP_1GS1_OFST, 0x06) 700 #define GOP_1GS1_REGDMA_STR GOP_REG(GOP_1GS1_OFST, 0x07) 701 #define GOP_1GS1_INT GOP_REG(GOP_1GS1_OFST, 0x08) 702 #define GOP_1GS1_HWSTATE GOP_REG(GOP_1GS1_OFST, 0x09) 703 #define GOP_1GS1_RDMA_HT GOP_REG(GOP_1GS1_OFST, 0x0e) 704 #define GOP_1GS1_HS_PIPE GOP_REG(GOP_1GS1_OFST, 0x0f) 705 #define GOP_1GS1_BRI GOP_REG(GOP_1GS1_OFST, 0x11) 706 #define GOP_1GS1_CON GOP_REG(GOP_1GS1_OFST, 0x12) 707 #define GOP_1GS1_BW GOP_REG(GOP_1GS1_OFST, 0x19) 708 #define GOP_1GS1_TRSCLR_L GOP_REG(GOP_1GS1_OFST, 0x24) 709 #define GOP_1GS1_TRSCLR_H GOP_REG(GOP_1GS1_OFST, 0x25) 710 #define GOP_1GS1_STRCH_HSZ GOP_REG(GOP_1GS1_OFST, 0x30) 711 #define GOP_1GS1_STRCH_VSZ GOP_REG(GOP_1GS1_OFST, 0x31) 712 #define GOP_1GS1_STRCH_HSTR GOP_REG(GOP_1GS1_OFST, 0x32) 713 #define GOP_1GS1_STRCH_VSTR GOP_REG(GOP_1GS1_OFST, 0x34) 714 #define GOP_1GS1_HSTRCH GOP_REG(GOP_1GS1_OFST, 0x35) 715 #define GOP_1GS1_HSTRCH_INI GOP_REG(GOP_1GS1_OFST, 0x38) 716 #define GOP_1GS1_VSTRCH_INI GOP_REG(GOP_1GS1_OFST, 0x39) 717 #define GOP_1GS1_HVStrch_MD GOP_REG(GOP_1GS1_OFST, 0x3a) 718 #define GOP_1GS1_OLDADDR GOP_REG(GOP_1GS1_OFST, 0x3b) 719 #define GOP_1GS1_MULTI_ALPHA GOP_REG(GOP_1GS1_OFST, 0x3c) 720 721 #define GOP_1GS1_GWIN0_CTRL GOP_REG(GOP_1GS1_OFST+1, 0x00) 722 #define GOP_1GS1_DRAM_RBLK_L GOP_REG(GOP_1GS1_OFST+1, 0x01) 723 #define GOP_1GS1_DRAM_RBLK_H GOP_REG(GOP_1GS1_OFST+1, 0x02) 724 #define GOP_1GS1_DEL_PIXEL GOP_REG(GOP_1GS1_OFST+1, 0x03) 725 #define GOP_1GS1_HSTR GOP_REG(GOP_1GS1_OFST+1, 0x04) 726 #define GOP_1GS1_HEND GOP_REG(GOP_1GS1_OFST+1, 0x05) 727 #define GOP_1GS1_VSTR GOP_REG(GOP_1GS1_OFST+1, 0x06) 728 #define GOP_1GS1_VEND GOP_REG(GOP_1GS1_OFST+1, 0x08) 729 #define GOP_1GS1_DRAM_RBLK_HSIZE GOP_REG(GOP_1GS1_OFST+1, 0x09) 730 #define GOP_1GS1_GWIN_ALPHA01 GOP_REG(GOP_1GS1_OFST+1, 0x0A) 731 #define GOP_1GS1_DRAM_VSTR_L GOP_REG(GOP_1GS1_OFST+1, 0x0C) 732 #define GOP_1GS1_DRAM_VSTR_H GOP_REG(GOP_1GS1_OFST+1, 0x0D) 733 #define GOP_1GS1_DRAM_FADE GOP_REG(GOP_1GS1_OFST+1, 0x16) 734 #define GOP_1GS1_3DOSD_SUB_RBLK_L GOP_REG(GOP_1GS1_OFST+1, 0x1E) 735 #define GOP_1GS1_3DOSD_SUB_RBLK_H GOP_REG(GOP_1GS1_OFST+1, 0x1F) 736 //------------------------------------------------------------------------------------------------- 737 // Type and Structure 738 //------------------------------------------------------------------------------------------------- 739 740 //---------------------------------------------------------------------------- 741 // GOP Test Pattern Reg 742 //---------------------------------------------------------------------------- 743 #define REG_TSTCLR_EN GOP_REG(GOP_4G_OFST, 0x00) 744 #define REG_TSTCLR_ALPHA_EN GOP_REG(GOP_4G_OFST+2, 0x00) 745 #define REG_TLB_TAG_ADDR_L GOP_REG(GOP_4G_OFST+2, 0x2C) 746 #define REG_TLB_TAG_ADDR_H GOP_REG(GOP_4G_OFST+2, 0x2D) 747 #define REG_TLB_TAG_ADDR_RVIEW_L GOP_REG(GOP_4G_OFST+2, 0x2E) 748 #define REG_TLB_TAG_ADDR_RVIEW_H GOP_REG(GOP_4G_OFST+2, 0x2F) 749 #define REG_TSTCLR_ALPHA GOP_REG(GOP_4G_OFST+2, 0x40) 750 #define REG_R_STC GOP_REG(GOP_4G_OFST+2, 0x41) 751 #define REG_G_STC GOP_REG(GOP_4G_OFST+2, 0x48) 752 #define REG_B_STC GOP_REG(GOP_4G_OFST+2, 0x49) 753 #define REG_TSTCLR_HDUP GOP_REG(GOP_4G_OFST+2, 0x01) 754 #define REG_TSTCLR_VDUP GOP_REG(GOP_4G_OFST+2, 0x01) 755 #define REG_HR_INC GOP_REG(GOP_4G_OFST+2, 0x42) 756 #define REG_HR_INC_SIGNZ GOP_REG(GOP_4G_OFST+2, 0x42) 757 #define REG_HG_INC GOP_REG(GOP_4G_OFST+2, 0x43) 758 #define REG_HG_INC_SIGNZ GOP_REG(GOP_4G_OFST+2, 0x43) 759 #define REG_HB_INC GOP_REG(GOP_4G_OFST+2, 0x44) 760 #define REG_HB_INC_SIGNZ GOP_REG(GOP_4G_OFST+2, 0x44) 761 #define REG_HR_STEP GOP_REG(GOP_4G_OFST+2, 0x4A) 762 #define REG_HG_STEP GOP_REG(GOP_4G_OFST+2, 0x4B) 763 #define REG_HB_STEP GOP_REG(GOP_4G_OFST+2, 0x4C) 764 #define REG_VR_INC GOP_REG(GOP_4G_OFST+2, 0x45) 765 #define REG_VR_INC_SIGNZ GOP_REG(GOP_4G_OFST+2, 0x45) 766 #define REG_VG_INC GOP_REG(GOP_4G_OFST+2, 0x46) 767 #define REG_VG_INC_SIGNZ GOP_REG(GOP_4G_OFST+2, 0x46) 768 #define REG_VB_INC GOP_REG(GOP_4G_OFST+2, 0x47) 769 #define REG_VB_INC_SIGNZ GOP_REG(GOP_4G_OFST+2, 0x47) 770 #define REG_VR_STEP GOP_REG(GOP_4G_OFST+2, 0x4D) 771 #define REG_VG_STEP GOP_REG(GOP_4G_OFST+2, 0x4E) 772 #define REG_VB_STEP GOP_REG(GOP_4G_OFST+2, 0x4F) 773 #define REG_TLB_BASE_ADDR_L GOP_REG(GOP_4G_OFST+2, 0x58) 774 #define REG_TLB_BASE_ADDR_H GOP_REG(GOP_4G_OFST+2, 0x59) 775 #define REG_TLB_BASE_ADDR_RVIEW_L GOP_REG(GOP_4G_OFST+2, 0x5A) 776 #define REG_TLB_BASE_ADDR_RVIEW_H GOP_REG(GOP_4G_OFST+2, 0x5B) 777 778 #define MASK_TSTCLR_EN GOP_BIT6 779 #define MASK_TSTCLR_ALPHA_EN GOP_BIT1 780 #define MASK_TSTCLR_ALPHA BMASK(11:8)|BMASK(3:0) 781 #define MASK_RGB_STC_VALID BMASK(7:0) 782 #define MASK_R_STC BMASK(11:8)|BMASK(3:0) 783 #define MASK_G_STC BMASK(11:8)|BMASK(3:0) 784 #define MASK_B_STC BMASK(11:8)|BMASK(3:0) 785 #define MASK_INI_TSTCLR_EN GOP_BIT0 786 #define MASK_TSTCLR_HDUP BMASK(3:2) 787 #define MASK_TSTCLR_VDUP BMASK(1:0) 788 #define MASK_HR_INC BMASK(10:8)|BMASK(3:0) 789 #define MASK_HR_INC_SIGNZ GOP_BIT11 790 #define MASK_HG_INC BMASK(10:8)|BMASK(3:0) 791 #define MASK_HG_INC_SIGNZ GOP_BIT11 792 #define MASK_HB_INC BMASK(10:8)|BMASK(3:0) 793 #define MASK_HB_INC_SIGNZ GOP_BIT11 794 #define MASK_HR_STEP BMASK(11:8)|BMASK(3:0) 795 #define MASK_HG_STEP BMASK(11:8)|BMASK(3:0) 796 #define MASK_HB_STEP BMASK(11:8)|BMASK(3:0) 797 #define MASK_VR_INC BMASK(10:8)|BMASK(3:0) 798 #define MASK_VR_INC_SIGNZ GOP_BIT11 799 #define MASK_VG_INC BMASK(10:8)|BMASK(3:0) 800 #define MASK_VG_INC_SIGNZ GOP_BIT11 801 #define MASK_VB_INC BMASK(10:8)|BMASK(3:0) 802 #define MASK_VB_INC_SIGNZ GOP_BIT11 803 #define MASK_VR_STEP BMASK(11:8)|BMASK(3:0) 804 #define MASK_VG_STEP BMASK(11:8)|BMASK(3:0) 805 #define MASK_VB_STEP BMASK(11:8)|BMASK(3:0) 806 807 #define SHIFT_TSTCLR_EN 6 808 #define SHIFT_TSTCLR_ALPHA_EN 1 809 #define SHIFT_TSTCLR_ALPHA 8 810 #define SHIFT_R_STC 0 811 #define SHIFT_G_STC 0 812 #define SHIFT_B_STC 0 813 #define SHIFT_INI_TSTCLR_EN 0 814 #define SHIFT_TSTCLR_HDUP 2 815 #define SHIFT_TSTCLR_VDUP 0 816 #define SHIFT_HR_INC 0 817 #define SHIFT_HR_INC_SIGNZ 11 818 #define SHIFT_HG_INC 0 819 #define SHIFT_HG_INC_SIGNZ 11 820 #define SHIFT_HB_INC 0 821 #define SHIFT_HB_INC_SIGNZ 11 822 #define SHIFT_HR_STEP 0 823 #define SHIFT_HG_STEP 0 824 #define SHIFT_HB_STEP 0 825 #define SHIFT_VR_INC 0 826 #define SHIFT_VR_INC_SIGNZ 11 827 #define SHIFT_VG_INC 0 828 #define SHIFT_VG_INC_SIGNZ 11 829 #define SHIFT_VB_INC 0 830 #define SHIFT_VB_INC_SIGNZ 11 831 #define SHIFT_VR_STEP 0 832 #define SHIFT_VG_STEP 0 833 #define SHIFT_VB_STEP 0 834 #endif // _REG_GOP_H_ 835