1 //<MStar Software>
2 //******************************************************************************
3 // MStar Software
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76 //******************************************************************************
77 //<MStar Software>
78 ////////////////////////////////////////////////////////////////////////////////
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92 //
93 ////////////////////////////////////////////////////////////////////////////////
94
95 #include "MsCommon.h"
96 #ifndef MSOS_TYPE_LINUX_KERNEL
97 #include <string.h>
98 #endif
99 #include "MsTypes.h"
100 #include "halGOP.h"
101 #include "regGOP.h"
102 #include "halCHIP.h"
103 #include "drvSYS.h"
104
105 //------------------------------------------------------------------------------
106 // Driver Compiler Options
107 //------------------------------------------------------------------------------
108 #define HAL_GOP_DEBUGINFO(x) //x
109
110 //------------------------------------------------------------------------------
111 // Local Defines
112 //------------------------------------------------------------------------------
113 #define RIU ((unsigned short volatile *) pGOPHalLocal->va_mmio_base)
114 #define GOP_WRITE2BYTE(addr, val) { RIU[addr] = val; }
115 #define GOP_READ2BYTE(addr) RIU[addr]
116 #define GOP_BANK_MASK 0x1FUL
117 #define GOP_DST_MASK 0xFUL
118
119 //Kastor have 5 GOP(s):GOP0 GOP1 GOP2 GOP3 GOP5
120 //The last gop num is 4 for API,but 5 needs to be set for register
121 //So we need to do a conversion.
122 #define GOPNUM_SW_MAX_ID (4UL)
123 #define GOPNUM_HW_MAX_ID (5UL)
124 #define GOPNUM_TRANSFORM(num) (((num) == GOPNUM_SW_MAX_ID) ? GOPNUM_HW_MAX_ID : (num))
125 #define GOPNUM_TRANSFORM_INVERSE(num) (((num) == GOPNUM_HW_MAX_ID) ? GOPNUM_SW_MAX_ID : (num))
126
127
128 //------------------------------------------------------------------------------
129 // Local Var
130 //------------------------------------------------------------------------------
131 MS_BOOL bIsMuxVaildToGopDst[MAX_GOP_MUX][MAX_DRV_GOP_DST_SUPPORT] =
132 {
133 /*IP0, IP0_SUB, MIXER2VE, OP0, VOP, IP1, IP1_SUB, MIXER2OP*/
134 {TRUE, FALSE, FALSE, TRUE, TRUE, FALSE, FALSE, FALSE}, /*All Gop Dst case is vaild or FALSE for mux 0 */
135 {TRUE, FALSE, FALSE, FALSE, TRUE, FALSE, FALSE, FALSE}, /*All Gop Dst case is vaild or FALSE for mux 1 */
136 {TRUE, FALSE, FALSE, TRUE, TRUE, FALSE, FALSE, FALSE}, /*All Gop Dst case is vaild or FALSE for mux 0 */
137 {TRUE, FALSE, FALSE, TRUE, TRUE, FALSE, FALSE, FALSE}, /*All Gop Dst case is vaild or FALSE for mux 0 */
138 };
139 #ifdef GOP_CMDQ_ENABLE
140 extern MS_U16 u16MIUSelect[MAX_GOP_SUPPORT];
141 extern MS_BOOL bMIUSelect[MAX_GOP_SUPPORT];
142
143 extern MS_U16 u16AFBCMIUSelect[MAX_GOP_SUPPORT];
144 extern MS_BOOL bAFBCMIUSelect[MAX_GOP_SUPPORT];
145 #endif
146 GOP_CHIP_PROPERTY g_GopChipPro =
147 {
148 .bSetHSyncInverse = FALSE,
149 .bGop1GPalette = TRUE,
150 .bSetHPipeOfst = FALSE,
151 .bNeedCheckMVOP = FALSE,
152 .bNeedSetMUX1ToIP0 = FALSE,
153 .bNeedSetMUX3ToIP0 = FALSE,
154 .bNewMux = TRUE,
155 .bNewPalette = TRUE,
156 .bNewBwReg = TRUE,
157 .bGop2VStretch = TRUE,
158 .bIgnoreIPHPD = TRUE, //Uranus4 has handshack with XC, should not set HPD
159 .bIgnoreVEHPD = FALSE, //Uranus4 to VE through Mixer, do not need adjust HPD
160 .bhastilemode = TRUE,
161 .bInitNotEnableGOPToSC = FALSE, //For Uranus4 mux init setting, enable GOP to SC in GOP init would cause problem
162 .bAutoAdjustMirrorHSize = TRUE, //whether hw will auto adjust start addr when H mirror is enable
163 .bGOPWithVscale = {TRUE, TRUE, TRUE, FALSE, TRUE}, //setting GOP with/without Vscale
164
165 .bDWINSupport = FALSE,
166 .DwinVer = 0x1,
167 .bTstPatternAlpha = TRUE,
168 .bXCDirrectBankSupport = TRUE, /*XC Dirrect Bank R/W*/
169 .bFRCSupport = FALSE, /*OC path*/
170 .bGOPMixerToVE= TRUE, /*Mixer to VE path*/
171 .bBnkForceWrite = TRUE, /*Direct Bank Force Write*/
172 .bPixelModeSupport = TRUE, /*Pixel Mode Support*/
173 .bScalingDownSupport= FALSE,
174 .b2Pto1PSupport= TRUE,
175 .bTLBSupport= {TRUE, FALSE, TRUE, TRUE, FALSE, FALSE},
176 .GOP_TestPattern_Vaild= E_GOP0,
177 .bInternalMIUSelect= {TRUE, TRUE, TRUE, TRUE, TRUE, FALSE, FALSE, FALSE}, //{E_GOP0, E_GOP1, E_GOP2, E_GOP3, E_GOP4, E_GOP_Dwin, E_GOP_MIXER, E_GOP5}
178 .bAFBC_Support= {FALSE, FALSE, FALSE, FALSE, FALSE},
179
180 #ifdef ENABLE_GOP_T3DPATCH
181 .GOP_PD = -0x42,
182 #else
183 .GOP_PD = 0xDB,
184 #endif
185 .GOP_HDR_OP_PD = -0x39,
186 .GOP_IP_PD = 0x00,
187 .GOP_MVOP_PD = 0x69,
188 .GOP_VE_PD = 0x89,
189 .GOP_MIXER_PD = 0x0,
190 .GOP_NonVS_PD_Offset = 0x5, //GOP without Vsacle might need add offset on pipedelay
191 .GOP_VE_V_Offset = 0x0,
192 .GOP_OP1_PD = 0xBC,
193
194 .GOP_MUX_Delta = 0x4,
195 .GOP_Mux_Offset = {0x0, 0x1, 0x2, 0x3, 0x4},
196 .GOP_MapLayer2Mux = {E_GOP_MUX0, E_GOP_MUX1, E_GOP_MUX2, E_GOP_MUX3, E_GOP_MUX4},
197 .GOP_Mux_FRC_offset= 0x13,
198
199 .WordUnit = GOP_WordUnit,
200 .TotalGwinNum = GOP_TotalGwinNum,
201 .Default_ConsAlpha_bits = DRV_VALID_8BITS,
202 .enGOP3DType = E_DRV_3D_DUP_FULL,
203 .bOpInterlace = FALSE,
204 .bAFBC_Merge_GOP_Trig = FALSE,
205 .bGOPVscalePipeDelay = {FALSE, FALSE, FALSE, TRUE, FALSE, FALSE},
206 .bOPHandShakeModeSupport = FALSE,
207 .bIgnoreIP1HPD = TRUE,
208 .bOPMuxDoubleBuffer = FALSE,
209 .bGOPAutoClkGating = TRUE,
210 };
211
212
213 //------------------------------------------------------------------------------
214 // Global Functions
215 //------------------------------------------------------------------------------
HAL_GOP_GetGOPEnum(GOP_CTX_HAL_LOCAL * pGOPHalLocal,GOP_TYPE_DEF * GOP_TYPE)216 void HAL_GOP_GetGOPEnum(GOP_CTX_HAL_LOCAL *pGOPHalLocal, GOP_TYPE_DEF* GOP_TYPE)
217 {
218 GOP_TYPE->GOP0 = E_GOP0;
219 GOP_TYPE->GOP1 = E_GOP1;
220 GOP_TYPE->GOP2 = E_GOP2;
221 GOP_TYPE->GOP3 = E_GOP3;
222 GOP_TYPE->GOP4 = E_GOP4;
223 GOP_TYPE->GOP5 = E_GOP5;
224 GOP_TYPE->DWIN = E_GOP_Dwin;
225 GOP_TYPE->MIXER = E_GOP_MIXER;
226 }
227
HAL_GOP_SetWinFmt(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_U8 regForm,MS_U8 u8GOPNum,MS_U8 u8GwinNum,MS_U16 colortype)228 GOP_Result HAL_GOP_SetWinFmt(GOP_CTX_HAL_LOCAL *pGOPHalLocal, MS_U8 regForm, MS_U8 u8GOPNum, MS_U8 u8GwinNum, MS_U16 colortype)
229 {
230 MS_U32 u32BankOffSet = 0;
231
232 _GetBnkOfstByGop(u8GOPNum, &u32BankOffSet);
233
234 if (((regForm & E_GOP_REG_FORM_MASK) == E_GOP_REG_FORM_T21G) || ((regForm & E_GOP_REG_FORM_MASK) == E_GOP_REG_FORM_T81G))
235 {
236 HAL_GOP_Write16Reg(pGOPHalLocal, u32BankOffSet + GOP_4G_GWIN0_CTRL(Gop23_GwinCtl_Ofet), colortype, GOP_REG_COLORTYPE_MASK<<GOP_REG_COLORTYPE_SHIFT);
237 }
238 else
239 {
240 HAL_GOP_Write16Reg(pGOPHalLocal, u32BankOffSet + GOP_4G_GWIN0_CTRL(u8GwinNum), colortype, GOP_REG_COLORTYPE_MASK<<GOP_REG_COLORTYPE_SHIFT);
241 }
242
243 return GOP_SUCCESS;
244 }
245
HAL_GOP_Set_PINPON(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_U8 u8GOPNum,MS_BOOL bEn,E_DRV_GOP_PINPON_MODE pinpon_mode)246 GOP_Result HAL_GOP_Set_PINPON(GOP_CTX_HAL_LOCAL *pGOPHalLocal, MS_U8 u8GOPNum, MS_BOOL bEn, E_DRV_GOP_PINPON_MODE pinpon_mode)
247 {
248 MS_U32 u32BankOffSet =0;
249 MS_U32 u32BitMask,Regval;
250
251 _GetBnkOfstByGop(u8GOPNum, &u32BankOffSet);
252
253 switch(pinpon_mode)
254 {
255 default:
256 case E_DRV_GOP_PINPON_G3D:
257 Regval = bEn << 5;
258 u32BitMask = GOP_BIT5;
259 break;
260 case E_DRV_GOP_PINPON_DWIN:
261 Regval = bEn << 6;
262 u32BitMask = GOP_BIT6;
263 break;
264 case E_DRV_GOP_PINPON_DIP:
265 Regval = bEn << 7;
266 u32BitMask = GOP_BIT7;
267 HAL_GOP_Write16Reg(pGOPHalLocal, u32BankOffSet+GOP_4G_MULTI_ALPHA, GOP_BIT9,(GOP_BIT8|GOP_BIT9));
268 break;
269 case E_DRV_GOP_PINPON_DWIN0:
270 Regval = bEn << 7;
271 u32BitMask = GOP_BIT7;
272 HAL_GOP_Write16Reg(pGOPHalLocal, u32BankOffSet+GOP_4G_MULTI_ALPHA, 0x0,(GOP_BIT8|GOP_BIT9));
273 break;
274 case E_DRV_GOP_PINPON_DWIN1:
275 Regval = bEn << 7;
276 u32BitMask = GOP_BIT7;
277 HAL_GOP_Write16Reg(pGOPHalLocal, u32BankOffSet+GOP_4G_MULTI_ALPHA, GOP_BIT8,(GOP_BIT8|GOP_BIT9));
278 break;
279 break;
280 }
281
282 HAL_GOP_Write16Reg(pGOPHalLocal, u32BankOffSet+GOP_4G_CTRL1, Regval, u32BitMask);
283 return GOP_SUCCESS;
284 }
285
286
_GetBnkOfstByGop(MS_U8 gop,MS_U32 * pBnkOfst)287 MS_BOOL _GetBnkOfstByGop(MS_U8 gop, MS_U32 *pBnkOfst)
288 {
289 if(gop >= MAX_GOP_SUPPORT)
290 {
291 printf("[%s][%d] Out of GOP support!!! GOP=%d\n",__FUNCTION__,__LINE__ ,gop);
292 return FALSE;
293 }
294
295 if (gop==E_GOP0)
296 *pBnkOfst = GOP_4G_OFST<<16;
297 else if (gop==E_GOP1)
298 *pBnkOfst = GOP_2G_OFST<<16;
299 else if (gop==E_GOP2)
300 *pBnkOfst = GOP_1G_OFST<<16;
301 else if (gop==E_GOP3)
302 *pBnkOfst = GOP_1GX_OFST<<16;
303 else if (gop==E_GOP4)
304 *pBnkOfst = GOP_1GS0_OFST<<16;
305 else
306 return FALSE;
307
308 return TRUE;
309 }
310
_GetGwinOffsetInGOP(MS_U8 u8GwinId)311 MS_U8 _GetGwinOffsetInGOP(MS_U8 u8GwinId)
312 {
313 if(u8GwinId >= GOP4_GwinIdBase)
314 return (u8GwinId - GOP4_GwinIdBase);
315 else if(u8GwinId >= GOP3_GwinIdBase)
316 return (u8GwinId - GOP3_GwinIdBase);
317 else if( u8GwinId >= GOP2_GwinIdBase)
318 return (u8GwinId - GOP2_GwinIdBase);
319 else if (u8GwinId >= GOP1_GwinIdBase)
320 return (u8GwinId - GOP1_GwinIdBase);
321 else
322 return u8GwinId;
323 }
324
HAL_GOP_SetGOPACKMask(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_U16 u16GopMask)325 GOP_Result HAL_GOP_SetGOPACKMask(GOP_CTX_HAL_LOCAL *pGOPHalLocal,MS_U16 u16GopMask)
326 {
327 MS_U16 u16Mask0 = 0;
328 MS_U16 u16Mask1 = 0;
329 if (u16GopMask&GOP_BIT0)
330 {
331 u16Mask0 |= GOP_BIT12;
332 }
333 if (u16GopMask&GOP_BIT1)
334 {
335 u16Mask0 |= GOP_BIT13;
336 }
337 if (u16GopMask&GOP_BIT2)
338 {
339 u16Mask0 |= GOP_BIT14;
340 }
341 if (u16GopMask&GOP_BIT3)
342 {
343 u16Mask0 |= GOP_BIT15;
344 }
345 if (u16GopMask&GOP_BIT4)
346 {
347 u16Mask1 |= GOP_BIT2;
348 }
349 if (u16Mask0 != 0)
350 {
351 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_BAK_SEL, 0xFFFF , u16Mask0);
352 }
353 if (u16Mask1 != 0)
354 {
355 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_BAK_SEL_EX, 0xFFFF , u16Mask1);
356 }
357
358 if(g_GopChipPro.bAFBC_Merge_GOP_Trig ==FALSE)
359 {
360 HAL_GOP_Write16Reg(pGOPHalLocal, REG_AFBC_TRIGGER, GOP_BIT1, GOP_BIT1);
361 }
362 return GOP_SUCCESS;
363 }
364
HAL_GOP_SetGOPACK(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_U8 gop)365 GOP_Result HAL_GOP_SetGOPACK(GOP_CTX_HAL_LOCAL *pGOPHalLocal,MS_U8 gop)
366 {
367 if(gop >= MAX_GOP_SUPPORT)
368 {
369 printf("[%s][%d] Out of GOP support!!! GOP=%d\n",__FUNCTION__,__LINE__ ,gop);
370 return GOP_FAIL;
371 }
372
373 switch(gop)
374 {
375 case E_GOP0:
376 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_BAK_SEL, GOP_BIT12 , GOP_BIT12);
377 break;
378 case E_GOP1:
379 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_BAK_SEL, GOP_BIT13 , GOP_BIT13);
380 break;
381 case E_GOP2:
382 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_BAK_SEL, GOP_BIT14 , GOP_BIT14);
383 break;
384 case E_GOP3:
385 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_BAK_SEL, GOP_BIT15 , GOP_BIT15);
386 break;
387 case E_GOP4:
388 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_BAK_SEL_EX, GOP_BIT2 , GOP_BIT2);
389 break;
390 default:
391 printf("[%s][%d] Unsurrport GOP=%d\n",__FUNCTION__,__LINE__ ,gop);
392 break;
393 }
394 if(g_GopChipPro.bAFBC_Merge_GOP_Trig ==FALSE)
395 {
396 HAL_GOP_Write16Reg(pGOPHalLocal, REG_AFBC_TRIGGER, GOP_BIT0, GOP_BIT0);
397 HAL_GOP_Write16Reg(pGOPHalLocal, REG_AFBC_TRIGGER, GOP_BIT1, GOP_BIT1);
398 }
399 return GOP_SUCCESS;
400 }
401
HAL_GOP_GetGOPACK(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_U8 gop)402 MS_U16 HAL_GOP_GetGOPACK(GOP_CTX_HAL_LOCAL *pGOPHalLocal,MS_U8 gop)
403 {
404 MS_U16 u16GopAck = 0,reg_val =0;
405
406 if(gop >= MAX_GOP_SUPPORT)
407 {
408 printf("[%s][%d] Out of GOP support!!! GOP=%d\n",__FUNCTION__,__LINE__ ,gop);
409 return FALSE;
410 }
411
412 switch(gop)
413 {
414 case E_GOP0:
415 HAL_GOP_Read16Reg(pGOPHalLocal,GOP_BAK_SEL,®_val);
416 if(reg_val&GOP_BIT12)
417 u16GopAck = FALSE;
418 else
419 u16GopAck = TRUE;
420 break;
421 case E_GOP1:
422 HAL_GOP_Read16Reg(pGOPHalLocal,GOP_BAK_SEL,®_val);
423 if(reg_val&GOP_BIT13)
424 u16GopAck = FALSE;
425 else
426 u16GopAck = TRUE;
427 break;
428 case E_GOP2:
429 HAL_GOP_Read16Reg(pGOPHalLocal,GOP_BAK_SEL,®_val);
430 if(reg_val&GOP_BIT14)
431 u16GopAck = FALSE;
432 else
433 u16GopAck = TRUE;
434 break;
435 case E_GOP3:
436 HAL_GOP_Read16Reg(pGOPHalLocal,GOP_BAK_SEL,®_val);
437 if(reg_val&GOP_BIT15)
438 u16GopAck = FALSE;
439 else
440 u16GopAck = TRUE;
441 break;
442 case E_GOP4:
443 HAL_GOP_Read16Reg(pGOPHalLocal,GOP_BAK_SEL_EX,®_val);
444 if(reg_val&GOP_BIT2)
445 u16GopAck = FALSE;
446 else
447 u16GopAck = TRUE;
448 break;
449 default:
450 printf("[%s][%d] Unsurrport GOP=%d\n",__FUNCTION__,__LINE__ ,gop);
451 break;
452 }
453 return u16GopAck;
454 }
455
HAL_GOP_EnableTwoLineBufferMode(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_U8 u8GOP,MS_BOOL bEnable)456 GOP_Result HAL_GOP_EnableTwoLineBufferMode(GOP_CTX_HAL_LOCAL *pGOPHalLocal, MS_U8 u8GOP, MS_BOOL bEnable)
457 {
458 return GOP_FUN_NOT_SUPPORTED;
459 }
460
HAL_GOP_Init(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_U8 u8GOPNum)461 void HAL_GOP_Init(GOP_CTX_HAL_LOCAL *pGOPHalLocal, MS_U8 u8GOPNum)
462 {
463 MS_U32 u32bankoff = 0;
464 MS_U16 mask_shift=0xFF;
465 MS_U16 u16RegVal=0xFF;
466 MS_U8 u8MIUSel=0xF;
467 MS_U8 u8Core=0;
468
469 if(u8GOPNum >= MAX_GOP_SUPPORT)
470 {
471 return;
472 }
473
474 _GetBnkOfstByGop(u8GOPNum, &u32bankoff);
475 HAL_GOP_Write16Reg(pGOPHalLocal, u32bankoff+GOP_4G_CTRL0, 0x000, GOP_BIT9); // Genshot fast=0 for t3, for T4 and after no need to set this bit.
476
477 HAL_GOP_Write16Reg(pGOPHalLocal, u32bankoff+GOP_4G_BW, GOP_BIT15|GOP_BIT14, GOP_BIT15|GOP_BIT14);
478 HAL_GOP_Write16Reg(pGOPHalLocal, u32bankoff+GOP_4G_NEW_BW, GOP_BIT14, GOP_BIT14);
479 HAL_GOP_Write16Reg(pGOPHalLocal, u32bankoff+GOP_4G_NEW_BW, GOP_BIT12, GOP_BIT13|GOP_BIT12);
480 HAL_GOP_Write16Reg(pGOPHalLocal, u32bankoff+GOP_4G_NEW_BW, GOP_BIT8|GOP_BIT9, GOP_BIT8|GOP_BIT9);
481
482 HAL_GOP_Write16Reg(pGOPHalLocal, u32bankoff+GOP_4G_HW_USAGE, 0, GOP_BIT0);
483
484 // H121 filter
485 HAL_GOP_Write16Reg(pGOPHalLocal, u32bankoff+GOP_4G_H121, 0, GOP_BIT0); // HD alpha Enable
486 HAL_GOP_Write16Reg(pGOPHalLocal, u32bankoff+GOP_4G_H121, 0, GOP_BIT1); // HD data Enable
487 HAL_GOP_Write16Reg(pGOPHalLocal, u32bankoff+GOP_4G_H121, GOP_BIT2, GOP_BIT2); // SD data Enable
488 HAL_GOP_Write16Reg(pGOPHalLocal, u32bankoff+GOP_4G_H121, GOP_BIT3, GOP_BIT3); // SD data Enable
489 HAL_GOP_Write16Reg(pGOPHalLocal, u32bankoff+GOP_4G_H121, 0x2000, 0x3F00); // Ratio between [H121] and [Bypass mode]
490
491 //Set handshake mode
492 if(g_GopChipPro.bOPHandShakeModeSupport)
493 HAL_GOP_Write16Reg(pGOPHalLocal, u32bankoff+GOP_4G_BANK_FWR, GOP_BIT10, GOP_BIT10);
494 else
495 HAL_GOP_Write16Reg(pGOPHalLocal, u32bankoff+GOP_4G_BANK_FWR, 0, GOP_BIT10);
496
497 if((u8GOPNum == 0)||(u8GOPNum == 1)||(u8GOPNum == 2))
498 {
499 if(u8GOPNum == 0)
500 {
501 HAL_GOP_Write16Reg(pGOPHalLocal, u32bankoff+GOP_4G_SRAM_BORROW, 0, GOP_BIT13|GOP_BIT14);
502 }
503 else
504 {
505 HAL_GOP_Write16Reg(pGOPHalLocal, u32bankoff+GOP_4G_SRAM_BORROW, 0, GOP_BIT14);
506 }
507 HAL_GOP_Write16Reg(pGOPHalLocal, u32bankoff+GOP_4G_TWO_LINEBUFFER, GOP_BIT12, GOP_BIT12);
508 }
509
510 /* enable GOP clock */
511 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_SRAMCLK, 0, CKG_SRAM1_DISABLE_CLK|CKG_SRAM0_DISABLE_CLK); /* GOP palette SRAM0&1 */
512 // HAL_GOP_Write16Reg(pGOPHalLocal, GOP_LB_SRAMCLK, 0, BMASK(7:0)); /* GOP Line buffer sram clock */
513
514 switch(u8GOPNum)
515 {
516 case E_GOP0:
517 mask_shift = GOP_MIU_CLIENT_GOP0;
518 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_GOPCLK, 0, CKG_GOPG0_DISABLE_CLK_MASK); /* GOP 0 */
519 break;
520 case E_GOP1:
521 mask_shift = GOP_MIU_CLIENT_GOP1;
522 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_GOPCLK, 0, CKG_GOPG1_DISABLE_CLK_MASK); /* GOP 1 */
523 break;
524 case E_GOP2:
525 mask_shift = GOP_MIU_CLIENT_GOP2;
526 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_GOP2CLK, 0, CKG_GOPG2_DISABLE_CLK_MASK); /* GOP 2 */
527 break;
528 case E_GOP3:
529 mask_shift = GOP_MIU_CLIENT_GOP3;
530 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_GOP3CLK, 0, CKG_GOPG3_DISABLE_CLK_MASK); /* GOP 3 */
531 break;
532 case E_GOP4: // K6 : GOP0~3 and GOP5, NO GOP4. Mapping E_GOP4 to GOP 5 reg
533 mask_shift = GOP_MIU_CLIENT_GOP5;
534 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_GOP5CLK, 0, CKG_GOPG5_DISABLE_CLK_MASK); /* GOP 5 */
535 break;
536 default:
537 mask_shift = 0xFF;
538 break;
539 }
540 if(g_GopChipPro.bAFBC_Support[u8GOPNum] ==TRUE)
541 {
542 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_AFBCCLK, 0, CKG_AFBCCLK_DISABLE_CLK_MASK);
543 HAL_GOP_Write16Reg(pGOPHalLocal, REG_AFBC_FMT(0), GOP_BIT5 , GOP_BIT5); //Half block
544 HAL_GOP_Write16Reg(pGOPHalLocal, REG_AFBC_FMT(1), GOP_BIT5 , GOP_BIT5); //Half block
545 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_AFBCCLK, CKG_AFBCCLK_432, GOP_BIT2|GOP_BIT3); //Clk(Without resoluton)
546 HAL_GOP_Write16Reg(pGOPHalLocal, REG_AFBC_TRIGGER, GOP_BIT0, GOP_BIT0); //Double buffer
547 }
548
549
550 if(pGOPHalLocal->pGopChipPro->bInternalMIUSelect[u8GOPNum] ==TRUE)
551 {
552 if(u8GOPNum ==E_GOP4) // K6 : GOP0~3 and GOP5, NO GOP4. Mapping E_GOP4 to GOP 5 reg
553 HAL_GOP_Read16Reg(pGOPHalLocal, GOP5_MIU_GROUP1, &u16RegVal);
554 else
555 HAL_GOP_Read16Reg(pGOPHalLocal, GOP_MIU_GROUP1, &u16RegVal);
556 u8MIUSel = (u16RegVal>>mask_shift)&0x0000001UL;
557 #ifdef GOP_MIU_GROUP2
558 HAL_GOP_Read16Reg(pGOPHalLocal, GOP_MIU_GROUP2, &u16RegVal);
559 u8MIUSel = u8MIUSel|(((u16RegVal>>mask_shift)&0x0000001UL)<<1);
560 #endif
561 HAL_GOP_Write16Reg(pGOPHalLocal, u32bankoff+GOP_4G_MIU_SEL, u8MIUSel<<0, GOP_BIT0|GOP_BIT1 );//GWIN MIU Select
562 HAL_GOP_Write16Reg(pGOPHalLocal, u32bankoff+GOP_4G_MIU_SEL, u8MIUSel<<2, GOP_BIT2|GOP_BIT3 );//GWIN_3D MIU Select
563 if(g_GopChipPro.bAFBC_Support[u8GOPNum]==TRUE)
564 {
565 HAL_GOP_AFBC_GetCore(pGOPHalLocal, u8GOPNum, &u8Core);
566 HAL_GOP_Write16Reg(pGOPHalLocal, REG_AFBC_MIU, u8MIUSel<<4 , GOP_BIT4|GOP_BIT5);
567 }
568
569 if(u8GOPNum ==E_GOP4) // K6 : GOP0~3 and GOP5, NO GOP4. Mapping E_GOP4 to GOP 5 reg
570 HAL_GOP_Write16Reg(pGOPHalLocal, GOP5_MIU_GROUP, 1<<mask_shift, 1<<mask_shift );//Get Control MIU select by GOP itself
571 else
572 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_MIU_GROUP, 1<<mask_shift, 1<<mask_shift );//Get Control MIU select by GOP itself
573 }
574
575 //OC_RM_alpha
576 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_SC_OCALPHA, GOP_BIT0, GOP_BIT0);
577 //THEALE/utopia_release/UTPA2-205.0.x_Muji/mxlib/hal/muji/gop/
578 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_MUX_4K2K, 0x7<< GOP_DIP_MUX_SHIFT, GOP_DIP_MUX_MASK);
579
580 // set VIP/VOP timing select, always select VOP should be OK.
581 HAL_GOP_Write16Reg(pGOPHalLocal, u32bankoff+GOP_4G_VIP_VOP_TIMING_SEL, GOP_BIT10, GOP_BIT10);
582
583 // Enable OP Mux double buff
584 if(g_GopChipPro.bOPMuxDoubleBuffer == TRUE)
585 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_4G_OP_MUX_DBF, GOP_BIT15 , GOP_BIT15);
586 else
587 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_4G_OP_MUX_DBF, 0 , GOP_BIT15);
588
589 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_SC_VOP2BLENDING_L, GOP_BIT7|GOP_BIT15, GOP_BIT7|GOP_BIT15);//Per Pixel New alpha mode
590 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_SC_VOP2BLENDING_H, GOP_BIT7|GOP_BIT15, GOP_BIT7|GOP_BIT15);//Per Pixel New alpha mode
591 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_MUX_IPVOP,GOP_IP_SUB_MUX_MASK, GOP_IP_SUB_MUX_MASK); //default mask sub IP
592 }
593
HAL_GOP_Chip_Proprity_Init(GOP_CTX_HAL_LOCAL * pGOPHalLocal)594 void HAL_GOP_Chip_Proprity_Init(GOP_CTX_HAL_LOCAL *pGOPHalLocal)
595 {
596 pGOPHalLocal->pGopChipPro = &g_GopChipPro;
597 }
598
HAL_GOP_GetMaxGwinNumByGOP(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_U8 u8GopNum)599 MS_U8 HAL_GOP_GetMaxGwinNumByGOP(GOP_CTX_HAL_LOCAL *pGOPHalLocal, MS_U8 u8GopNum)
600 {
601 switch(u8GopNum)
602 {
603 case E_GOP0:
604 return (MS_U8)MAX_GOP0_GWIN;
605 break;
606 case E_GOP1:
607 return (MS_U8)MAX_GOP1_GWIN;
608 break;
609 case E_GOP2:
610 return (MS_U8)MAX_GOP2_GWIN;
611 break;
612 case E_GOP3:
613 return (MS_U8)MAX_GOP3_GWIN;
614 break;
615 case E_GOP4:
616 return (MS_U8)MAX_GOP4_GWIN;
617 break;
618 default:
619 MS_ASSERT(0);
620 return 0xFF;
621 break;
622 }
623 }
624
HAL_GOP_SelGwinIdByGOP(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_U8 u8Gop,MS_U8 u8Idx)625 MS_U8 HAL_GOP_SelGwinIdByGOP(GOP_CTX_HAL_LOCAL *pGOPHalLocal, MS_U8 u8Gop, MS_U8 u8Idx)
626 {
627 MS_U8 u8GWinId = 0;
628
629 //Adjust GWIN ID by different Chip
630 if(u8Gop >= MAX_GOP_SUPPORT)
631 {
632 printf("[%s][%d] Out of GOP support!!! GOP=%d\n",__FUNCTION__,__LINE__ ,u8Gop);
633 MS_ASSERT(0);
634 return 0xFF;
635 }
636
637 switch(u8Gop)
638 {
639 case E_GOP0:
640 u8GWinId = GOP0_GwinIdBase + u8Idx;
641 break;
642 case E_GOP1:
643 u8GWinId = GOP1_GwinIdBase + u8Idx;
644 break;
645 case E_GOP2:
646 u8GWinId = GOP2_GwinIdBase + u8Idx;
647 break;
648 case E_GOP3:
649 u8GWinId = GOP3_GwinIdBase + u8Idx;
650 break;
651 #if (MAX_GOP_SUPPORT>4)
652 case E_GOP4:
653 u8GWinId = GOP4_GwinIdBase + u8Idx;
654 break;
655 #endif
656 default:
657 break;
658 }
659 return u8GWinId;
660
661 }
662
HAL_GOP_GOPSel(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_U8 u8GOPNum)663 GOP_Result HAL_GOP_GOPSel(GOP_CTX_HAL_LOCAL *pGOPHalLocal, MS_U8 u8GOPNum)
664 {
665 if(u8GOPNum >= MAX_GOP_SUPPORT)
666 {
667 printf("[%s][%d] Out of GOP support!!! GOP=%d\n",__FUNCTION__,__LINE__ ,u8GOPNum);
668 MS_ASSERT(0);
669 return 0xFF;
670 }
671
672 switch(u8GOPNum)
673 {
674 case E_GOP0: // GOP4G
675 pGOPHalLocal->bank_offset = GOP_4G_OFST<<16;
676 return GOP_SUCCESS;
677 case E_GOP1: // GOP2G
678 pGOPHalLocal->bank_offset = GOP_2G_OFST<<16;
679 return GOP_SUCCESS;
680 case E_GOP2: // GOP1G
681 pGOPHalLocal->bank_offset = GOP_1G_OFST<<16;
682 return GOP_SUCCESS;
683 case E_GOP3: // GOP1GX
684 pGOPHalLocal->bank_offset = GOP_1GX_OFST<<16;
685 return GOP_SUCCESS;
686 #if (MAX_GOP_SUPPORT>4)
687 case E_GOP4: // GOP1GS
688 pGOPHalLocal->bank_offset = GOP_1GS0_OFST<<16;
689 return GOP_SUCCESS;
690 #endif
691 default:
692 MS_ASSERT(0);
693 return GOP_FAIL;
694 }
695 }
696
HAL_GOP_BANK_SEL(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_U8 u8bank)697 void HAL_GOP_BANK_SEL(GOP_CTX_HAL_LOCAL *pGOPHalLocal, MS_U8 u8bank)
698 {
699 MS_U16 u16Bank;
700 u16Bank = GOP_READ2BYTE(GOP_BAK_SEL);
701 u16Bank &= ~BMASK(3:0);
702 u16Bank |= (u8bank&BMASK(3:0));
703 GOP_WRITE2BYTE(GOP_BAK_SEL, u16Bank);
704
705 #if(MAX_GOP_SUPPORT>4)
706 u16Bank = GOP_READ2BYTE(GOP_BAK_SEL_EX);
707 u16Bank &= ~GOP_BIT8;
708 if(u8bank&GOP_BIT4); // reg_gop_bnk_4
709 u16Bank |= GOP_BIT8;
710 GOP_WRITE2BYTE(GOP_BAK_SEL_EX, u16Bank);
711 #endif
712 }
713
HAL_GOP_Get_BANK(GOP_CTX_HAL_LOCAL * pGOPHalLocal)714 MS_U8 HAL_GOP_Get_BANK(GOP_CTX_HAL_LOCAL *pGOPHalLocal)
715 {
716 MS_U16 u16GetBank=0;
717 u16GetBank = (GOP_READ2BYTE(GOP_BAK_SEL)&0xF);
718
719 #if (MAX_GOP_SUPPORT>4)
720 if(GOP_READ2BYTE(GOP_BAK_SEL_EX)&GOP_BIT8) //reg_gop_bnk_4
721 return GOP_BIT4|(u16GetBank&GOP_BANK_MASK);
722 #endif
723 return (u16GetBank&GOP_BANK_MASK);
724
725 }
726
HAL_GOP_Read16Reg(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_U32 u32addr,MS_U16 * pu16ret)727 void HAL_GOP_Read16Reg(GOP_CTX_HAL_LOCAL *pGOPHalLocal, MS_U32 u32addr, MS_U16* pu16ret)
728 {
729 MS_U16 u16xcSubbank=0, u16BankAddr=0, u16BankTemp=0;
730 MS_U32 bank;
731 MS_U32 direct_addr;
732
733 HAL_GOP_DEBUGINFO(printf("HAL_GOP_Read16Reg[%x]\n", u32addr));
734
735 //* Gop driver should access another HW IP register
736 //* ex: SC's IP and OP setting, GE's det frame buffer setting, ChipTop GOP clk setting
737 switch (u32addr & 0xFF00)
738 {
739 case GOP_REG_BASE:
740 {
741 bank = (u32addr & 0xFF0000) >> 8;
742 #if 0 //for GOP4
743 if(bank==0xE00)//GOP4: 0x121B00
744 {
745 bank=GOP_REG_GOP4_BK_OFFSET;
746 }
747 else if(bank==0xF00)//GWIN4: 0x121E00
748 {
749 bank=GOP_REG_GOP4_GW_OFFSET;
750 }
751 else if(bank==0x1000)//GOP4_ST
752 {
753 bank=GOP_REG_GOP4_ST_OFFSET;
754 }
755 #endif
756 direct_addr = GOP_REG_DIRECT_BASE + bank + (u32addr & 0xFF); //Direct_Base + bank + addr_offset
757 *pu16ret = GOP_READ2BYTE((direct_addr&0xFFFFF));
758 break;
759 }
760 case SC1_REG_BASE:
761 {
762 if(g_GopChipPro.bXCDirrectBankSupport)
763 {
764 u16xcSubbank = (u32addr & 0xFF0000)>>8;
765 u32addr = SC1_DIRREG_BASE+ u16xcSubbank + (u32addr & 0xFF);
766 *pu16ret = GOP_READ2BYTE((u32addr&0xFFFFF));
767 }
768 else
769 {
770 u16xcSubbank = (u32addr & 0xFF0000)>>16;
771 u16BankAddr = GOP_SC_BANKSEL+0;
772 u32addr = SC1_REG_BASE + (u32addr & 0xFF);
773
774 u16BankTemp = GOP_READ2BYTE(u16BankAddr&0xFFFF);
775 GOP_WRITE2BYTE(u16BankAddr&0xFFFF, u16xcSubbank);
776 *pu16ret = GOP_READ2BYTE((u32addr&0xFFFF));
777 GOP_WRITE2BYTE(u16BankAddr&0xFFFF, u16BankTemp);
778 }
779 break;
780 }
781 case GE_REG_BASE:
782 case CKG_REG_BASE:
783 case MIU0_REG_BASE:
784 case MIU_REG_BASE:
785 case MVOP_REG_BASE:
786 case VE_REG_BASE:
787 {
788 *pu16ret = GOP_READ2BYTE((u32addr&0xFFFF));
789 break;
790 }
791 #ifdef GOP_MIU_GROUP2
792 case (MIU2_REG_BASE & 0xFF00):
793 {
794 direct_addr = MIU2_REG_BASE + (u32addr & 0xFF); //Direct_Base + addr_offset
795 *pu16ret = GOP_READ2BYTE((direct_addr&0xFFFFF));
796
797 break;
798 }
799 #endif
800 default:
801 {
802 //Gop lib current do not support this HW ip base
803 MS_ASSERT(0);
804 *pu16ret =0;
805 break;
806 }
807 }
808 }
809
HAL_GOP_Write16Reg(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_U32 u32addr,MS_U16 u16val,MS_U16 mask)810 void HAL_GOP_Write16Reg(GOP_CTX_HAL_LOCAL *pGOPHalLocal, MS_U32 u32addr, MS_U16 u16val, MS_U16 mask)
811 {
812 MS_U16 u16tmp=0;
813 MS_U16 u16xcSubbank=0,u16BankAddr=0,pu16ret=0;
814 MS_U32 bank;
815 MS_U32 direct_addr;
816
817 HAL_GOP_DEBUGINFO(printf("HAL_GOP_Write16Reg[%04x] = %04x\n", u32addr, u16val));
818
819 if(mask!=0xffff)
820 {
821 HAL_GOP_Read16Reg(pGOPHalLocal, u32addr, &u16tmp);
822 u16tmp &= ~mask;
823 u16val &= mask;
824 u16val |= u16tmp;
825 }
826
827 //* Gop driver should access another HW IP register
828 //* ex: SC's IP and OP setting, GE's det frame buffer setting, ChipTop GOP clk setting
829 switch (u32addr & 0xFF00)
830 {
831 case GOP_REG_BASE:
832 {
833 bank = (u32addr & 0xFF0000) >> 8;
834 #if 0 //for GOP4
835 if(bank==0xE00)//GOP4: 0x121B00
836 {
837 bank=GOP_REG_GOP4_BK_OFFSET;
838 }
839 else if(bank==0xF00)//GWIN4: 0x121E00
840 {
841 bank=GOP_REG_GOP4_GW_OFFSET;
842 }
843 else if(bank==0x1000) //GOP4_ST
844 {
845 bank=GOP_REG_GOP4_ST_OFFSET;
846 }
847 #endif
848 direct_addr = GOP_REG_DIRECT_BASE + bank + (u32addr & 0xFF);
849 GOP_WRITE2BYTE((direct_addr&0xFFFFF), u16val);
850 break;
851 }
852 case SC1_REG_BASE:
853 if(g_GopChipPro.bXCDirrectBankSupport)
854 { /*Derrick Bank*/
855 u16xcSubbank = (u32addr & 0xFF0000)>>8 ;
856 direct_addr = SC1_DIRREG_BASE + u16xcSubbank+ (u32addr & 0xFF);
857 GOP_WRITE2BYTE((direct_addr&0xFFFFF), u16val);
858 }
859 else
860 { /*Sub Bank*/
861 u16xcSubbank = (u32addr & 0xFF0000)>>16 ;
862 u16BankAddr = GOP_SC_BANKSEL+0;
863 u32addr = SC1_REG_BASE + (u32addr & 0xFF);
864
865 pu16ret = GOP_READ2BYTE(u16BankAddr&0xFFFF);
866 GOP_WRITE2BYTE((u16BankAddr&0xFFFF), u16xcSubbank);
867 GOP_WRITE2BYTE((u32addr&0xFFFF), u16val);
868 GOP_WRITE2BYTE((u16BankAddr&0xFFFF), pu16ret);
869 }
870 break;
871 case GE_REG_BASE:
872 case CKG_REG_BASE:
873 case MIU0_REG_BASE:
874 case MIU_REG_BASE:
875 case VE_REG_BASE:
876 {
877 GOP_WRITE2BYTE((u32addr&0xFFFF), u16val);
878 break;
879 }
880 #ifdef GOP_MIU_GROUP2
881 case (MIU2_REG_BASE & 0xFF00):
882 {
883 direct_addr = MIU2_REG_BASE + (u32addr & 0xFF); //Direct_Base + addr_offset
884 GOP_WRITE2BYTE((direct_addr&0xFFFFF), u16val);
885 break;
886 }
887 #endif
888 default:
889 {
890 //Gop lib current do not support this HW ip base
891 MS_ASSERT(0);
892 break;
893 }
894
895 }
896 }
897
898
HAL_GOP_Write32Reg(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_U32 u32addr,MS_U32 u32val)899 void HAL_GOP_Write32Reg(GOP_CTX_HAL_LOCAL *pGOPHalLocal, MS_U32 u32addr, MS_U32 u32val)
900 {
901 MS_U32 bank;
902 MS_U32 direct_addr;
903
904 HAL_GOP_DEBUGINFO(printf("HAL_GOP_Write32Reg[%bx] = %lx\n", u32addr, u32val));
905
906 //* Gop driver should access another HW IP register
907 //* ex: SC's IP and OP setting, GE's det frame buffer setting, ChipTop GOP clk setting
908 switch (u32addr & 0xFF00)
909 {
910 case GOP_REG_BASE:
911 {
912 bank = (u32addr & 0xFF0000) >> 8;
913 #if 0 //for GOP4
914 if(bank==0xE00)//GOP4: 0x121B00
915 {
916 bank=GOP_REG_GOP4_BK_OFFSET;
917 }
918 else if(bank==0xF00)//GWIN4: 0x121E00
919 {
920 bank=GOP_REG_GOP4_GW_OFFSET;
921 }
922 else if(bank==0x1000) //GOP4_ST
923 {
924 bank=GOP_REG_GOP4_ST_OFFSET;
925 }
926 #endif
927 direct_addr = GOP_REG_DIRECT_BASE + bank + (u32addr & 0xFF);
928 GOP_WRITE2BYTE((direct_addr&0xFFFFF), (u32val&0xFFFF));
929 GOP_WRITE2BYTE((direct_addr&0xFFFFF)+2, (u32val&0xFFFF0000)>>16);
930 break;
931 }
932
933 case GE_REG_BASE:
934 case SC1_REG_BASE:
935 case CKG_REG_BASE:
936 {
937 GOP_WRITE2BYTE((u32addr&0xFFFF), (u32val&0xFFFF));
938 GOP_WRITE2BYTE((u32addr&0xFFFF)+2, (u32val&0xFFFF0000)>>16);
939 break;
940 }
941
942 default:
943 {
944 //Gop lib current do not support this HW ip base
945 MS_ASSERT(0);
946 break;
947 }
948
949 }
950 }
951
952 //extern E_BDMA_Ret MDrv_BDMA_Mem_Fill(MS_U32 u32Addr, MS_U32 u32Len, MS_U32 u32Pattern, E_BDMA_DstDev eDev);
953
HAL_GOP_Write32Pal(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_U8 * pREGMAP_Base,MS_U16 * pREGMAP_Offset,MS_U32 u32REGMAP_Len,MS_U8 u8Index,MS_U8 u8A,MS_U8 u8R,MS_U8 u8G,MS_U8 u8B)954 void HAL_GOP_Write32Pal(GOP_CTX_HAL_LOCAL *pGOPHalLocal,
955 MS_U8 *pREGMAP_Base, MS_U16 *pREGMAP_Offset, MS_U32 u32REGMAP_Len,
956 MS_U8 u8Index, MS_U8 u8A, MS_U8 u8R, MS_U8 u8G, MS_U8 u8B)
957 {
958 MS_U8 i=0;
959 HAL_GOP_DEBUGINFO(printf("GOP_Write32Pal : i= %02bx, ARGB = %02bx,%02bx,%02bx,%02bx\n",u8Index, u8A, u8R, u8G, u8B));
960
961 /* Don't care high byte */
962 MS_ASSERT((MS_U32)(*pREGMAP_Offset +GOP_WordUnit)<= u32REGMAP_Len);
963
964 for(i =(GOP_WordUnit-1);i>4;i--)
965 {
966 *(pREGMAP_Base + *pREGMAP_Offset + i) = 0;
967 }
968 *(pREGMAP_Base + *pREGMAP_Offset + 4) = u8Index;
969 *(pREGMAP_Base + *pREGMAP_Offset + 3) = u8A;
970 *(pREGMAP_Base + *pREGMAP_Offset + 2) = u8R;
971 *(pREGMAP_Base + *pREGMAP_Offset + 1) = u8G;
972 *(pREGMAP_Base + *pREGMAP_Offset) = u8B;
973 *pREGMAP_Offset += GOP_WordUnit;
974
975 MsOS_FlushMemory(); //make sure cpu write data to dram
976
977 }
978
HAL_GOP_GetBPP(GOP_CTX_HAL_LOCAL * pGOPHalLocal,DRV_GOPColorType fbFmt)979 MS_U16 HAL_GOP_GetBPP(GOP_CTX_HAL_LOCAL *pGOPHalLocal, DRV_GOPColorType fbFmt)
980 {
981 MS_U16 bpp=0;
982
983 switch ( fbFmt )
984 {
985 case E_DRV_GOP_COLOR_RGB555_BLINK :
986 case E_DRV_GOP_COLOR_RGB565 :
987 case E_DRV_GOP_COLOR_ARGB1555:
988 case E_DRV_GOP_COLOR_RGBA5551:
989 case E_DRV_GOP_COLOR_ARGB4444 :
990 case E_DRV_GOP_COLOR_RGBA4444 :
991 case E_DRV_GOP_COLOR_RGB555YUV422:
992 case E_DRV_GOP_COLOR_YUV422:
993 case E_DRV_GOP_COLOR_2266:
994 bpp = 16;
995 break;
996 case E_DRV_GOP_COLOR_ARGB8888 :
997 case E_DRV_GOP_COLOR_ABGR8888 :
998 bpp = 32;
999 break;
1000
1001 case E_DRV_GOP_COLOR_I8 :
1002 bpp = 8;
1003 break;
1004
1005 default :
1006 //print err
1007 MS_ASSERT(0);
1008 bpp = 0xFFFF;
1009 break;
1010 }
1011 return bpp;
1012
1013 }
1014
HAL_GOP_GWIN_SetBlending(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_U8 u8win,MS_BOOL bEnable,MS_U8 u8coef)1015 void HAL_GOP_GWIN_SetBlending(GOP_CTX_HAL_LOCAL *pGOPHalLocal, MS_U8 u8win, MS_BOOL bEnable, MS_U8 u8coef)
1016 {
1017 MS_U16 regval;
1018 /*For compatibility
1019 Old chip only have alpha coeffient 6 bits. Charka2 define UI alpha value base on it.*/
1020 MS_U8 u8coef_cpt = u8coef;
1021
1022 //if UI alpha value based on alpha coeffient 6 bits, and our chip is 8bit, please do it.
1023 if( pGOPHalLocal->User_ConsAlpha_bits != g_GopChipPro.Default_ConsAlpha_bits)
1024 {
1025 switch(u8coef)
1026 {
1027 case 0x0 :
1028 u8coef_cpt = u8coef<<2;
1029 break;
1030 case 0x3f :
1031 u8coef_cpt = ((u8coef<<2)|0x3);
1032 break;
1033 default:
1034 u8coef_cpt = ((u8coef<<2)|0x1);
1035 break;
1036 }
1037 }
1038
1039 /*alpha coeffient 6/8bit chip has GOP0,GOP1*/
1040 if (u8win<(MAX_GOP0_GWIN+MAX_GOP1_GWIN))
1041 {
1042 regval = (MS_U16)(bEnable?(1<<14):0)|(MS_U16)((u8coef&0x3F)<<8);
1043 HAL_GOP_Write16Reg(pGOPHalLocal, (u8win < MAX_GOP0_GWIN)? GOP_4G_GWIN0_CTRL(u8win):GOP_2G_GWIN_CTRL(u8win-MAX_GOP0_GWIN), regval, 0x4000);
1044 HAL_GOP_Write16Reg(pGOPHalLocal, (u8win < MAX_GOP0_GWIN)? GOP_4G_GWIN_ALPHA01(u8win):GOP_2G_GWIN_ALPHA01(u8win-MAX_GOP0_GWIN), u8coef_cpt, 0xFF);
1045 }
1046 /*Only alpha coeffient 8bit chip has GOP2,GOP3...*/
1047 else
1048 {
1049 if (u8win==(MAX_GOP0_GWIN+MAX_GOP1_GWIN))
1050 {
1051 regval = (MS_U16)(bEnable?(1<<14):0);
1052 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_1G_GWIN0_CTRL, regval, 0x4000);
1053 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_1G_GWIN_ALPHA01, u8coef, 0xFF);
1054 }
1055 else if ((u8win==(MAX_GOP0_GWIN+MAX_GOP1_GWIN+MAX_GOP2_GWIN)))
1056 {
1057 regval = (MS_U16)(bEnable?(1<<14):0);
1058 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_1GX_GWIN0_CTRL, regval, 0x4000);
1059 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_1GX_GWIN_ALPHA01, u8coef, 0xFF);
1060 }
1061 else
1062 {
1063 regval = (MS_U16)(bEnable?(1<<14):0);
1064 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_1GS0_GWIN0_CTRL, regval, 0x4000);
1065 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_1GS0_GWIN_ALPHA01, u8coef, 0xFF);
1066 }
1067 }
1068 }
1069
HAL_GOP_SetIOMapBase(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_VIRT addr)1070 void HAL_GOP_SetIOMapBase(GOP_CTX_HAL_LOCAL *pGOPHalLocal, MS_VIRT addr)
1071 {
1072 pGOPHalLocal->va_mmio_base = addr;
1073 }
HAL_GOP_SetIOFRCMapBase(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_VIRT addr)1074 void HAL_GOP_SetIOFRCMapBase(GOP_CTX_HAL_LOCAL *pGOPHalLocal, MS_VIRT addr)
1075 {
1076 }
HAL_GOP_SetIOPMMapBase(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_VIRT addr)1077 void HAL_GOP_SetIOPMMapBase(GOP_CTX_HAL_LOCAL *pGOPHalLocal, MS_VIRT addr)
1078 {
1079 }
1080
1081
HAL_GOP_GWIN_SetDstPlane(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_U8 GopNum,DRV_GOPDstType eDstType,MS_BOOL bOnlyCheck)1082 GOP_Result HAL_GOP_GWIN_SetDstPlane(GOP_CTX_HAL_LOCAL *pGOPHalLocal, MS_U8 GopNum, DRV_GOPDstType eDstType,MS_BOOL bOnlyCheck)
1083 {
1084 /*A5 GOP dst type:
1085 1: IP (Main)
1086 0: IP (Sub)
1087 2: OP
1088 3: MVOP
1089 4: MVOP (Sub)
1090 6: FRC
1091 11: InsideFRC
1092 */
1093 MS_U16 u16RegVal;
1094 MS_U32 u32BankOffSet;
1095 MS_BOOL bEnable=FALSE;
1096 MS_U16 u16HSyncMask=GOP_BIT14;
1097
1098 if( GopNum >= MAX_GOP_SUPPORT)
1099 {
1100 printf("[%s][%d] Out of GOP support!!! GOP=%d\n",__FUNCTION__,__LINE__ ,GopNum);
1101 return GOP_INVALID_PARAMETERS;
1102 }
1103
1104 switch (eDstType)
1105 {
1106 case E_DRV_GOP_DST_IP0:
1107 if( (GopNum == E_GOP0) || (GopNum == E_GOP1) )
1108 {
1109 u16RegVal = 0x0;
1110 bEnable = FALSE;
1111 u16HSyncMask=0;
1112 }else{
1113 return GOP_FUN_NOT_SUPPORTED;
1114 }
1115 break;
1116
1117 case E_DRV_GOP_DST_IP0_SUB:
1118 if( (GopNum == E_GOP0) || (GopNum == E_GOP1) )
1119 {
1120 u16RegVal = 0x1;
1121 bEnable = FALSE;
1122 u16HSyncMask=0;
1123 }else{
1124 return GOP_FUN_NOT_SUPPORTED;
1125 }
1126 break;
1127
1128 case E_DRV_GOP_DST_OP0:
1129 u16RegVal = 0x2;
1130 bEnable = FALSE;
1131 u16HSyncMask=GOP_BIT14;
1132 break;
1133
1134 case E_DRV_GOP_DST_IP1:
1135 u16RegVal = 0x5;
1136 bEnable = TRUE;
1137 break;
1138
1139 case E_DRV_GOP_DST_OP1:
1140 u16RegVal = 0x6;
1141 bEnable = TRUE;
1142 u16HSyncMask=GOP_BIT14;
1143 break;
1144
1145 case E_DRV_GOP_DST_VE:
1146 u16RegVal = 0x7;
1147 bEnable = TRUE;
1148 u16HSyncMask=GOP_BIT14;
1149 break;
1150 case E_DRV_GOP_DST_DIP:
1151 u16RegVal = 0x8;
1152 bEnable = TRUE;
1153 u16HSyncMask=GOP_BIT14;
1154 break;
1155
1156 default:
1157 return GOP_FUN_NOT_SUPPORTED;
1158 }
1159
1160 if(bOnlyCheck == FALSE)
1161 {
1162 _GetBnkOfstByGop(GopNum, &u32BankOffSet);
1163 HAL_GOP_SetGOP2Pto1P(pGOPHalLocal, GopNum, bEnable);
1164 HAL_GOP_Write16Reg(pGOPHalLocal, u32BankOffSet+GOP_4G_CTRL1, u16RegVal, BMASK(3:0));
1165
1166 HAL_GOP_Write16Reg(pGOPHalLocal, u32BankOffSet+GOP_4G_CTRL0, u16HSyncMask, GOP_BIT14); // Set mask Hsync when VFDE is low
1167 }
1168 return GOP_SUCCESS;
1169 }
1170
HAL_GOP_SetMixerDst(GOP_CTX_HAL_LOCAL * pGOPHalLocal,DRV_GOPDstType eDstType)1171 GOP_Result HAL_GOP_SetMixerDst(GOP_CTX_HAL_LOCAL *pGOPHalLocal, DRV_GOPDstType eDstType)
1172 {
1173 /*U4 Mixer dst type:
1174 2: OP
1175 3: VE
1176 */
1177 MS_U16 u16Regval = 0;
1178 DRV_MixerDstType eType=E_DRV_MIXER_DST_VE;
1179
1180 switch(eDstType)
1181 {
1182 case E_DRV_GOP_DST_MIXER2VE:
1183 eType = E_DRV_MIXER_DST_VE;
1184 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_MIXER_CTRL, GOP_BIT7, GOP_BIT7); //Enable pseudo hsync
1185 break;
1186 case E_DRV_GOP_DST_MIXER2OP:
1187 eType = E_DRV_MIXER_DST_OP;
1188 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_MIXER_CTRL, 0x0, GOP_BIT7); //Disable pseudo hsync
1189 break;
1190 default:
1191 break;
1192 }
1193
1194 HAL_GOP_Read16Reg(pGOPHalLocal, GOP_MIXER_CTRL, &u16Regval);
1195
1196 u16Regval &= (~(GOP_BIT3|GOP_BIT4));
1197 u16Regval |= (eType<<0x3);
1198
1199 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_MIXER_CTRL, u16Regval, (GOP_BIT3|GOP_BIT4));
1200 return GOP_SUCCESS;
1201 }
1202
HAL_GOP_GetMixerDst(GOP_CTX_HAL_LOCAL * pGOPHalLocal,DRV_GOPDstType * pGopDst)1203 GOP_Result HAL_GOP_GetMixerDst(GOP_CTX_HAL_LOCAL *pGOPHalLocal, DRV_GOPDstType *pGopDst)
1204 {
1205 MS_U16 u16Regval = 0;
1206
1207 HAL_GOP_Read16Reg(pGOPHalLocal, GOP_MIXER_CTRL, &u16Regval);
1208
1209 if(((u16Regval&0x18)>>3) == 0x2)
1210 *pGopDst = E_DRV_GOP_DST_MIXER2OP;
1211 else
1212 *pGopDst = E_DRV_GOP_DST_MIXER2VE;
1213
1214 return GOP_SUCCESS;
1215 }
1216
HAL_GOP_InitMux(GOP_CTX_HAL_LOCAL * pGOPHalLocal)1217 GOP_Result HAL_GOP_InitMux(GOP_CTX_HAL_LOCAL *pGOPHalLocal)
1218 {
1219 /*T8
1220 OP path: support 3 mux (mux0, mux 2, mux3) to blend with SC simultaneously
1221 IP path: support mux0 and mux1 to IPMain/IPSub. Only one mux of mux0 and mux1 can be blended to IPMain/IPSub
1222 SW default setting=> mux0:gop1g, mux1:gop1gx, mux2:gop2g, mux3:gop4g
1223 */
1224 MS_U8 gop4g=0, gop2g=1, gop1g=2, gop1gx=3, gop1gs=5;
1225 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_MUX, ((gop1gs<<(GOP_MUX_SHIFT*4))|(gop4g<<(GOP_MUX_SHIFT*3))|(gop2g<<(GOP_MUX_SHIFT*2))|(gop1gx<<(GOP_MUX_SHIFT*1))|gop1g), GOP_REG_WORD_MASK);
1226
1227 if(g_GopChipPro.bOPMuxDoubleBuffer == TRUE)
1228 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_BAK_SEL_EX, GOP_BIT14 , GOP_BIT14); //SC_0 Mux trigger
1229
1230 /*Disable VE OSD enable*/
1231 HAL_GOP_VE_SetOSDEnable(pGOPHalLocal, FALSE, EN_OSD_0, 0x4);
1232 HAL_GOP_VE_SetOSDEnable(pGOPHalLocal, FALSE, EN_OSD_1, 0x4);
1233
1234 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_SC1_VOPNBL, 1<<7, GOP_BIT7);
1235 return GOP_SUCCESS;
1236 }
1237
HAL_GOP_GWIN_GetMUX(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_U8 * u8GOPNum,Gop_MuxSel eGopMux)1238 void HAL_GOP_GWIN_GetMUX(GOP_CTX_HAL_LOCAL*pGOPHalLocal, MS_U8* u8GOPNum, Gop_MuxSel eGopMux)
1239 {
1240 MS_U16 u16GopMux=0;
1241 switch(eGopMux)
1242 {
1243 case E_GOP_MUX0:
1244 case E_GOP_MUX1:
1245 case E_GOP_MUX2:
1246 case E_GOP_MUX3:
1247 case E_GOP_MUX4:
1248 HAL_GOP_Read16Reg(pGOPHalLocal, GOP_MUX, &u16GopMux);
1249 *u8GOPNum = (u16GopMux >> (eGopMux*GOP_MUX_SHIFT))& GOP_REGMUX_MASK;
1250 break;
1251 case E_GOP_IP0_MUX:
1252 HAL_GOP_Read16Reg(pGOPHalLocal, GOP_MUX_IPVOP, &u16GopMux);
1253 *u8GOPNum = (u16GopMux&GOP_IP_MAIN_MUX_MASK)>>GOP_IP_MAIN_MUX_SHIFT;
1254 break;
1255 case E_GOP_IP0_SUB_MUX:
1256 HAL_GOP_Read16Reg(pGOPHalLocal, GOP_MUX_IPVOP, &u16GopMux);
1257 *u8GOPNum = (u16GopMux&GOP_IP_SUB_MUX_MASK)>>GOP_IP_SUB_MUX_SHIFT;
1258 break;
1259 case E_GOP_VOP0_MUX:
1260 HAL_GOP_Read16Reg(pGOPHalLocal, GOP_MUX_IPVOP, &u16GopMux);
1261 *u8GOPNum = (u16GopMux&GOP_IP_VOP0_MUX_MASK)>>GOP_IP_VOP0_MUX_SHIFT;
1262 break;
1263 case E_GOP_VOP0_SUB_MUX:
1264 HAL_GOP_Read16Reg(pGOPHalLocal, GOP_MUX_IPVOP, &u16GopMux);
1265 *u8GOPNum = (u16GopMux&GOP_IP_VOP1_MUX_MASK)>>GOP_IP_VOP1_MUX_SHIFT;
1266 break;
1267 case E_GOP_Mix_MUX0:
1268 HAL_GOP_Read16Reg(pGOPHalLocal, GOP_MUX4_MIX_VE, &u16GopMux);
1269 *u8GOPNum = (u16GopMux&GOP_Mix_MUX0_MASK)>>GOP_Mix_MUX0_SHIFT;
1270 break;
1271 case E_GOP_Mix_MUX1:
1272 HAL_GOP_Read16Reg(pGOPHalLocal, GOP_MUX4_MIX_VE, &u16GopMux);
1273 *u8GOPNum = (u16GopMux&GOP_Mix_MUX1_MASK)>>GOP_Mix_MUX1_SHIFT;
1274 break;
1275 case E_GOP_VE0_MUX:
1276 HAL_GOP_Read16Reg(pGOPHalLocal, GOP_MUX4_MIX_VE, &u16GopMux);
1277 *u8GOPNum = (u16GopMux&GOP_VE0_MUX_MASK)>>GOP_VE0_MUX_SHIFT;
1278 break;
1279 case E_GOP_VE1_MUX:
1280 HAL_GOP_Read16Reg(pGOPHalLocal, GOP_MUX4_MIX_VE, &u16GopMux);
1281 *u8GOPNum = (u16GopMux&GOP_VE1_MUX_MASK)>>GOP_VE1_MUX_SHIFT;
1282 break;
1283 case E_GOP_DIP_MUX:
1284 HAL_GOP_Read16Reg(pGOPHalLocal, GOP_MUX_4K2K, &u16GopMux);
1285 *u8GOPNum = (u16GopMux&GOP_DIP_MUX_MASK)>>GOP_DIP_MUX_SHIFT;
1286 break;
1287 case E_GOP_FRC_MUX0:
1288 case E_GOP_FRC_MUX1:
1289 case E_GOP_FRC_MUX2:
1290 case E_GOP_FRC_MUX3:
1291 HAL_GOP_Read16Reg(pGOPHalLocal, GOP_MUX_4K2K, &u16GopMux);
1292 *u8GOPNum = (u16GopMux >> ((eGopMux%E_GOP_FRC_MUX0)*GOP_FRC_MUX_SHIFT))& GOP_FRC_REGMUX_MASK;
1293 break;
1294 case E_GOP_BYPASS_MUX0:
1295 break;
1296 case E_GOP_OP1_MUX:
1297 HAL_GOP_Read16Reg(pGOPHalLocal, GOP_MUX_SC1, &u16GopMux);
1298 *u8GOPNum = (u16GopMux& ((BMASK((GOP_MUX_SHIFT-1):0))<<12))>>12;
1299 break;
1300 case E_GOP_IP1_MUX:
1301 case E_GOP_VOP1_MUX:
1302 case E_GOP_GS_MUX:
1303 case E_GOP_DUALRATE_OP_MUX0:
1304 case E_GOP_DUALRATE_OP_MUX1:
1305 case E_GOP_DUALRATE_OP_MUX2:
1306 // to prevent warning log
1307 break;
1308 default:
1309 printf("[%s]ERROR, not support the mux[%d]\n",__FUNCTION__,eGopMux);
1310 break;
1311 }
1312 //Transform GOPNum for app user
1313 *u8GOPNum = GOPNUM_TRANSFORM_INVERSE(*u8GOPNum);
1314 }
1315
HAL_GOP_GWIN_SetMUX(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_U8 u8GOPNum,Gop_MuxSel eGopMux)1316 void HAL_GOP_GWIN_SetMUX(GOP_CTX_HAL_LOCAL*pGOPHalLocal, MS_U8 u8GOPNum, Gop_MuxSel eGopMux)
1317 {
1318 MS_U16 u16Ret[4]={0};
1319 u8GOPNum = GOPNUM_TRANSFORM(u8GOPNum);
1320
1321 switch(eGopMux)
1322 {
1323 case E_GOP_MUX0:
1324 case E_GOP_MUX1:
1325 case E_GOP_MUX2:
1326 case E_GOP_MUX3:
1327 case E_GOP_MUX4:
1328 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_MUX, u8GOPNum <<(GOP_MUX_SHIFT*eGopMux), GOP_REGMUX_MASK<<(GOP_MUX_SHIFT*eGopMux));
1329 if(g_GopChipPro.bOPMuxDoubleBuffer == TRUE)
1330 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_BAK_SEL_EX, GOP_BIT14 , GOP_BIT14); //SC_0 Mux trigger
1331 break;
1332 case E_GOP_OP1_MUX:
1333 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_MUX_SC1, u8GOPNum <<12, GOP_REGMUX_MASK<<12);
1334 if(g_GopChipPro.bOPMuxDoubleBuffer == TRUE)
1335 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_BAK_SEL_EX, GOP_BIT13 , GOP_BIT13); //SC_1 Mux trigger
1336 break;
1337 case E_GOP_IP0_MUX:
1338 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_MUX_IPVOP, u8GOPNum << GOP_IP_MAIN_MUX_SHIFT, GOP_IP_MAIN_MUX_MASK);
1339 break;
1340 case E_GOP_IP1_MUX:
1341 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_MUX_4K2K, u8GOPNum << 0, BMASK(2:0));
1342 break;
1343 case E_GOP_VOP0_MUX:
1344 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_MUX_IPVOP, u8GOPNum << GOP_IP_VOP0_MUX_SHIFT, GOP_IP_VOP0_MUX_MASK);
1345 break;
1346 case E_GOP_VOP1_MUX:
1347 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_MUX_IPVOP, u8GOPNum << GOP_IP_VOP1_MUX_SHIFT, GOP_IP_VOP1_MUX_MASK);
1348 break;
1349 case E_GOP_Mix_MUX0:
1350 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_MUX4_MIX_VE, u8GOPNum << GOP_Mix_MUX0_SHIFT, GOP_Mix_MUX0_MASK);
1351 break;
1352 case E_GOP_Mix_MUX1:
1353 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_MUX4_MIX_VE, u8GOPNum << GOP_Mix_MUX1_SHIFT, GOP_Mix_MUX1_MASK);
1354 break;
1355 case E_GOP_VE0_MUX:
1356 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_MUX4_MIX_VE, u8GOPNum << GOP_VE0_MUX_SHIFT, GOP_VE0_MUX_MASK);
1357 break;
1358 case E_GOP_VE1_MUX:
1359 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_MUX4_MIX_VE, u8GOPNum << GOP_VE1_MUX_SHIFT, GOP_VE1_MUX_MASK);
1360 break;
1361 case E_GOP_DIP_MUX:
1362 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_MUX_4K2K, u8GOPNum << GOP_DIP_MUX_SHIFT, GOP_DIP_MUX_MASK);
1363 break;
1364 case E_GOP_FRC_MUX0:
1365 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_MUX_4K2K, u8GOPNum <<(GOP_FRC_MUX_SHIFT*(eGopMux%E_GOP_FRC_MUX0)) , GOP_REGMUX_MASK<<(GOP_FRC_MUX_SHIFT*(eGopMux%E_GOP_FRC_MUX0)));
1366 break;
1367 case E_GOP_FRC_MUX1:
1368 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_MUX_4K2K, u8GOPNum <<(GOP_FRC_MUX_SHIFT*(eGopMux%E_GOP_FRC_MUX0)) , GOP_REGMUX_MASK<<(GOP_FRC_MUX_SHIFT*(eGopMux%E_GOP_FRC_MUX0)));
1369 break;
1370 case E_GOP_FRC_MUX2:
1371 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_MUX_4K2K, u8GOPNum <<(GOP_FRC_MUX_SHIFT*(eGopMux%E_GOP_FRC_MUX0)) , GOP_REGMUX_MASK<<(GOP_FRC_MUX_SHIFT*(eGopMux%E_GOP_FRC_MUX0)));
1372 break;
1373 case E_GOP_FRC_MUX3:
1374 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_MUX_4K2K, u8GOPNum <<(GOP_FRC_MUX_SHIFT*(eGopMux%E_GOP_FRC_MUX0)) , GOP_REGMUX_MASK<<(GOP_FRC_MUX_SHIFT*(eGopMux%E_GOP_FRC_MUX0)));
1375 break;
1376 case E_GOP_BYPASS_MUX0:
1377 //Check MUX is using? Checking from priority high to low
1378 HAL_GOP_Read16Reg(pGOPHalLocal, GOP_SC_FRC_LAYER2_L_EN, &u16Ret[0]);
1379 HAL_GOP_Read16Reg(pGOPHalLocal, GOP_SC_FRC_LAYER2_R_EN, &u16Ret[1]);
1380 HAL_GOP_Read16Reg(pGOPHalLocal, GOP_SC_FRC_LAYER1_L_EN, &u16Ret[2]);
1381 HAL_GOP_Read16Reg(pGOPHalLocal, GOP_SC_FRC_LAYER1_R_EN, &u16Ret[3]);
1382
1383 //Checking if un-use
1384 if((u16Ret[0] & GOP_BIT0) ==0)
1385 {
1386 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_MUX_4K2K, u8GOPNum <<(GOP_FRC_MUX_SHIFT*(E_GOP_FRC_MUX2%E_GOP_FRC_MUX0)) , GOP_REGMUX_MASK<<(GOP_FRC_MUX_SHIFT*(E_GOP_FRC_MUX2%E_GOP_FRC_MUX0)));
1387 }
1388 else if((u16Ret[1] & GOP_BIT0) ==0)
1389 {
1390 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_MUX_4K2K, u8GOPNum <<(GOP_FRC_MUX_SHIFT*(E_GOP_FRC_MUX3%E_GOP_FRC_MUX0)) , GOP_REGMUX_MASK<<(GOP_FRC_MUX_SHIFT*(E_GOP_FRC_MUX3%E_GOP_FRC_MUX0)));
1391 }
1392 else if((u16Ret[2] & GOP_BIT0) ==0)
1393 {
1394 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_MUX_4K2K, u8GOPNum <<(GOP_FRC_MUX_SHIFT*(E_GOP_FRC_MUX0%E_GOP_FRC_MUX0)) , GOP_REGMUX_MASK<<(GOP_FRC_MUX_SHIFT*(E_GOP_FRC_MUX0%E_GOP_FRC_MUX0)));
1395 }
1396 else if((u16Ret[3] & GOP_BIT0) ==0)
1397 {
1398 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_MUX_4K2K, u8GOPNum <<(GOP_FRC_MUX_SHIFT*(E_GOP_FRC_MUX1%E_GOP_FRC_MUX0)) , GOP_REGMUX_MASK<<(GOP_FRC_MUX_SHIFT*(E_GOP_FRC_MUX1%E_GOP_FRC_MUX0)));
1399 }
1400 else
1401 {
1402 printf("[%s][%d]FRC mux is already full.\n",__FUNCTION__,__LINE__);
1403 }
1404 break;
1405 break;
1406 default:
1407 printf("[%s]ERROR mux setting\n",__FUNCTION__);
1408 break;
1409 }
1410 }
1411
HAL_GOP_SetGOPEnable2SC(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_U8 gopNum,MS_BOOL bEnable)1412 GOP_Result HAL_GOP_SetGOPEnable2SC(GOP_CTX_HAL_LOCAL *pGOPHalLocal, MS_U8 gopNum, MS_BOOL bEnable)
1413 {
1414 /* GOP OP Path enable to SC Setting
1415 A5: GOP OP Path blending with SC sequence
1416 mux1-->mux0-->mux2-->mux3
1417 */
1418 MS_BOOL bOSDBEnable=TRUE;
1419 MS_U16 muxValue=0, mux4Value=0, regval=0;
1420
1421 DRV_GOPDstType pGopDst = E_DRV_GOP_DST_INVALID;
1422 MS_U16 u164K2KMuxValue=0;
1423 MS_U8 u8GopNumTemp = 0;//save the gop num after convert
1424
1425 if(gopNum >= MAX_GOP_SUPPORT)
1426 {
1427 printf("[%s][%d] Out of GOP support!!! GOP=%d\n",__FUNCTION__,__LINE__ ,gopNum);
1428 return GOP_FAIL;
1429 }
1430 u8GopNumTemp = GOPNUM_TRANSFORM(gopNum);
1431 HAL_GOP_Read16Reg(pGOPHalLocal, GOP_MUX, &muxValue);
1432 if(bOSDBEnable)
1433 {
1434 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_SC_GOPEN, 0x0, GOP_REG_HW_MASK);
1435
1436 }else
1437 {
1438 HAL_GOP_Read16Reg(pGOPHalLocal, GOP_SC_GOPEN, ®val);
1439 }
1440
1441 if (u8GopNumTemp == (muxValue & GOP_MUX0_MASK)) //enable mux0 to SC
1442 {
1443 if(bOSDBEnable)
1444 {
1445 if(bEnable)
1446 {
1447 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_SC_VOP2BLENDING_L, 0<<1, GOP_BIT1|GOP_BIT2);
1448 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_SC_VOP2BLENDING_L, GOP_BIT3, GOP_BIT3);
1449 }else{
1450 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_SC_VOP2BLENDING_L, 0, GOP_BIT3);
1451 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_SC_VOP2BLENDING_L, 0<<1, GOP_BIT1|GOP_BIT2);
1452 }
1453 }
1454 else
1455 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_SC_GOPEN, bEnable?(regval |GOP_BIT15):(regval & ~GOP_BIT15), GOP_BIT15);
1456 }
1457
1458 if (u8GopNumTemp == ((muxValue & GOP_MUX1_MASK)>>(GOP_MUX_SHIFT*1))) //enable mux1
1459 {
1460 if(bOSDBEnable)
1461 {
1462 if(bEnable)
1463 {
1464 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_SC_VOP2BLENDING_L, 1<<9, GOP_BIT9|GOP_BIT10);
1465 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_SC_VOP2BLENDING_L, GOP_BIT11, GOP_BIT11);
1466 }else{
1467 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_SC_VOP2BLENDING_L, 0, GOP_BIT11);
1468 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_SC_VOP2BLENDING_L, 1<<9, GOP_BIT9|GOP_BIT10);
1469 }
1470 }
1471 else
1472 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_SC_GOPEN, bEnable?(regval | GOP_BIT12):(regval & ~GOP_BIT12), GOP_BIT12);
1473 }
1474
1475 if (u8GopNumTemp == ((muxValue & GOP_MUX2_MASK)>>(GOP_MUX_SHIFT*2))) //enable mux2
1476 {
1477 if(bOSDBEnable)
1478 {
1479 if(bEnable)
1480 {
1481 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_SC_VOP2BLENDING_H, 2<<1, GOP_BIT1|GOP_BIT2);
1482 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_SC_VOP2BLENDING_H, GOP_BIT3, GOP_BIT3);
1483 }else{
1484 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_SC_VOP2BLENDING_H, 0, GOP_BIT3);
1485 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_SC_VOP2BLENDING_H, 2<<1, GOP_BIT1|GOP_BIT2);
1486 }
1487 }
1488 else
1489 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_SC_GOPEN, bEnable?(regval |GOP_BIT14):(regval & ~GOP_BIT14), GOP_BIT14);
1490 }
1491
1492 if (u8GopNumTemp == ((muxValue & GOP_MUX3_MASK)>>(GOP_MUX_SHIFT*3))) //enable mux3
1493 {
1494 if(bOSDBEnable)
1495 {
1496 if(bEnable)
1497 {
1498 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_SC_VOP2BLENDING_H, 3<<9, GOP_BIT9|GOP_BIT10);
1499 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_SC_VOP2BLENDING_H, GOP_BIT11, GOP_BIT11);
1500 }else{
1501 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_SC_VOP2BLENDING_H, 0, GOP_BIT11);
1502 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_SC_VOP2BLENDING_H, 3<<9, GOP_BIT9|GOP_BIT10);
1503 }
1504 }
1505 else
1506 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_SC_GOPEN, bEnable?(regval |GOP_BIT13):(regval & ~GOP_BIT13), GOP_BIT13);
1507 }
1508
1509 if (u8GopNumTemp == ((muxValue & GOP_MUX4_MASK)>>(GOP_MUX_SHIFT*4))) //enable mux4
1510 {
1511 if(bOSDBEnable)
1512 {
1513 if(bEnable)
1514 {
1515 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_SC_VOP2BLENDING_EX, GOP_BIT3, GOP_BIT3);
1516 }else{
1517 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_SC_VOP2BLENDING_EX, 0, GOP_BIT3);
1518 }
1519 }
1520 else
1521 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_SC_GOPEN, bEnable?(regval |GOP_BIT11):(regval & ~GOP_BIT11), GOP_BIT11);
1522 }
1523
1524 if(MAX_GOP_SUPPORT ==5)
1525 {
1526 HAL_GOP_Read16Reg(pGOPHalLocal, GOP_MUX4_MIX_VE, &mux4Value);
1527 if (u8GopNumTemp == ((mux4Value & GOP_MUX4_MASK)>> GOP_MUX4_SHIFT)) //enable mux4
1528 {
1529 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_SC_GOPEN, bEnable?(regval |GOP_BIT11):(regval & ~GOP_BIT11), GOP_BIT11);
1530 }
1531 }
1532
1533 /*For FRC mux switch*/
1534 HAL_GOP_GetGOPDst(pGOPHalLocal, gopNum, &pGopDst);
1535 HAL_GOP_Read16Reg(pGOPHalLocal, GOP_MUX_4K2K, &u164K2KMuxValue);
1536 if (gopNum== (u164K2KMuxValue & GOP_MUX0_MASK))
1537 {
1538 /* Switch FRC blending */
1539 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_SC_FRC_LAYER1_L_EN, (pGopDst==E_DRV_GOP_DST_BYPASS)?GOP_BIT0: ~GOP_BIT0, GOP_BIT0);
1540 }
1541
1542 if (gopNum== ((u164K2KMuxValue & GOP_MUX1_MASK)>>(GOP_MUX_SHIFT*1)))
1543 {
1544 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_SC_FRC_LAYER1_R_EN, (pGopDst==E_DRV_GOP_DST_BYPASS)?GOP_BIT0: ~GOP_BIT0, GOP_BIT0);
1545 }
1546
1547 if (gopNum== ((u164K2KMuxValue & GOP_MUX2_MASK)>>(GOP_MUX_SHIFT*2)))
1548 {
1549 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_SC_FRC_LAYER2_L_EN, (pGopDst==E_DRV_GOP_DST_BYPASS)?GOP_BIT0: ~GOP_BIT0, GOP_BIT0);
1550 }
1551
1552 if (gopNum== ((u164K2KMuxValue & GOP_MUX3_MASK)>>(GOP_MUX_SHIFT*3)))
1553 {
1554 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_SC_FRC_LAYER2_R_EN, (pGopDst==E_DRV_GOP_DST_BYPASS)?GOP_BIT0: ~GOP_BIT0, GOP_BIT0);
1555 }
1556
1557 return GOP_SUCCESS;
1558 }
1559
HAL_GOP_SetGOP2Pto1P(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_U8 gopNum,MS_BOOL bEnable)1560 GOP_Result HAL_GOP_SetGOP2Pto1P(GOP_CTX_HAL_LOCAL *pGOPHalLocal, MS_U8 gopNum, MS_BOOL bEnable)
1561 {
1562 MS_U32 u32pBankOffSet=0;
1563 MS_U16 u16Regval;
1564
1565 if(g_GopChipPro.b2Pto1PSupport)
1566 {
1567 _GetBnkOfstByGop(gopNum, &u32pBankOffSet);
1568 HAL_GOP_Read16Reg(pGOPHalLocal, u32pBankOffSet + GOP_4G_SRAM_BORROW, &u16Regval);
1569 HAL_GOP_Write16Reg(pGOPHalLocal, u32pBankOffSet + GOP_4G_SRAM_BORROW, bEnable?(u16Regval |GOP_BIT11):(u16Regval & ~GOP_BIT11), GOP_BIT11);
1570 }
1571 return GOP_SUCCESS;
1572 }
1573
HAL_GOP_SetGOPEnable2Mode1(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_U8 gopNum,MS_BOOL bEnable)1574 GOP_Result HAL_GOP_SetGOPEnable2Mode1(GOP_CTX_HAL_LOCAL *pGOPHalLocal, MS_U8 gopNum, MS_BOOL bEnable)
1575 {
1576 /* GOP OP Path enable to SC Setting
1577 A5: GOP OP Path blending with SC sequence
1578 mux1-->mux0-->mux2-->mux3
1579 */
1580 MS_U16 muxValue=0, regval=0;
1581
1582 if(gopNum >= MAX_GOP_SUPPORT)
1583 {
1584 printf("[%s][%d] Out of GOP support!!! GOP=%d\n",__FUNCTION__,__LINE__ ,gopNum );
1585 return FALSE;
1586 }
1587
1588 HAL_GOP_Read16Reg(pGOPHalLocal, GOP_MUX, &muxValue);
1589 HAL_GOP_Read16Reg(pGOPHalLocal, GOP_SC_GOPENMODE1, ®val);
1590 if (gopNum== (muxValue & GOP_MUX0_MASK)) //enable mux0 to SC
1591 {
1592 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_SC_GOPENMODE1, bEnable?(regval |0x10):(regval & ~0x10), 0x30);
1593 }
1594 else if (gopNum== ((muxValue & GOP_MUX1_MASK)>>(GOP_MUX_SHIFT*1))) //enable mux1
1595 {
1596 //printf("");
1597 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_SC_GOPENMODE1, bEnable?(regval |0x1000):(regval & ~0x1000), 0x3000);
1598 }
1599 else if (gopNum== ((muxValue & GOP_MUX2_MASK)>>(GOP_MUX_SHIFT*2))) //enable mux2
1600 {
1601 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_SC_GOPENMODE1, bEnable?(regval |0x40):(regval & ~0x40), 0xC0);
1602 }
1603 else if (gopNum== ((muxValue & GOP_MUX3_MASK)>>(GOP_MUX_SHIFT*3))) //enable mux3
1604 {
1605 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_SC_GOPENMODE1, bEnable?(regval |0x100):(regval & ~0x100), 0x300);
1606 }
1607 else if (gopNum== ((muxValue & GOP_MUX4_MASK)>> (GOP_MUX_SHIFT*4))) //enable mux4
1608 {
1609 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_SC_GOPENMODE1, bEnable?(regval |0x4000):(regval & ~0x4000), 0xc000);
1610 }
1611 else
1612 {
1613 return GOP_FAIL;
1614 }
1615 return GOP_SUCCESS;
1616 }
1617
HAL_GOP_GetGOPAlphaMode1(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_U8 gopNum,MS_BOOL * pbEnable)1618 GOP_Result HAL_GOP_GetGOPAlphaMode1(GOP_CTX_HAL_LOCAL *pGOPHalLocal, MS_U8 gopNum, MS_BOOL *pbEnable)
1619 {
1620 MS_U16 muxValue=0;
1621 MS_U16 regval37=0;
1622 MS_U16 regval38=0;
1623
1624 if(gopNum >= MAX_GOP_SUPPORT)
1625 {
1626 printf("[%s][%d] Out of GOP support!!! GOP=%d\n",__FUNCTION__,__LINE__ ,gopNum );
1627 return FALSE;
1628 }
1629
1630 HAL_GOP_Read16Reg(pGOPHalLocal, GOP_MUX, &muxValue);
1631 HAL_GOP_Read16Reg(pGOPHalLocal, GOP_SC_VOP2BLENDING_L, ®val37);
1632 HAL_GOP_Read16Reg(pGOPHalLocal, GOP_SC_VOP2BLENDING_H, ®val38);
1633 if (gopNum== (muxValue & GOP_MUX0_MASK)) //enable mux0 to SC
1634 {
1635 *pbEnable = (regval37& GOP_BIT5) == GOP_BIT5;
1636 }
1637 else if (gopNum== ((muxValue & GOP_MUX1_MASK)>>(GOP_MUX_SHIFT*1))) //enable mux1
1638 {
1639 *pbEnable = (regval37 & GOP_BIT13) == GOP_BIT13;
1640 }
1641 else if (gopNum== ((muxValue & GOP_MUX2_MASK)>>(GOP_MUX_SHIFT*2))) //enable mux2
1642 {
1643 *pbEnable = (regval38 & GOP_BIT5) == GOP_BIT5;
1644 }
1645 else if (gopNum== ((muxValue & GOP_MUX3_MASK)>>(GOP_MUX_SHIFT*3))) //enable mux3
1646 {
1647 *pbEnable = (regval38 & GOP_BIT13) == GOP_BIT13;
1648 }
1649 else
1650 {
1651 return GOP_FAIL;
1652 }
1653 return GOP_SUCCESS;
1654 }
1655
HAL_GOP_SetGOPHighPri(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_U8 gopNum)1656 GOP_Result HAL_GOP_SetGOPHighPri(GOP_CTX_HAL_LOCAL *pGOPHalLocal, MS_U8 gopNum)
1657 {
1658 /*T8
1659 OP path: support 4 mux (mux0, mux1, mux 2, mux3) to blend with SC simultaneously
1660 IP path: support mux0 and mux1 to IPMain/IPSub. Only one mux of mux0 and mux1 can be blended to IPMain/IPSub
1661 */
1662 MS_U16 Mux3Gop, muxValue=0, i;
1663 MS_U16 MuxShift;
1664
1665 MuxShift = GOP_MUX_SHIFT * E_GOP_MUX3;
1666
1667 HAL_GOP_Read16Reg(pGOPHalLocal, GOP_MUX, &muxValue);
1668 for (i=0; i<MAX_GOP_MUX;i++) //T8 4 mux
1669 {
1670 if (gopNum== ((muxValue&(GOP_REGMUX_MASK<<(i*GOP_MUX_SHIFT)))>>(i*GOP_MUX_SHIFT)))
1671 {
1672 Mux3Gop = (muxValue&GOP_MUX3_MASK)>> MuxShift; //save mux2 gop
1673
1674 muxValue &= ~GOP_MUX3_MASK; //clear mux2 setting
1675 muxValue &= ~(GOP_REGMUX_MASK<<(i*GOP_MUX_SHIFT)); //clear current mux setting
1676 muxValue |= ((gopNum<< MuxShift)|(Mux3Gop<<(i*GOP_MUX_SHIFT)));
1677 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_MUX, muxValue, GOP_REG_WORD_MASK);
1678
1679 if(g_GopChipPro.bOPMuxDoubleBuffer == TRUE)
1680 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_BAK_SEL_EX, GOP_BIT14 , GOP_BIT14); //SC_0 Mux trigger
1681
1682 break;
1683
1684 }
1685
1686 }
1687 return GOP_SUCCESS;
1688 }
1689
HAL_GOP_SetGOPClk(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_U8 gopNum,DRV_GOPDstType eDstType)1690 GOP_Result HAL_GOP_SetGOPClk(GOP_CTX_HAL_LOCAL *pGOPHalLocal, MS_U8 gopNum, DRV_GOPDstType eDstType)
1691 {
1692 /*T8 GOP dst type:
1693 0: IP (Main)
1694 1: IP (Sub)
1695 2: OP
1696 3: MVOP
1697 */
1698
1699 if(gopNum >= MAX_GOP_SUPPORT)
1700 {
1701 printf("[%s][%d] Out of GOP support!!! GOP=%d\n",__FUNCTION__,__LINE__ ,gopNum);
1702 MS_ASSERT(0);
1703 return GOP_INVALID_PARAMETERS;
1704 }
1705 /* Monaco clkgen setting */
1706 /******************
1707 0: odclk
1708 1: idclk_f2 (ipm)
1709 2: idclk_f1 (ips)
1710 3: ocmixer
1711 4: ve
1712 5 : mvop main
1713 6 : mvop sub
1714 ******************/
1715
1716 switch(eDstType)
1717 {
1718 case E_DRV_GOP_DST_IP0:
1719 if (gopNum==E_GOP0)
1720 {
1721 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_GOPCLK, CKG_GOPG0_IDCLK2, CKG_GOPG0_MASK);
1722 }
1723 else if (gopNum==E_GOP1)
1724 {
1725 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_GOPCLK, CKG_GOPG1_IDCLK2, CKG_GOPG1_MASK);
1726 }
1727 else
1728 {
1729 MS_ASSERT(0);
1730 return GOP_INVALID_PARAMETERS;
1731 }
1732 break;
1733
1734 case E_DRV_GOP_DST_IP0_SUB:
1735 if (gopNum==E_GOP0)
1736 {
1737 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_GOPCLK, CKG_GOPG0_IDCLK2, CKG_GOPG0_MASK);
1738 }
1739 else if (gopNum==E_GOP1)
1740 {
1741 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_GOPCLK, CKG_GOPG1_IDCLK2, CKG_GOPG1_MASK);
1742 }
1743 else
1744 {
1745 MS_ASSERT(0);
1746 return GOP_INVALID_PARAMETERS;
1747 }
1748 break;
1749
1750 case E_DRV_GOP_DST_OP0:
1751 if (gopNum==E_GOP0)
1752 {
1753 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_GOPCLK, CKG_GOPG0_ODCLK, CKG_GOPG0_MASK);
1754 }
1755 else if (gopNum==E_GOP1)
1756 {
1757 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_GOPCLK, CKG_GOPG1_ODCLK, CKG_GOPG1_MASK);
1758 }
1759 else if (gopNum==E_GOP2)
1760 {
1761 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_GOP2CLK, CKG_GOPG2_ODCLK, CKG_GOPG2_MASK);
1762 }else if (gopNum==E_GOP3)
1763 {
1764 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_GOP3CLK, CKG_GOPG3_ODCLK, CKG_GOPG3_MASK);
1765 }else if (gopNum==E_GOP4) // K6 : GOP0~3 and GOP5, NO GOP4. Mapping E_GOP4 to GOP 5 reg
1766 {
1767 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_GOP5CLK, CKG_GOPG5_ODCLK, CKG_GOPG5_MASK);
1768 }else
1769 {
1770 MS_ASSERT(0);
1771 return GOP_INVALID_PARAMETERS;
1772 }
1773 break;
1774
1775 case E_DRV_GOP_DST_IP1:
1776 if (gopNum==E_GOP0)
1777 {
1778 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_GOPCLK, CKG_GOPG0_IDCLK1, CKG_GOPG0_MASK);
1779 }
1780 else if (gopNum==E_GOP1)
1781 {
1782 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_GOPCLK, CKG_GOPG1_IDCLK1, CKG_GOPG1_MASK);
1783 }
1784 else if (gopNum==E_GOP2)
1785 {
1786 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_GOP2CLK, CKG_GOPG2_IDCLK1, CKG_GOPG2_MASK);
1787 }else if (gopNum==E_GOP3)
1788 {
1789 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_GOP3CLK, CKG_GOPG3_IDCLK1, CKG_GOPG3_MASK);
1790 }else if (gopNum==E_GOP4) // K6 : GOP0~3 and GOP5, NO GOP4. Mapping E_GOP4 to GOP 5 reg
1791 {
1792 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_GOP5CLK, CKG_GOPG5_IDCLK1, CKG_GOPG5_MASK);
1793 }else
1794 {
1795 MS_ASSERT(0);
1796 return GOP_INVALID_PARAMETERS;
1797 }
1798 break;
1799
1800 case E_DRV_GOP_DST_OP1:
1801 if (gopNum==E_GOP0)
1802 {
1803 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_GOPCLK, CKG_GOPG0_OD1CLK, CKG_GOPG0_MASK);
1804 }
1805 else if (gopNum==E_GOP1)
1806 {
1807 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_GOPCLK, CKG_GOPG1_OD1CLK, CKG_GOPG1_MASK);
1808 }
1809 else if (gopNum==E_GOP2)
1810 {
1811 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_GOP2CLK, CKG_GOPG2_OD1CLK, CKG_GOPG2_MASK);
1812 }else if (gopNum==E_GOP3)
1813 {
1814 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_GOP3CLK, CKG_GOPG3_OD1CLK, CKG_GOPG3_MASK);
1815 }else if (gopNum==E_GOP4) // K6 : GOP0~3 and GOP5, NO GOP4. Mapping E_GOP4 to GOP 5 reg
1816 {
1817 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_GOP5CLK, CKG_GOPG5_OD1CLK, CKG_GOPG5_MASK);
1818 }else
1819 {
1820 MS_ASSERT(0);
1821 return GOP_INVALID_PARAMETERS;
1822 }
1823 break;
1824
1825 case E_DRV_GOP_DST_DIP:
1826 if (gopNum==E_GOP0)
1827 {
1828 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_GOPCLK, CKG_GOPG0_DIP, CKG_GOPG0_MASK);
1829 }
1830 else if (gopNum==E_GOP1)
1831 {
1832 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_GOPCLK, CKG_GOPG1_DIP, CKG_GOPG1_MASK);
1833 }
1834 else if (gopNum==E_GOP2)
1835 {
1836 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_GOP2CLK, CKG_GOPG2_DIP, CKG_GOPG2_MASK);
1837 }else if (gopNum==E_GOP3)
1838 {
1839 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_GOP3CLK, CKG_GOPG3_DIP, CKG_GOPG3_MASK);
1840 }else if (gopNum==E_GOP4) // K6 : GOP0~3 and GOP5, NO GOP4. Mapping E_GOP4 to GOP 5 reg
1841 {
1842 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_GOP5CLK, CKG_GOPG5_DIP, CKG_GOPG5_MASK);
1843 }else
1844 {
1845 MS_ASSERT(0);
1846 return GOP_INVALID_PARAMETERS;
1847 }
1848 break;
1849
1850 case E_DRV_GOP_DST_VE:
1851 if (gopNum==E_GOP0)
1852 {
1853 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_GOPCLK, CKG_GOPG0_OD1CLK, CKG_GOPG0_MASK);
1854 }
1855 else if (gopNum==E_GOP1)
1856 {
1857 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_GOPCLK, CKG_GOPG1_OD1CLK, CKG_GOPG1_MASK);
1858 }
1859 else if (gopNum==E_GOP2)
1860 {
1861 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_GOP2CLK, CKG_GOPG2_OD1CLK, CKG_GOPG2_MASK);
1862 }else if (gopNum==E_GOP3)
1863 {
1864 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_GOP3CLK, CKG_GOPG3_OD1CLK, CKG_GOPG3_MASK);
1865 }else if (gopNum==E_GOP4) // K6 : GOP0~3 and GOP5, NO GOP4. Mapping E_GOP4 to GOP 5 reg
1866 {
1867 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_GOP5CLK, CKG_GOPG5_OD1CLK, CKG_GOPG5_MASK);
1868 }else
1869 {
1870 MS_ASSERT(0);
1871 return GOP_INVALID_PARAMETERS;
1872 }
1873 break;
1874 default:
1875 MS_ASSERT(0);
1876 return GOP_ENUM_NOT_SUPPORTED;
1877 }
1878
1879 HAL_GOP_Read16Reg(pGOPHalLocal, GOP_GOPCLK, &pGOPHalLocal->u16Clk0Setting); //Backup current GOPG clock settings
1880 HAL_GOP_Read16Reg(pGOPHalLocal, GOP_SRAMCLK,&pGOPHalLocal->u16Clk2Setting); //Backup current SRAM clock settings
1881
1882 return GOP_SUCCESS;
1883 }
1884
1885
HAL_GOP_SetClkForCapture(GOP_CTX_HAL_LOCAL * pGOPHalLocal,DRV_GOP_DWIN_SRC_SEL enSrcSel)1886 GOP_Result HAL_GOP_SetClkForCapture(GOP_CTX_HAL_LOCAL *pGOPHalLocal, DRV_GOP_DWIN_SRC_SEL enSrcSel)
1887 {
1888 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_GOP2CLK, 0, GOP_BIT8);
1889 if (enSrcSel==GOP_DRV_DWIN_SRC_OP)
1890 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_GOPDCLK, CKG_GOPD_CLK_ODCLK, CKG_GOPD_MASK);
1891 else if (enSrcSel==GOP_DRV_DWIN_SRC_MVOP)
1892 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_GOPDCLK, CKG_GOPD_CLK_DC0CLK, CKG_GOPD_MASK);
1893 else if (enSrcSel==GOP_DRV_DWIN_SRC_IP)
1894 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_GOPDCLK, CKG_GOPD_CLK_IDCLK2, CKG_GOPD_MASK);
1895 else
1896 return GOP_INVALID_PARAMETERS;
1897
1898 HAL_GOP_Read16Reg(pGOPHalLocal, GOP_GOP2CLK, &pGOPHalLocal->u16Clk1Setting); //Backup current GOPD clock settings
1899 return GOP_SUCCESS;
1900 }
HAL_GOP_SetClock(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_BOOL bEnable)1901 GOP_Result HAL_GOP_SetClock(GOP_CTX_HAL_LOCAL *pGOPHalLocal,MS_BOOL bEnable)
1902 {
1903 if (bEnable)
1904 {
1905 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_GOPCLK, pGOPHalLocal->u16Clk0Setting, GOP_REG_WORD_MASK);
1906 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_GOP2CLK, pGOPHalLocal->u16Clk1Setting, GOP_REG_WORD_MASK);
1907 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_SRAMCLK, pGOPHalLocal->u16Clk2Setting, GOP_REG_WORD_MASK);
1908 }
1909 else
1910 {
1911 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_GOPCLK, CKG_GOPG0_DISABLE_CLK, CKG_GOPG0_MASK);
1912 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_GOPCLK, CKG_GOPG1_DISABLE_CLK, CKG_GOPG1_MASK);
1913 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_GOP2CLK, CKG_GOPG2_DISABLE_CLK, CKG_GOPG2_MASK);
1914 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_GOPDCLK, CKG_GOPD_DISABLE_CLK, CKG_GOPD_MASK);
1915 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_SRAMCLK, CKG_SRAM0_DISABLE_CLK, CKG_SRAM0_MASK);
1916 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_SRAMCLK, CKG_SRAM1_DISABLE_CLK, CKG_SRAM1_MASK);
1917 }
1918
1919 return GOP_SUCCESS;
1920 }
1921
HAL_GOP_MIXER_SetGOPEnable2Mixer(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_U8 gopNum,MS_BOOL bEnable)1922 GOP_Result HAL_GOP_MIXER_SetGOPEnable2Mixer(GOP_CTX_HAL_LOCAL *pGOPHalLocal, MS_U8 gopNum, MS_BOOL bEnable)
1923 {
1924 DRV_GOPDstType MixerDstType;
1925 MS_U16 regval = 0;
1926 MS_U8 u8MUXGOPNum = 0;
1927 int i = 0;
1928
1929 HAL_GOP_Read16Reg(pGOPHalLocal, GOP_MIXER_CTRL, ®val);
1930 #if 0 //TO DO: To disable mixer mux
1931 MS_U16 u16val;
1932 if( regval & 0x0001) //MIXER GOP0 enable -> enable GOP1
1933 {
1934 u16val = (bEnable? TRUE: FALSE);
1935 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_MIXER_CTRL, (u16val<<1), GOP_BIT1);
1936 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_MIXER_CTRL, (gopNum<<12), (GOP_BIT12|GOP_BIT13));
1937 }
1938 else //enable GOP0
1939 {
1940 u16val = (bEnable? TRUE: FALSE);
1941 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_MIXER_CTRL, u16val, GOP_BIT0);
1942 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_MIXER_CTRL, (gopNum<<10), (GOP_BIT10|GOP_BIT11));
1943 }
1944 #else
1945 if((regval&(GOP_BIT0|GOP_BIT1)) == (GOP_BIT0|GOP_BIT1))
1946 {
1947 if((gopNum != ((regval&(GOP_BIT10|GOP_BIT11))>>10)) && (gopNum != ((regval&(GOP_BIT12|GOP_BIT13))>>12)))
1948 {
1949 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_MIXER_CTRL, GOP_BIT0, GOP_BIT0);
1950 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_MIXER_CTRL, (gopNum<<10), (GOP_BIT10|GOP_BIT11));
1951 }
1952 }
1953 else if(regval&GOP_BIT0)
1954 {
1955 if(gopNum != ((regval&(GOP_BIT10|GOP_BIT11))>>10))
1956 {
1957 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_MIXER_CTRL, GOP_BIT1, GOP_BIT1);
1958 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_MIXER_CTRL, (gopNum<<12), (GOP_BIT12|GOP_BIT13));
1959 }
1960 }
1961 else if(regval&GOP_BIT1) //gop1Enable
1962 {
1963 if(gopNum != ((regval&(GOP_BIT12|GOP_BIT13))>>12))
1964 {
1965 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_MIXER_CTRL, GOP_BIT1, GOP_BIT1);
1966 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_MIXER_CTRL, (gopNum<<12), (GOP_BIT12|GOP_BIT13));
1967 }
1968 }
1969 else //no one enable
1970 {
1971 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_MIXER_CTRL, GOP_BIT0, GOP_BIT0);
1972 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_MIXER_CTRL, (gopNum<<10), (GOP_BIT10|GOP_BIT11));
1973 }
1974 #endif
1975
1976 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_MIXER_CTRL, GOP_BIT7, GOP_BIT7); //disable pseudo hsync
1977
1978 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_MIXER_CTRL, 0x0, GOP_BIT2); //alpha mode: 0 bypass mode: 1
1979
1980 HAL_GOP_GetMixerDst(pGOPHalLocal,&MixerDstType);
1981 if(MixerDstType == E_DRV_GOP_DST_MIXER2OP)
1982 {
1983 for (i=0; i<MAX_GOP_MUX - 1; i++) //mux3 not supported to OP
1984 {
1985 HAL_GOP_GWIN_GetMUX(pGOPHalLocal, &u8MUXGOPNum, (Gop_MuxSel)i);
1986 if (0x4==u8MUXGOPNum)
1987 {
1988 HAL_GOP_EnableSCNewAlphaMode(pGOPHalLocal, (Gop_MuxSel)i, TRUE);
1989 }
1990 else
1991 {
1992 HAL_GOP_EnableSCNewAlphaMode(pGOPHalLocal, (Gop_MuxSel)i, FALSE);
1993 }
1994 }
1995 }
1996 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_MIXER_VE, GOP_MIXER_EN_VFIL, GOP_MIXER_EN_VFIL_MASK);
1997 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_MIXER_VE, GOP_MIXER_VS_FLD_ON, GOP_MIXER_VS_FLD_ON_MASK);
1998 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_MIXER_REG_DUMMY, GOP_BIT0, GOP_BIT0);
1999 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_MIXER_CTRL, GOP_BIT15, GOP_BIT15); //Enable Mixer
2000
2001 //HAL_GOP_Write16Reg(pGOPHalLocal, GOP_MIXER_FHST, GOP_VE_PAL_HSTART_OFST, GOP_REG_WORD_MASK);
2002 //HAL_GOP_Write16Reg(pGOPHalLocal, GOP_MIXER_FVST, GOP_VE_PAL_VSTART_OFST, GOP_REG_WORD_MASK);
2003
2004
2005 //HAL_GOP_Write16Reg(pGOPHalLocal, GOP_4G_HS_PIPE, pGOPHalLocal->pGopChipPro->GOP_MIXER_PD, GOP_REG_WORD_MASK);
2006
2007 #if 0 /* PAL System*/
2008 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_VE_ENABLE_OSD, GOP_BIT0, GOP_BIT0);
2009 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_VE_ENABLE_OSD, GOP_BIT2, GOP_BIT2);
2010 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_MIXER_FHST, GOP_VE_HSTART_OFST, GOP_REG_WORD_MASK);
2011 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_MIXER_FVST, GOP_VE_VSTART_OFST, GOP_REG_WORD_MASK);
2012 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_MIXER_FHEND, 0x330, GOP_REG_WORD_MASK);
2013 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_MIXER_FVEND, 0x25D, GOP_REG_WORD_MASK);
2014 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_MIXER_HTT, GOP_VE_PAL_HTOTAL-1, GOP_REG_WORD_MASK);
2015 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_MIXER_HS_DELAY, GOP_VE_HS_DELAY, GOP_REG_WORD_MASK);
2016 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_4G_HS_PIPE, GOP_MIXER_PD, GOP_REG_WORD_MASK);
2017 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_MIXER_CTRL, GOP_BIT15, GOP_BIT15);
2018 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_MIXER_CTRL, GOP_BIT0, GOP_BIT0);
2019 #endif
2020 return GOP_SUCCESS;
2021
2022 }
2023
HAL_GOP_MIXER_SetMux(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_U8 gopNum,MS_U8 muxNum,MS_BOOL bEnable)2024 GOP_Result HAL_GOP_MIXER_SetMux(GOP_CTX_HAL_LOCAL *pGOPHalLocal, MS_U8 gopNum, MS_U8 muxNum, MS_BOOL bEnable)
2025 {
2026 MS_U16 u16val;
2027
2028 if (muxNum >= MAX_MIXER_MUX)
2029 {
2030 MS_CRITICAL_MSG(printf("\n[%s] not support mux%d in this chip version!!",__FUNCTION__, muxNum));
2031 return GOP_FAIL;
2032 }
2033
2034 if(muxNum==MIXER_MUX0Id) //Set GOP to mux0
2035 {
2036 u16val = (bEnable? TRUE: FALSE);
2037 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_MIXER_CTRL, u16val, GOP_BIT0);
2038 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_MIXER_CTRL, (gopNum<<10), (GOP_BIT10|GOP_BIT11));
2039 }
2040 else //Set GOP to mux1
2041 {
2042 u16val = (bEnable? TRUE: FALSE);
2043 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_MIXER_CTRL, (u16val<<1), GOP_BIT1);
2044 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_MIXER_CTRL, (gopNum<<12), (GOP_BIT12|GOP_BIT13));
2045 }
2046 return GOP_SUCCESS;
2047
2048 }
2049
HAL_GOP_MIXER_EnableOldBlendMode(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_U8 u8GOP,MS_BOOL bEn)2050 GOP_Result HAL_GOP_MIXER_EnableOldBlendMode(GOP_CTX_HAL_LOCAL *pGOPHalLocal, MS_U8 u8GOP, MS_BOOL bEn)
2051 {
2052 MS_U32 u32bankoffset = 0;
2053 DRV_GOPDstType gopDstType = E_DRV_GOP_DST_IP0;
2054 MS_U16 regval = 0x0;
2055
2056 HAL_GOP_GetGOPDst(pGOPHalLocal, u8GOP, &gopDstType);
2057
2058 if(gopDstType == E_DRV_GOP_DST_MIXER2VE)
2059 {
2060
2061 _GetBnkOfstByGop(u8GOP, &u32bankoffset);
2062
2063 if(bEn)
2064 {
2065
2066 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_MIXER_CTRL, GOP_BIT2, GOP_BIT2); //alpha mode: 0 bypass mode: 1
2067 HAL_GOP_Write16Reg(pGOPHalLocal, u32bankoffset + GOP_4G_CTRL0, (MS_U16)~GOP_BIT15, GOP_BIT15);
2068
2069 HAL_GOP_Read16Reg(pGOPHalLocal, GOP_MIXER_CTRL, ®val);
2070
2071 if(u8GOP == ((regval&(GOP_BIT10|GOP_BIT11))>>10))
2072 {
2073 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_VE_TVS_OSD_EN, (~BIT(2))|BIT(1), BIT(1)|BIT(2));
2074 }
2075 else if(u8GOP == ((regval&(GOP_BIT12|GOP_BIT13))>>12))
2076 {
2077 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_VE_TVS_OSD1_EN, (~BIT(2))|BIT(1), BIT(1)|BIT(2));
2078 }
2079 else
2080 {
2081 printf("[%s][%d]GOP not exisit in VE mux\n",__FUNCTION__,__LINE__);
2082 return GOP_FAIL;
2083 }
2084 }
2085 else
2086 {
2087 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_MIXER_CTRL, 0x0, GOP_BIT2); //alpha mode: 0 bypass mode: 1
2088 HAL_GOP_Write16Reg(pGOPHalLocal, u32bankoffset + GOP_4G_CTRL0, (MS_U16)GOP_BIT15, GOP_BIT15);
2089
2090 HAL_GOP_Read16Reg(pGOPHalLocal, GOP_MIXER_CTRL, ®val);
2091
2092 if(u8GOP == ((regval&(GOP_BIT10|GOP_BIT11))>>10))
2093 {
2094 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_VE_TVS_OSD_EN, (~BIT(1))|BIT(2), BIT(1)|BIT(2));
2095 }
2096 else if(u8GOP == ((regval&(GOP_BIT12|GOP_BIT13))>>12))
2097 {
2098 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_VE_TVS_OSD1_EN, (~BIT(1))|BIT(2), BIT(1)|BIT(2));
2099 }
2100 else
2101 {
2102 printf("[%s][%d]GOP not exisit in VE mux\n",__FUNCTION__,__LINE__);
2103 return GOP_FAIL;
2104 }
2105 }
2106 }
2107 else
2108 {
2109 printf("[%s][%d]GOP not on Mixer2VE path\n",__FUNCTION__,__LINE__);
2110 return GOP_FAIL;
2111 }
2112
2113 return GOP_SUCCESS;
2114
2115 }
2116
HAL_GOP_EnableSCNewAlphaMode(GOP_CTX_HAL_LOCAL * pGOPHalLocal,Gop_MuxSel muxNum,MS_BOOL bEnable)2117 GOP_Result HAL_GOP_EnableSCNewAlphaMode(GOP_CTX_HAL_LOCAL *pGOPHalLocal, Gop_MuxSel muxNum, MS_BOOL bEnable)
2118 {
2119 MS_U16 bankTemp = 0;
2120 MS_U16 u16val = 0;
2121
2122 u16val = (bEnable? TRUE: FALSE);
2123 HAL_GOP_Read16Reg(pGOPHalLocal, GOP_SC_BANKSEL, &bankTemp);
2124 switch (muxNum) //Enable OP new alpha mode
2125 {
2126 case 0:
2127 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_SC_BANKSEL, 0x2F, GOP_REG_WORD_MASK);
2128 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_SC_BLEND0_GOP_SWITCH, (u16val<<1), GOP_BIT1);
2129 break;
2130 case 1:
2131 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_SC_BANKSEL, 0x10, GOP_REG_WORD_MASK);
2132 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_SC_ALPHAMODE, (u16val<<6), GOP_BIT6);
2133 break;
2134 case 2:
2135 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_SC_BANKSEL, 0x10, GOP_REG_WORD_MASK);
2136 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_SC_ALPHAMODE, (u16val<<8), GOP_BIT8);
2137 break;
2138 default:
2139 printf("\n [%s],This chip is not support this MUX value!\n",__FUNCTION__);
2140 break;
2141 }
2142 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_SC_BANKSEL, bankTemp, GOP_REG_WORD_MASK);
2143 return GOP_SUCCESS;
2144 }
2145
HAL_GOP_EnableSCPerPixelNewAlphaMode(GOP_CTX_HAL_LOCAL * pGOPHalLocal,Gop_MuxSel muxNum,MS_BOOL bEnable)2146 GOP_Result HAL_GOP_EnableSCPerPixelNewAlphaMode(GOP_CTX_HAL_LOCAL *pGOPHalLocal, Gop_MuxSel muxNum, MS_BOOL bEnable)
2147 {
2148 MS_U16 bankTemp = 0;
2149 MS_U16 u16val = 0;
2150
2151 u16val = (bEnable? TRUE: FALSE);
2152 HAL_GOP_Read16Reg(pGOPHalLocal, GOP_SC_BANKSEL, &bankTemp);
2153 switch (muxNum) //Enable OP per pixel new alpha mode
2154 {
2155 case 0:
2156 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_SC_BANKSEL, 0x2F, GOP_REG_WORD_MASK);
2157 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_SC_BLEND0_GOP_SWITCH, (u16val<<3), GOP_BIT3);
2158 break;
2159 case 1:
2160 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_SC_BANKSEL, 0x10, GOP_REG_WORD_MASK);
2161 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_SC_ALPHAMODE, (u16val<<14), GOP_BIT14);
2162 break;
2163 case 2:
2164 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_SC_BANKSEL, 0x10, GOP_REG_WORD_MASK);
2165 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_SC_ALPHAMODE, (u16val<<15), GOP_BIT15);
2166 break;
2167 default:
2168 printf("\n [%s],This chip is not support this MUX value!\n",__FUNCTION__);
2169 break;
2170 }
2171 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_SC_BANKSEL, bankTemp, GOP_REG_WORD_MASK);
2172 return GOP_SUCCESS;
2173 }
2174
HAL_GOP_Init_Context(GOP_CTX_HAL_LOCAL * pGOPHalLocal,GOP_CTX_HAL_SHARED * pHALShared,MS_BOOL bNeedInitShared)2175 void HAL_GOP_Init_Context(GOP_CTX_HAL_LOCAL *pGOPHalLocal, GOP_CTX_HAL_SHARED *pHALShared, MS_BOOL bNeedInitShared)
2176 {
2177 MS_U32 u32GopIdx;
2178
2179 memset(pGOPHalLocal, 0, sizeof(*pGOPHalLocal));
2180 pGOPHalLocal->pHALShared = pHALShared;
2181
2182 for(u32GopIdx=0; u32GopIdx<MAX_GOP_SUPPORT; u32GopIdx++)
2183 {
2184 pGOPHalLocal->drvGFlipGOPDst[u32GopIdx] = E_DRV_GOP_DST_OP0;
2185 }
2186 pGOPHalLocal->pGopChipPro = &g_GopChipPro;
2187 pGOPHalLocal->pbIsMuxVaildToGopDst = (MS_BOOL *)bIsMuxVaildToGopDst;
2188 }
HAL_GOP_Restore_Ctx(GOP_CTX_HAL_LOCAL * pGOPHalLocal)2189 void HAL_GOP_Restore_Ctx(GOP_CTX_HAL_LOCAL *pGOPHalLocal)
2190 {
2191 }
2192
HAL_ConvertAPIAddr(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_U8 gwinid,MS_PHY * u64Adr)2193 GOP_Result HAL_ConvertAPIAddr(GOP_CTX_HAL_LOCAL *pGOPHalLocal, MS_U8 gwinid, MS_PHY* u64Adr)
2194 {
2195 MS_U8 u8Miu=0xff;
2196 MS_U16 u16RegVal_L=0;
2197 #ifdef GOP_MIU_GROUP2
2198 MS_U16 u16RegVal_H=0;
2199 #endif
2200
2201 HAL_GOP_Read16Reg(pGOPHalLocal, GOP_MIU_GROUP1, &u16RegVal_L);
2202 #ifdef GOP_MIU_GROUP2
2203 HAL_GOP_Read16Reg(pGOPHalLocal, GOP_MIU_GROUP2, &u16RegVal_H);
2204 #endif
2205 if (gwinid<MAX_GOP0_GWIN) //gop0
2206 {
2207 u16RegVal_L &= BIT(GOP_MIU_CLIENT_GOP0);
2208 #ifdef GOP_MIU_GROUP2
2209 u16RegVal_H &= BIT(GOP_MIU_CLIENT_GOP0);
2210 u8Miu = (u16RegVal_L>>GOP_MIU_CLIENT_GOP0) | (u16RegVal_H>>GOP_MIU_CLIENT_GOP0)<<1;
2211 #else
2212 u8Miu = (u16RegVal_L>>GOP_MIU_CLIENT_GOP0);
2213 #endif
2214 }
2215 else if (gwinid>=MAX_GOP0_GWIN && gwinid<MAX_GOP0_GWIN+MAX_GOP1_GWIN) //gop1
2216 {
2217 u16RegVal_L &= BIT(GOP_MIU_CLIENT_GOP1);
2218 #ifdef GOP_MIU_GROUP2
2219 u16RegVal_H &= BIT(GOP_MIU_CLIENT_GOP1);
2220 u8Miu = (u16RegVal_L>>GOP_MIU_CLIENT_GOP1) | (u16RegVal_H>>GOP_MIU_CLIENT_GOP1)<<1;
2221 #else
2222 u8Miu = (u16RegVal_L>>GOP_MIU_CLIENT_GOP1);
2223 #endif
2224 }
2225 else if (gwinid==GOP2_GwinIdBase) //gop2
2226 {
2227 u16RegVal_L &= BIT(GOP_MIU_CLIENT_GOP2);
2228 #ifdef GOP_MIU_GROUP2
2229 u16RegVal_H &= BIT(GOP_MIU_CLIENT_GOP2);
2230 u8Miu = (u16RegVal_L>>GOP_MIU_CLIENT_GOP2) | (u16RegVal_H>>GOP_MIU_CLIENT_GOP2)<<1;
2231 #else
2232 u8Miu = (u16RegVal_L>>GOP_MIU_CLIENT_GOP2);
2233 #endif
2234 }
2235 else if (gwinid==GOP3_GwinIdBase) //gop3
2236 {
2237 u16RegVal_L &= BIT(GOP_MIU_CLIENT_GOP3);
2238 #ifdef GOP_MIU_GROUP2
2239 u16RegVal_H &= BIT(GOP_MIU_CLIENT_GOP3);
2240 u8Miu = (u16RegVal_L>>GOP_MIU_CLIENT_GOP3) | (u16RegVal_H>>GOP_MIU_CLIENT_GOP3)<<1;
2241 #else
2242 u8Miu = (u16RegVal_L>>GOP_MIU_CLIENT_GOP3);
2243 #endif
2244 }
2245 else if (gwinid==GOP5_GwinIdBase) //gop5
2246 {
2247 HAL_GOP_Read16Reg(pGOPHalLocal, GOP5_MIU_GROUP1, &u16RegVal_L);
2248 u16RegVal_L &= BIT(GOP_MIU_CLIENT_GOP5);
2249 u8Miu = (u16RegVal_L>>GOP_MIU_CLIENT_GOP5);
2250 }
2251 else
2252 {
2253 return GOP_FAIL;
2254 }
2255
2256 if (u8Miu <= 2)
2257 {
2258 _miu_offset_to_phy(u8Miu, *u64Adr, *u64Adr);
2259 }
2260 else
2261 {
2262 printf("[%s] ERROR GOP miu client\n",__FUNCTION__);
2263 return GOP_FAIL;
2264 }
2265 return GOP_SUCCESS;
2266 }
2267
HAL_GOP_GetMIUDst(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_U8 gopnum)2268 MS_U8 HAL_GOP_GetMIUDst(GOP_CTX_HAL_LOCAL *pGOPHalLocal, MS_U8 gopnum)
2269 {
2270 MS_U8 u8Miu=0xff;
2271 MS_U16 u16RegVal_L=0;
2272 MS_U32 u32BnkOfst=0xFFFF;
2273 #ifdef GOP_MIU_GROUP2
2274 MS_U16 u16RegVal_H=0;
2275 #endif
2276
2277 if(pGOPHalLocal->pGopChipPro->bInternalMIUSelect[gopnum]==TRUE)
2278 {
2279 _GetBnkOfstByGop(gopnum, &u32BnkOfst);
2280 HAL_GOP_Read16Reg(pGOPHalLocal, u32BnkOfst+GOP_4G_MIU_SEL, &u16RegVal_L);
2281
2282 u8Miu= (u16RegVal_L& (GOP_BIT2|GOP_BIT3)) >>2;
2283 }
2284 else
2285 {
2286 HAL_GOP_Read16Reg(pGOPHalLocal, GOP_MIU_GROUP1, &u16RegVal_L);
2287 #ifdef GOP_MIU_GROUP2
2288 HAL_GOP_Read16Reg(pGOPHalLocal, GOP_MIU_GROUP2, &u16RegVal_H);
2289 #endif
2290 switch (gopnum)
2291 {
2292 case 0:
2293 u16RegVal_L &= BIT(GOP_MIU_CLIENT_GOP0);
2294 #ifdef GOP_MIU_GROUP2
2295 u16RegVal_H &= BIT(GOP_MIU_CLIENT_GOP0);
2296 u8Miu = (u16RegVal_L>>GOP_MIU_CLIENT_GOP0) | (u16RegVal_H>>GOP_MIU_CLIENT_GOP0)<<1;
2297 #else
2298 u8Miu = (u16RegVal_L>>GOP_MIU_CLIENT_GOP0);
2299 #endif
2300 break;
2301 case 1:
2302 u16RegVal_L &= BIT(GOP_MIU_CLIENT_GOP1);
2303 #ifdef GOP_MIU_GROUP2
2304 u16RegVal_H &= BIT(GOP_MIU_CLIENT_GOP1);
2305 u8Miu = (u16RegVal_L>>GOP_MIU_CLIENT_GOP1) | (u16RegVal_H>>GOP_MIU_CLIENT_GOP1)<<1;
2306 #else
2307 u8Miu = (u16RegVal_L>>GOP_MIU_CLIENT_GOP1);
2308 #endif
2309 break;
2310
2311 case 2:
2312 u16RegVal_L &= BIT(GOP_MIU_CLIENT_GOP2);
2313 #ifdef GOP_MIU_GROUP2
2314 u16RegVal_H &= BIT(GOP_MIU_CLIENT_GOP2);
2315 u8Miu = (u16RegVal_L>>GOP_MIU_CLIENT_GOP2) | (u16RegVal_H>>GOP_MIU_CLIENT_GOP2)<<1;
2316 #else
2317 u8Miu = (u16RegVal_L>>GOP_MIU_CLIENT_GOP2);
2318 #endif
2319 break;
2320
2321 case 3:
2322 u16RegVal_L &= BIT(GOP_MIU_CLIENT_GOP3);
2323 #ifdef GOP_MIU_GROUP2
2324 u16RegVal_H &= BIT(GOP_MIU_CLIENT_GOP3);
2325 u8Miu = (u16RegVal_L>>GOP_MIU_CLIENT_GOP3) | (u16RegVal_H>>GOP_MIU_CLIENT_GOP3)<<1;
2326 #else
2327 u8Miu = (u16RegVal_L>>GOP_MIU_CLIENT_GOP3);
2328 #endif
2329 break;
2330 case 4: //GOP5
2331 HAL_GOP_Read16Reg(pGOPHalLocal, GOP5_MIU_GROUP1, &u16RegVal_L);
2332 u8Miu = (u16RegVal_L>>GOP_MIU_CLIENT_GOP5);
2333
2334 default:
2335 return 0xff;
2336 break;
2337 }
2338
2339 if(u8Miu > MAX_GOP_MIUSEL )
2340 {
2341 printf("[%s] ERROR GOP miu client\n",__FUNCTION__);
2342 return 0xff;
2343 }
2344
2345 }
2346 return u8Miu;
2347 }
HAL_GOP_GetGOPDst(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_U8 u8gopNum,DRV_GOPDstType * pGopDst)2348 GOP_Result HAL_GOP_GetGOPDst(GOP_CTX_HAL_LOCAL *pGOPHalLocal, MS_U8 u8gopNum, DRV_GOPDstType *pGopDst)
2349 {
2350 MS_U16 u16Regval;
2351 MS_U32 u32pBankOffSet=0;
2352 GOP_Result ret;
2353
2354 if(u8gopNum >= MAX_GOP_SUPPORT)
2355 {
2356 printf("[%s][%d] Out of GOP support!!! GOP=%d\n",__FUNCTION__,__LINE__ ,u8gopNum);
2357 *pGopDst = E_DRV_GOP_DST_INVALID;
2358 return GOP_FAIL;
2359 }
2360
2361 _GetBnkOfstByGop(u8gopNum, &u32pBankOffSet);
2362 HAL_GOP_Read16Reg(pGOPHalLocal, u32pBankOffSet + GOP_4G_CTRL1, &u16Regval);
2363
2364 switch (u16Regval&GOP_DST_MASK)
2365 {
2366 case 0:
2367 *pGopDst = E_DRV_GOP_DST_IP0;
2368 ret = GOP_SUCCESS;
2369 break;
2370 case 1:
2371 *pGopDst = E_DRV_GOP_DST_IP0_SUB;
2372 ret = GOP_SUCCESS;
2373 break;
2374 case 2:
2375 *pGopDst = E_DRV_GOP_DST_OP0;
2376 ret = GOP_SUCCESS;
2377 break;
2378 case 5:
2379 *pGopDst = E_DRV_GOP_DST_IP1;
2380 ret = GOP_SUCCESS;
2381 break;
2382 case 6:
2383 *pGopDst = E_DRV_GOP_DST_OP1;
2384 ret = GOP_SUCCESS;
2385 break;
2386 case 7:
2387 *pGopDst = E_DRV_GOP_DST_VE;
2388 ret = GOP_SUCCESS;
2389 break;
2390 case 8:
2391 *pGopDst = E_DRV_GOP_DST_DIP;
2392 ret = GOP_SUCCESS;
2393 break;
2394 default:
2395 *pGopDst = E_DRV_GOP_DST_INVALID;
2396 ret = GOP_FAIL;
2397 break;
2398 }
2399
2400 return ret;
2401
2402 }
2403
HAL_GOP_SetIPSel2SC(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_IPSEL_GOP ipSelGop)2404 void HAL_GOP_SetIPSel2SC(GOP_CTX_HAL_LOCAL *pGOPHalLocal, MS_IPSEL_GOP ipSelGop)
2405 {
2406 MS_U16 muxValue=0;
2407 MS_U16 u16RegVal= 0, u16RegMsk = 0;
2408 MS_BOOL bSC1_OP=0,bSC1_IP=0;
2409
2410 HAL_GOP_Read16Reg(pGOPHalLocal, GOP_MUX_IPVOP, &muxValue);
2411
2412 switch(ipSelGop)
2413 {
2414 case MS_DRV_IP0_SEL_GOP0:
2415 u16RegVal = GOP_BIT7 | GOP_BIT5 ;
2416 if(E_GOP0 == (muxValue &GOP_MUX0_MASK))
2417 u16RegVal |= GOP_BIT12;//mux0
2418 else
2419 u16RegVal |= GOP_BIT13;//mux1
2420 u16RegMsk = 0xFFE7;//Skip bit3/4 for GOP_SUB_IP control
2421 bSC1_OP =FALSE;
2422 bSC1_IP =FALSE;
2423 break;
2424
2425 case MS_DRV_IP0_SEL_GOP1:
2426 u16RegVal = GOP_BIT7 | GOP_BIT5 ;
2427 if(E_GOP1 == (muxValue &GOP_MUX0_MASK))
2428 u16RegVal |= GOP_BIT12;//mux0
2429 else
2430 u16RegVal |= GOP_BIT13;//mux1
2431 u16RegMsk = 0xFFE7;//Skip bit3/4 for GOP_SUB_IP control
2432 bSC1_OP =FALSE;
2433 bSC1_IP =FALSE;
2434 break;
2435 case MS_DRV_IP0_SEL_GOP2:
2436 u16RegVal = GOP_BIT7 | GOP_BIT5 ;
2437 if(E_GOP2 == (muxValue &GOP_MUX0_MASK))
2438 u16RegVal |= GOP_BIT12;//mux0
2439 else
2440 u16RegVal |= GOP_BIT13;//mux1
2441 u16RegMsk = 0xFFE7;//Skip bit3/4 for GOP_SUB_IP control
2442 bSC1_OP =FALSE;
2443 bSC1_IP =FALSE;
2444 break;
2445
2446 case MS_DRV_NIP_SEL_GOP0:
2447 if(E_GOP0 == (muxValue &GOP_MUX0_MASK))
2448 {
2449 u16RegVal = ~GOP_BIT12;//mux0
2450 u16RegMsk = GOP_BIT12;
2451 }
2452 else
2453 {
2454 u16RegVal = ~GOP_BIT13;//mux1
2455 u16RegMsk = GOP_BIT13;
2456 }
2457 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_SC_CHANNELSYNC, GOP_BIT11, GOP_BIT11);
2458 bSC1_OP =FALSE;
2459 bSC1_IP =FALSE;
2460 break;
2461
2462 case MS_DRV_NIP_SEL_GOP1:
2463 if(E_GOP1 == (muxValue &GOP_MUX0_MASK))
2464 {
2465 u16RegVal = ~GOP_BIT12;//mux0
2466 u16RegMsk = GOP_BIT12;
2467 }
2468 else
2469 {
2470 u16RegVal = ~GOP_BIT13;//mux1
2471 u16RegMsk = GOP_BIT13;
2472 }
2473 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_SC_CHANNELSYNC, GOP_BIT11, GOP_BIT11);
2474 bSC1_OP =FALSE;
2475 bSC1_IP =FALSE;
2476 break;
2477 case MS_DRV_NIP_SEL_GOP2:
2478 if(E_GOP2 == (muxValue &GOP_MUX0_MASK))
2479 {
2480 u16RegVal = ~GOP_BIT12;//mux0
2481 u16RegMsk = GOP_BIT12;
2482 }
2483 else
2484 {
2485 u16RegVal = ~GOP_BIT13;//mux1
2486 u16RegMsk = GOP_BIT13;
2487 }
2488 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_SC_CHANNELSYNC, GOP_BIT11, GOP_BIT11);
2489 bSC1_OP =FALSE;
2490 bSC1_IP =FALSE;
2491 break;
2492 case MS_DRV_MVOP_SEL:
2493 u16RegVal = GOP_BIT7 | GOP_BIT5 ;
2494 u16RegVal |= GOP_BIT12; //mux0
2495 u16RegMsk = 0xFFE7;//Skip bit3/4 for GOP_SUB_IP control
2496 bSC1_OP =FALSE;
2497 bSC1_IP =FALSE;
2498 break;
2499 case MS_DRV_SC1OP_SEL:
2500 bSC1_OP =TRUE;
2501 bSC1_IP =FALSE;
2502 break;
2503 case MS_DRV_IP1_SEL:
2504 bSC1_OP =FALSE;
2505 bSC1_IP =TRUE;
2506 break;
2507 default:
2508 printf("[%s] ERROR invalid source select\n",__FUNCTION__);
2509 break;
2510 }
2511 if(0 != u16RegMsk)
2512 {
2513 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_SC_CHANNELSYNC, u16RegVal, u16RegMsk);
2514 }
2515
2516 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_SC1_GOPEN, bSC1_OP<<14, GOP_BIT14);
2517 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_SC1_CHANNELSYNC, !bSC1_IP<<11, GOP_BIT11);
2518 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_SC1_CHANNELSYNC, bSC1_IP<<12, GOP_BIT12);
2519
2520 }
2521
HAL_GOP_DWIN_SetSourceSel(GOP_CTX_HAL_LOCAL * pGOPHalLocal,DRV_GOP_DWIN_SRC_SEL enSrcSel)2522 GOP_Result HAL_GOP_DWIN_SetSourceSel(GOP_CTX_HAL_LOCAL *pGOPHalLocal, DRV_GOP_DWIN_SRC_SEL enSrcSel)
2523 {
2524 return GOP_FUN_NOT_SUPPORTED;
2525 }
2526
2527
HAL_GOP_GetDWINMIU(GOP_CTX_HAL_LOCAL * pGOPHalLocal)2528 MS_U8 HAL_GOP_GetDWINMIU(GOP_CTX_HAL_LOCAL *pGOPHalLocal)
2529 {
2530 return GOP_FUN_NOT_SUPPORTED;
2531 }
HAL_GOP_SetDWINMIU(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_U8 miu)2532 GOP_Result HAL_GOP_SetDWINMIU(GOP_CTX_HAL_LOCAL *pGOPHalLocal, MS_U8 miu)
2533 {
2534 return GOP_FUN_NOT_SUPPORTED;
2535 }
2536
HAL_GOP_DWIN_EnableR2YCSC(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_BOOL bEnable)2537 GOP_Result HAL_GOP_DWIN_EnableR2YCSC(GOP_CTX_HAL_LOCAL *pGOPHalLocal, MS_BOOL bEnable)
2538 {
2539 return GOP_FUN_NOT_SUPPORTED;
2540 }
2541
HAL_GOP_VE_SetOutputTiming(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_U32 u32mode)2542 GOP_Result HAL_GOP_VE_SetOutputTiming(GOP_CTX_HAL_LOCAL *pGOPHalLocal, MS_U32 u32mode)
2543 {
2544 if(u32mode == E_GOP_PAL)
2545 {
2546 /* PAL System*/
2547 pGOPHalLocal->pGopChipPro->GOP_VE_PD = 0x73;
2548 pGOPHalLocal->pGopChipPro->GOP_VE_V_Offset = 0x13;
2549 HAL_GOP_Write16Reg(pGOPHalLocal, HAL_GOP_BankOffset(pGOPHalLocal)+GOP_4G_BOT_HS, ~GOP_BIT2, GOP_BIT2);
2550 }
2551 else if(u32mode == E_GOP_NTSC)
2552 {
2553 /* NTSC System*/
2554 pGOPHalLocal->pGopChipPro->GOP_VE_PD = 0x65;
2555 pGOPHalLocal->pGopChipPro->GOP_VE_V_Offset = 0xF;
2556 HAL_GOP_Write16Reg(pGOPHalLocal, HAL_GOP_BankOffset(pGOPHalLocal)+GOP_4G_BOT_HS, GOP_BIT2, GOP_BIT2);
2557 }
2558 return GOP_SUCCESS;
2559 }
2560
HAL_GOP_MIXER_SetOutputTiming(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_U32 u32mode,GOP_DRV_MixerTiming * pTM)2561 GOP_Result HAL_GOP_MIXER_SetOutputTiming(GOP_CTX_HAL_LOCAL *pGOPHalLocal, MS_U32 u32mode, GOP_DRV_MixerTiming *pTM)
2562 {
2563
2564 if(u32mode == E_GOP_PAL)
2565 {
2566 /* PAL System*/
2567 //HAL_GOP_Write16Reg(pGOPHalLocal, GOP_VE_ENABLE_OSD, GOP_BIT0, GOP_BIT0);
2568 //HAL_GOP_Write16Reg(pGOPHalLocal, GOP_VE_ENABLE_OSD, GOP_BIT2, GOP_BIT2);
2569 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_MIXER_FHST, GOP_VE_PAL_HSTART_OFST, GOP_REG_WORD_MASK);
2570 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_MIXER_FVST, GOP_VE_PAL_VSTART_OFST, GOP_REG_WORD_MASK);
2571 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_MIXER_FHEND, GOP_VE_PAL_WIDTH, GOP_REG_WORD_MASK);
2572 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_MIXER_FVEND, GOP_VE_PAL_HEIGHT, GOP_REG_WORD_MASK);
2573 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_MIXER_HTT, GOP_VE_PAL_HTOTAL-1, GOP_REG_WORD_MASK);
2574 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_MIXER_HS_DELAY, GOP_VE_PAL_HS_DELAY, GOP_REG_WORD_MASK);
2575 HAL_GOP_Write16Reg(pGOPHalLocal, HAL_GOP_BankOffset(pGOPHalLocal)+GOP_4G_HS_PIPE, pGOPHalLocal->pGopChipPro->GOP_MIXER_PD, GOP_REG_WORD_MASK);
2576
2577 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_MIXER_CTRL, GOP_BIT15, GOP_BIT15);
2578 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_MIXER_CTRL, GOP_BIT0, GOP_BIT0);
2579 }
2580 else if(u32mode == E_GOP_NTSC)
2581 {
2582 /* NTSC System*/
2583 //HAL_GOP_Write16Reg(pGOPHalLocal, GOP_VE_ENABLE_OSD, GOP_BIT0, GOP_BIT0);
2584 //HAL_GOP_Write16Reg(pGOPHalLocal, GOP_VE_ENABLE_OSD, GOP_BIT2, GOP_BIT2);
2585 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_MIXER_FHST, GOP_VE_NTSC_HSTART_OFST, GOP_REG_WORD_MASK);
2586 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_MIXER_FVST, GOP_VE_NTSC_VSTART_OFST, GOP_REG_WORD_MASK);
2587 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_MIXER_FHEND, GOP_VE_NTSC_WIDTH, GOP_REG_WORD_MASK);
2588 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_MIXER_FVEND, GOP_VE_NTSC_HEIGHT, GOP_REG_WORD_MASK);
2589 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_MIXER_HTT, GOP_VE_NTSC_HTOTAL, GOP_REG_WORD_MASK);
2590 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_MIXER_HS_DELAY, GOP_VE_NTSC_HS_DELAY, GOP_REG_WORD_MASK);
2591
2592 HAL_GOP_Write16Reg(pGOPHalLocal, HAL_GOP_BankOffset(pGOPHalLocal)+GOP_4G_HS_PIPE, pGOPHalLocal->pGopChipPro->GOP_MIXER_PD, GOP_REG_WORD_MASK);
2593
2594 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_MIXER_CTRL, GOP_BIT15, GOP_BIT15);
2595 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_MIXER_CTRL, GOP_BIT0, GOP_BIT0);
2596 }
2597 else if(u32mode == E_GOP_CUSTOM)
2598 {
2599 return GOP_FUN_NOT_SUPPORTED;
2600 /*
2601 //HAL_GOP_Write16Reg(pGOPHalLocal, GOP_VE_ENABLE_OSD, GOP_BIT0, GOP_BIT0);
2602 //HAL_GOP_Write16Reg(pGOPHalLocal, GOP_VE_ENABLE_OSD, GOP_BIT2, GOP_BIT2);
2603 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_MIXER_FHST, pTM->hstart, GOP_REG_WORD_MASK);
2604 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_MIXER_FVST, pTM->vstart, GOP_REG_WORD_MASK);
2605 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_MIXER_FHEND, pTM->hend, GOP_REG_WORD_MASK);
2606 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_MIXER_FVEND, pTM->vend, GOP_REG_WORD_MASK);
2607 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_MIXER_HTT, pTM->htotal, GOP_REG_WORD_MASK);
2608 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_MIXER_HS_DELAY, pTM->hsyncdelay, GOP_REG_WORD_MASK);
2609
2610 HAL_GOP_Write16Reg(pGOPHalLocal, HAL_GOP_BankOffset(pGOPHalLocal)+GOP_4G_HS_PIPE, pGOPHalLocal->pGopChipPro->GOP_MIXER_PD, GOP_REG_WORD_MASK);
2611
2612 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_MIXER_CTRL, GOP_BIT7, GOP_BIT7); //enable pseudo hsync
2613 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_MIXER_CTRL, GOP_BIT15, GOP_BIT15);
2614 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_MIXER_CTRL, GOP_BIT0, GOP_BIT0);
2615 */
2616 }
2617 else if(u32mode == E_GOP_CUSTOM_OP)
2618 {
2619 return GOP_FUN_NOT_SUPPORTED;
2620 }
2621 return GOP_SUCCESS;
2622 }
2623
HAL_GOP_MIXER_EnableVfilter(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_BOOL bEn)2624 GOP_Result HAL_GOP_MIXER_EnableVfilter(GOP_CTX_HAL_LOCAL *pGOPHalLocal, MS_BOOL bEn)
2625 {
2626 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_MIXER_VE, bEn, GOP_MIXER_EN_VFIL_MASK);
2627 return GOP_SUCCESS;
2628 }
2629
HAL_GOP_GWIN_EnableTileMode(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_U8 u8win,MS_BOOL bEnable,E_GOP_TILE_DATA_TYPE tilemode)2630 GOP_Result HAL_GOP_GWIN_EnableTileMode(GOP_CTX_HAL_LOCAL *pGOPHalLocal, MS_U8 u8win, MS_BOOL bEnable, E_GOP_TILE_DATA_TYPE tilemode)
2631 {
2632 //fix me need to modify tile_32bpp mode in 64b_bus
2633 if(E_DRV_GOP_TILE_DATA_16BPP == tilemode)
2634 {
2635 HAL_GOP_Write16Reg(pGOPHalLocal, HAL_GOP_BankOffset(pGOPHalLocal)+GOP_4G_GWIN0_CTRL(u8win), \
2636 bEnable?GOP_BIT15:~GOP_BIT15, GOP_BIT15);
2637 HAL_GOP_Write16Reg(pGOPHalLocal, HAL_GOP_BankOffset(pGOPHalLocal)+GOP_4G_DRAM_FADE(u8win), \
2638 ~GOP_BIT7, GOP_BIT7);
2639
2640 }
2641 else if(E_DRV_GOP_TILE_DATA_32BPP == tilemode)
2642 {
2643 HAL_GOP_Write16Reg(pGOPHalLocal, HAL_GOP_BankOffset(pGOPHalLocal)+GOP_4G_GWIN0_CTRL(u8win), \
2644 bEnable?GOP_BIT15:~GOP_BIT15, GOP_BIT15);
2645 HAL_GOP_Write16Reg(pGOPHalLocal, HAL_GOP_BankOffset(pGOPHalLocal)+GOP_4G_DRAM_FADE(u8win), \
2646 ~GOP_BIT7, GOP_BIT7);
2647 }
2648 else
2649 {
2650 return GOP_FUN_NOT_SUPPORTED;
2651 }
2652
2653 return GOP_SUCCESS;
2654
2655 }
2656
HAL_GOP_SetUVSwap(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_U8 u8GOPNum,MS_BOOL bEn)2657 GOP_Result HAL_GOP_SetUVSwap(GOP_CTX_HAL_LOCAL *pGOPHalLocal, MS_U8 u8GOPNum,MS_BOOL bEn)
2658 {
2659 MS_U32 u32BankOffSet =0;
2660
2661 _GetBnkOfstByGop(u8GOPNum, &u32BankOffSet);
2662
2663 if (bEn)
2664 HAL_GOP_Write16Reg(pGOPHalLocal, u32BankOffSet+GOP_4G_YUV_SWAP, GOP_BIT14, GOP_BIT14);
2665 else
2666 HAL_GOP_Write16Reg(pGOPHalLocal, u32BankOffSet+GOP_4G_YUV_SWAP, ~GOP_BIT14, GOP_BIT14);
2667
2668 return GOP_SUCCESS;
2669 }
2670
HAL_GOP_SetYCSwap(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_U8 u8GOPNum,MS_BOOL bEn)2671 GOP_Result HAL_GOP_SetYCSwap(GOP_CTX_HAL_LOCAL *pGOPHalLocal, MS_U8 u8GOPNum,MS_BOOL bEn)
2672 {
2673 MS_U32 u32BankOffSet =0;
2674
2675 _GetBnkOfstByGop(u8GOPNum, &u32BankOffSet);
2676
2677 if (bEn)
2678 HAL_GOP_Write16Reg(pGOPHalLocal, u32BankOffSet+GOP_4G_YUV_SWAP, GOP_BIT15, GOP_BIT15);
2679 else
2680 HAL_GOP_Write16Reg(pGOPHalLocal, u32BankOffSet+GOP_4G_YUV_SWAP, 0x0, GOP_BIT15);
2681
2682 return GOP_SUCCESS;
2683 }
2684
HAL_GOP_GWIN_GetNewAlphaMode(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_U8 u8win,MS_BOOL * pEnable)2685 GOP_Result HAL_GOP_GWIN_GetNewAlphaMode(GOP_CTX_HAL_LOCAL *pGOPHalLocal, MS_U8 u8win, MS_BOOL* pEnable)
2686 {
2687 MS_U16 u16Val =0x0;
2688 if (u8win < GOP1_GwinIdBase)
2689 {
2690 HAL_GOP_Read16Reg(pGOPHalLocal, GOP_4G_GWIN_ALPHA01(u8win), &u16Val);
2691 *pEnable = (MS_BOOL)(u16Val>>15);
2692 }
2693 else if (u8win < GOP2_GwinIdBase)
2694 {
2695 HAL_GOP_Read16Reg(pGOPHalLocal, GOP_2G_GWIN_ALPHA01(u8win - MAX_GOP0_GWIN), &u16Val);
2696 *pEnable = (MS_BOOL)(u16Val>>15);
2697 }
2698 else if (u8win < GOP3_GwinIdBase)
2699 {
2700 HAL_GOP_Read16Reg(pGOPHalLocal, GOP_1G_GWIN_ALPHA01, &u16Val);
2701 *pEnable = (MS_BOOL)(u16Val>>15);
2702 }
2703 else if (u8win < GOP4_GwinIdBase)
2704 {
2705 HAL_GOP_Read16Reg(pGOPHalLocal, GOP_1GX_GWIN_ALPHA01, &u16Val);
2706 *pEnable = (MS_BOOL)(u16Val>>15);
2707 }
2708 else if (u8win < GOP5_GwinIdBase)
2709 {
2710 HAL_GOP_Read16Reg(pGOPHalLocal, GOP_1GS0_GWIN_ALPHA01, &u16Val);
2711 *pEnable = (MS_BOOL)(u16Val>>15);
2712 }
2713 else
2714 {
2715 printf("%s Not support this GWIN num%d!!!\n",__FUNCTION__, u8win);
2716 return GOP_INVALID_PARAMETERS;
2717 }
2718
2719 return GOP_SUCCESS;
2720 }
2721
HAL_GOP_EnableVENewAlphaMode(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_U8 veMuxNum,MS_BOOL bEnable)2722 GOP_Result HAL_GOP_EnableVENewAlphaMode(GOP_CTX_HAL_LOCAL *pGOPHalLocal, MS_U8 veMuxNum, MS_BOOL bEnable)
2723 {
2724 MS_U16 u16val = 0x0;
2725 u16val = (bEnable? BIT(2): 0);
2726 switch (veMuxNum) //Enable OP per pixel new alpha mode
2727 {
2728 case 0:
2729 //printf("[%s][%d]====enable_new alpha====\n",__FUNCTION__,__LINE__);
2730 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_VE_TVS_OSD_EN, u16val, BIT(2));
2731 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_VE_TVS_OSD_EN_ALPHA_INV, (bEnable? ~(BIT(7)): BIT(7)), BIT(7));
2732 break;
2733
2734 case 1:
2735 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_VE_TVS_OSD1_EN, u16val, BIT(2));
2736 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_VE_TVS_OSD1_EN, (bEnable? ~(BIT(5)): BIT(5)), BIT(5));
2737 break;
2738
2739 default:
2740 printf("\n [%s],This chip is not support this MUX value!\n",__FUNCTION__);
2741 break;
2742 }
2743 return GOP_SUCCESS;
2744 }
2745
HAL_GOP_GWIN_SetNewAlphaMode(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_U8 u8win,MS_BOOL bEnable)2746 GOP_Result HAL_GOP_GWIN_SetNewAlphaMode(GOP_CTX_HAL_LOCAL *pGOPHalLocal, MS_U8 u8win, MS_BOOL bEnable)
2747 {
2748 MS_U8 u8GOP;
2749 MS_U16 u16Val = bEnable << 15;
2750 MS_U16 regval;
2751 DRV_GOPDstType gopDstType;
2752
2753 if (u8win < GOP1_GwinIdBase)
2754 {
2755 u8GOP = 0;
2756 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_4G_GWIN_ALPHA01(u8win), u16Val, GOP_BIT15);
2757 }
2758 else if (u8win < GOP2_GwinIdBase)
2759 {
2760 u8GOP = 1;
2761 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_2G_GWIN_ALPHA01(u8win - MAX_GOP0_GWIN), u16Val, GOP_BIT15);
2762 }
2763 else if (u8win < GOP3_GwinIdBase)
2764 {
2765 u8GOP = 2;
2766 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_1G_GWIN_ALPHA01, u16Val, GOP_BIT15);
2767 }
2768 else if (u8win < GOP4_GwinIdBase)
2769 {
2770 u8GOP = 3;
2771 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_1GX_GWIN_ALPHA01, u16Val, GOP_BIT15);
2772 }
2773 else if (u8win < GOP5_GwinIdBase)
2774 {
2775 u8GOP = 4;
2776 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_1GS0_GWIN_ALPHA01, u16Val, GOP_BIT15);
2777 }
2778 else
2779 {
2780 printf("%s Not support this GWIN num%d!!!\n",__FUNCTION__, u8win);
2781 return GOP_INVALID_PARAMETERS;
2782 }
2783
2784 HAL_GOP_GetGOPDst(pGOPHalLocal, u8GOP, &gopDstType);
2785 if(gopDstType == E_DRV_GOP_DST_VE)
2786 {
2787 HAL_GOP_Read16Reg(pGOPHalLocal, GOP_MUX4_MIX_VE, ®val);
2788 if(u8GOP == ((regval&(GOP_BIT6|GOP_BIT7|GOP_BIT8))>>6))
2789 {
2790 HAL_GOP_EnableVENewAlphaMode(pGOPHalLocal, 0, bEnable);
2791 }
2792 else if(u8GOP == ((regval&(GOP_BIT9|GOP_BIT10|GOP_BIT11))>>9))
2793 {
2794 HAL_GOP_EnableVENewAlphaMode(pGOPHalLocal, 1, bEnable);
2795 }
2796 }
2797
2798 return GOP_SUCCESS;
2799 }
2800
HAL_GOP_GWiN_Set3DOSD_Sub(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_U8 u8GOP,MS_U8 u8Gwin,MS_PHY u32SubAddr)2801 GOP_Result HAL_GOP_GWiN_Set3DOSD_Sub(GOP_CTX_HAL_LOCAL *pGOPHalLocal,MS_U8 u8GOP ,MS_U8 u8Gwin, MS_PHY u32SubAddr)
2802 {
2803 MS_U16 u16Reg = 0;
2804 MS_U32 u32WordBase = 0;
2805 MS_U32 u32BankOffSet=0;
2806
2807 _GetBnkOfstByGop(u8GOP, &u32BankOffSet);
2808
2809 HAL_GOP_Read16Reg(pGOPHalLocal, u32BankOffSet + GOP_4G_BANK_FWR, &u16Reg);
2810
2811 if(u16Reg & GOP_BIT7)
2812 {
2813 u32WordBase = 1;
2814 }
2815 else
2816 {
2817 u32WordBase = GOP_WordUnit;
2818 }
2819
2820 u32SubAddr /= u32WordBase;
2821
2822 if(u8GOP == E_GOP2)
2823 {
2824 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_1G_3DOSD_SUB_RBLK_L, u32SubAddr&GOP_REG_WORD_MASK ,GOP_REG_WORD_MASK );
2825 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_1G_3DOSD_SUB_RBLK_H, u32SubAddr>>16 ,GOP_REG_WORD_MASK );
2826 }
2827 else if(u8GOP == E_GOP3)
2828 {
2829 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_1GX_3DOSD_SUB_RBLK_L, u32SubAddr&GOP_REG_WORD_MASK ,GOP_REG_WORD_MASK );
2830 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_1GX_3DOSD_SUB_RBLK_H, u32SubAddr>>16 ,GOP_REG_WORD_MASK );
2831
2832 }
2833 else if(u8GOP == E_GOP4)
2834 {
2835 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_1GS0_3DOSD_SUB_RBLK_L, u32SubAddr&GOP_REG_WORD_MASK ,GOP_REG_WORD_MASK );
2836 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_1GS0_3DOSD_SUB_RBLK_H, u32SubAddr>>16 ,GOP_REG_WORD_MASK );
2837 }
2838 else if(u8GOP == E_GOP1)
2839 {
2840 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_2G_3DOSD_SUB_RBLK_L(u8Gwin - MAX_GOP0_GWIN), u32SubAddr&GOP_REG_WORD_MASK ,GOP_REG_WORD_MASK );
2841 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_2G_3DOSD_SUB_RBLK_H(u8Gwin - MAX_GOP0_GWIN), u32SubAddr>>16 ,GOP_REG_WORD_MASK );
2842 }
2843 else //gop0
2844 {
2845 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_4G_3DOSD_SUB_RBLK_L(u8Gwin), u32SubAddr&GOP_REG_WORD_MASK ,GOP_REG_WORD_MASK );
2846 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_4G_3DOSD_SUB_RBLK_H(u8Gwin), u32SubAddr>>16 ,GOP_REG_WORD_MASK );
2847 }
2848
2849 return GOP_SUCCESS;
2850
2851 }
2852
2853 //------------------------------------------------------------------------------
2854 /// Set VE output with OSD
2855 /// @return none
2856 //------------------------------------------------------------------------------
HAL_GOP_VE_SetOSDEnable(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_BOOL bEnable,EN_VE_OSD_ENABLE eOSD,MS_U8 gopNum)2857 GOP_Result HAL_GOP_VE_SetOSDEnable(GOP_CTX_HAL_LOCAL *pGOPHalLocal, MS_BOOL bEnable, EN_VE_OSD_ENABLE eOSD, MS_U8 gopNum)
2858 {
2859 MS_U32 u32Reg = 0x0;
2860
2861 if(eOSD == EN_OSD_0)
2862 {
2863 u32Reg = GOP_VE_TVS_OSD_EN;
2864 }
2865 else if(eOSD == EN_OSD_1)
2866 {
2867 u32Reg = GOP_VE_TVS_OSD1_EN;
2868 }
2869
2870 if(bEnable) // enable OSD
2871 {
2872 HAL_GOP_Write16Reg(pGOPHalLocal, u32Reg, BIT(0), BIT(0));
2873 }
2874 else // disable OSD
2875 {
2876 HAL_GOP_Write16Reg(pGOPHalLocal, u32Reg, 0x0, BIT(0));
2877 }
2878 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_VE_TVE_SWRST, BIT(2), BIT(2));
2879 //set VE alpha inverse
2880 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_VE_TVS_OSD1_EN, BIT(5), BIT(5));
2881
2882 return GOP_SUCCESS;
2883 }
2884
HAL_GOP_SetGOPToVE(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_U8 gopNum,MS_BOOL bEn)2885 GOP_Result HAL_GOP_SetGOPToVE(GOP_CTX_HAL_LOCAL *pGOPHalLocal, MS_U8 gopNum, MS_BOOL bEn )
2886 {
2887 MS_U16 regval = 0x0;
2888
2889 HAL_GOP_Read16Reg(pGOPHalLocal, GOP_MUX4_MIX_VE, ®val);
2890 // there are only 2 mux, the 3rd gop will be set to 2nd mux(osd1).
2891 if((gopNum != ((regval&(GOP_BIT6|GOP_BIT7|GOP_BIT8)>>6))) && (gopNum != ((regval&(GOP_BIT9|GOP_BIT10|GOP_BIT11))>>9)))
2892 {
2893 // if have to overwrite one, overwriting INIT VALUE is better.
2894 if (VE_MUX_INIT_VALUE == ((regval&(GOP_BIT6|GOP_BIT7|GOP_BIT8))>>6))
2895 {
2896 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_MUX4_MIX_VE, (gopNum<<6), GOP_BIT6|GOP_BIT7|GOP_BIT8);
2897 HAL_GOP_VE_SetOSDEnable(pGOPHalLocal,bEn, EN_OSD_0, gopNum);
2898 }
2899 else
2900 {
2901 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_MUX4_MIX_VE, (gopNum<<9), (GOP_BIT9|GOP_BIT10|GOP_BIT11));
2902 HAL_GOP_VE_SetOSDEnable(pGOPHalLocal,bEn, EN_OSD_1, gopNum);
2903 }
2904 }
2905 else if(gopNum != ((regval&(GOP_BIT6|GOP_BIT7|GOP_BIT8))>>6))
2906 {
2907 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_MUX4_MIX_VE, (gopNum<<9), (GOP_BIT9|GOP_BIT10|GOP_BIT11));
2908 HAL_GOP_VE_SetOSDEnable(pGOPHalLocal,bEn, EN_OSD_1, gopNum);
2909 }
2910 else
2911 {
2912 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_MUX4_MIX_VE, (gopNum<<6) , GOP_BIT6|GOP_BIT7|GOP_BIT8);
2913 HAL_GOP_VE_SetOSDEnable(pGOPHalLocal,bEn, EN_OSD_0, gopNum);
2914 }
2915 return GOP_SUCCESS;
2916 /*
2917 MS_U32 u32BankOffSet=0;
2918 _GetBnkOfstByGop(gopNum, &u32BankOffSet);
2919
2920 //Direct to SC1 OP
2921 HAL_GOP_SetIPSel2SC(pGOPHalLocal, MS_DRV_SC1OP_SEL);
2922 HAL_GOP_SetGOPClk(pGOPHalLocal, gopNum, E_DRV_GOP_DST_OP1);
2923 HAL_GOP_GWIN_SetMUX(pGOPHalLocal,gopNum,E_GOP_OP1_MUX);
2924 HAL_GOP_Write16Reg(pGOPHalLocal, u32BankOffSet+GOP_4G_CTRL0, (MS_U16)~GOP_BIT1, GOP_BIT1);
2925 HAL_GOP_Write16Reg(pGOPHalLocal, u32BankOffSet + GOP_4G_CTRL0, (MS_U16)GOP_BIT15, GOP_BIT15);
2926 */
2927 return GOP_SUCCESS;
2928 }
2929
HAL_GOP_GetVideoTimingMirrorType(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_BOOL bHorizontal)2930 E_GOP_VIDEOTIMING_MIRRORTYPE HAL_GOP_GetVideoTimingMirrorType(GOP_CTX_HAL_LOCAL *pGOPHalLocal, MS_BOOL bHorizontal)
2931 {
2932 E_GOP_VIDEOTIMING_MIRRORTYPE enMirrorType = E_GOP_VIDEOTIMING_MIRROR_BYSCALER;
2933 MS_U16 u16MVOPMirrorCfg = 0;
2934 MS_U16 u16ScalerMirrorCfg = 0;
2935
2936 HAL_GOP_Read16Reg(pGOPHalLocal, GOP_MVOP_MIRRORCFG, &u16MVOPMirrorCfg);
2937 HAL_GOP_Read16Reg(pGOPHalLocal, GOP_SC_MIRRORCFG, &u16ScalerMirrorCfg);
2938 if(bHorizontal) // Horizontal
2939 {
2940 if(u16MVOPMirrorCfg & GOP_BIT1)
2941 {
2942 enMirrorType = E_GOP_VIDEOTIMING_MIRROR_BYMVOP;
2943 }
2944 else if(u16ScalerMirrorCfg & GOP_BIT12)
2945 {
2946 enMirrorType = E_GOP_VIDEOTIMING_MIRROR_BYSCALER;
2947 }
2948 }
2949 else //vertical
2950 {
2951 if(u16MVOPMirrorCfg & GOP_BIT0)
2952 {
2953 enMirrorType = E_GOP_VIDEOTIMING_MIRROR_BYMVOP;
2954 }
2955 else if(u16ScalerMirrorCfg & GOP_BIT13)
2956 {
2957 enMirrorType = E_GOP_VIDEOTIMING_MIRROR_BYSCALER;
2958 }
2959 }
2960 return enMirrorType;
2961 }
2962
HAL_GOP_3D_SetMiddle(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_U8 u8GOP,MS_U16 u16Middle)2963 GOP_Result HAL_GOP_3D_SetMiddle(GOP_CTX_HAL_LOCAL *pGOPHalLocal,MS_U8 u8GOP,MS_U16 u16Middle)
2964 {
2965 MS_U32 u32BankOffSet =0;
2966
2967 _GetBnkOfstByGop(u8GOP, &u32BankOffSet);
2968 HAL_GOP_Write16Reg(pGOPHalLocal,u32BankOffSet+GOP_4G_3D_MIDDLE, u16Middle, GOP_REG_WORD_MASK);
2969 return GOP_SUCCESS;
2970 }
2971
HAL_GOP_OC_SetOCEn(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_U8 u8GOP,MS_BOOL bOCEn)2972 GOP_Result HAL_GOP_OC_SetOCEn(GOP_CTX_HAL_LOCAL *pGOPHalLocal, MS_U8 u8GOP, MS_BOOL bOCEn)
2973 {
2974 MS_U8 i=0, eGopMux=0, FRCMuxOffset=0;
2975 MS_U16 u16Val=0;
2976 MS_U16 u16Mux[MAX_GOP_MUX];
2977
2978 HAL_GOP_Read16Reg(pGOPHalLocal, GOP_MUX, &u16Val);
2979 u16Mux[0] =( u16Val & GOP_MUX0_MASK);
2980 u16Mux[1] =( u16Val & GOP_MUX1_MASK) >> (GOP_MUX_SHIFT*1);
2981 u16Mux[2] =( u16Val & GOP_MUX2_MASK) >> (GOP_MUX_SHIFT*2);
2982 u16Mux[3] =( u16Val & GOP_MUX3_MASK) >> (GOP_MUX_SHIFT*3);
2983 #if (MAX_GOP_MUX>4)
2984 u16Mux[4] =( u16Val & GOP_MUX4_MASK) >> (GOP_MUX_SHIFT*4);
2985 #endif
2986 switch(u8GOP)
2987 {
2988 case E_GOP0:
2989 case E_GOP1:
2990 case E_GOP2:
2991 case E_GOP3:
2992 #if (MAX_GOP_MUX>4)
2993 case E_GOP4:
2994 #endif
2995 for(i=0; i<MAX_GOP_MUX; i++)
2996 {
2997 if(u8GOP == u16Mux[i])
2998 {
2999 eGopMux = i;
3000 #if (MAX_GOP_MUX>4)
3001 if(eGopMux == 4)
3002 {
3003 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_MUX_4K2K, bOCEn<<15, GOP_BIT15);
3004 }
3005 else
3006 #endif
3007 {
3008 FRCMuxOffset = 12 + eGopMux;
3009 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_MUX_IPVOP, bOCEn<<FRCMuxOffset, 1<<FRCMuxOffset);
3010 }
3011 }
3012 }
3013 break;
3014 default:
3015 return GOP_FAIL;
3016 break;
3017 }
3018
3019 return GOP_SUCCESS;
3020 }
3021
HAL_GOP_OC_SetOCInfo(GOP_CTX_HAL_LOCAL * pGOPHalLocal,DRV_GOP_OC_INFO * pOCinfo)3022 GOP_Result HAL_GOP_OC_SetOCInfo(GOP_CTX_HAL_LOCAL *pGOPHalLocal, DRV_GOP_OC_INFO* pOCinfo)
3023 {
3024 return GOP_FUN_NOT_SUPPORTED;
3025 }
3026
HAL_GOP_OC_Get_MIU_Sel(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_U8 * MIUId)3027 GOP_Result HAL_GOP_OC_Get_MIU_Sel(GOP_CTX_HAL_LOCAL *pGOPHalLocal, MS_U8 *MIUId)
3028 {
3029 return GOP_FUN_NOT_SUPPORTED;
3030 }
3031
HAL_GOP_DWIN_SetRingBuffer(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_U32 u32RingSize,MS_U32 u32BufSize)3032 GOP_Result HAL_GOP_DWIN_SetRingBuffer(GOP_CTX_HAL_LOCAL *pGOPHalLocal, MS_U32 u32RingSize,MS_U32 u32BufSize)
3033 {
3034 return GOP_FUN_NOT_SUPPORTED;
3035 }
3036
HAL_GOP_AdjustField(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_U8 GopNum,DRV_GOPDstType eDstType)3037 GOP_Result HAL_GOP_AdjustField(GOP_CTX_HAL_LOCAL *pGOPHalLocal, MS_U8 GopNum, DRV_GOPDstType eDstType)
3038 {
3039 MS_U32 u32BankOffSet = 0;
3040 MS_BOOL bInverse = 0xFF;
3041 _GetBnkOfstByGop(GopNum, &u32BankOffSet);
3042
3043 switch (eDstType)
3044 {
3045 case E_DRV_GOP_DST_IP0:
3046 case E_DRV_GOP_DST_IP1:
3047 case E_DRV_GOP_DST_OP1:
3048 case E_DRV_GOP_DST_VE:
3049 bInverse = TRUE;
3050 break;
3051 default:
3052 bInverse = FALSE;
3053 break;
3054 }
3055 if(bInverse == TRUE)
3056 {
3057 HAL_GOP_Write16Reg(pGOPHalLocal, u32BankOffSet + GOP_4G_CTRL0, 1<<4, 0x10);
3058 }
3059 else
3060 {
3061 HAL_GOP_Write16Reg(pGOPHalLocal, u32BankOffSet + GOP_4G_CTRL0, 0<<4, 0x10);
3062 }
3063 return GOP_SUCCESS;
3064 }
3065
3066 /********************************************************************************/
3067 ///Test Pattern
3068 /********************************************************************************/
HAL_GOP_TestPattern_IsVaild(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_U8 u8GopNum)3069 GOP_Result HAL_GOP_TestPattern_IsVaild(GOP_CTX_HAL_LOCAL *pGOPHalLocal, MS_U8 u8GopNum)
3070 {
3071 if(u8GopNum == pGOPHalLocal->pGopChipPro->GOP_TestPattern_Vaild)
3072 {
3073 return GOP_SUCCESS;
3074 }
3075 else
3076 {
3077 return GOP_FAIL;
3078 }
3079
3080 }
3081
3082
3083 /********************************************************************************/
3084 ///GOP Scaling down (internal)
3085 /********************************************************************************/
3086
HAL_GOP_EnableScalingDownSram(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_U8 u8GOP,MS_BOOL bEn)3087 MS_BOOL HAL_GOP_EnableScalingDownSram(GOP_CTX_HAL_LOCAL *pGOPHalLocal,MS_U8 u8GOP,MS_BOOL bEn)
3088 {
3089 return GOP_FUN_NOT_SUPPORTED;
3090 }
3091
HAL_GOP_HScalingDown(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_U8 u8GOP,MS_BOOL bEnable,MS_U16 src,MS_U16 dst)3092 GOP_Result HAL_GOP_HScalingDown(GOP_CTX_HAL_LOCAL *pGOPHalLocal,MS_U8 u8GOP, MS_BOOL bEnable,MS_U16 src, MS_U16 dst)
3093 {
3094 return GOP_FUN_NOT_SUPPORTED;
3095 }
3096
HAL_GOP_VScalingDown(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_U8 u8GOP,MS_BOOL bEnable,MS_U16 src,MS_U16 dst)3097 GOP_Result HAL_GOP_VScalingDown(GOP_CTX_HAL_LOCAL *pGOPHalLocal,MS_U8 u8GOP, MS_BOOL bEnable,MS_U16 src, MS_U16 dst)
3098 {
3099 return GOP_FUN_NOT_SUPPORTED;
3100 }
3101
HAL_GOP_DeleteWinHVSize(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_U8 u8GOP,MS_U16 u16HSize,MS_U16 u16VSize)3102 GOP_Result HAL_GOP_DeleteWinHVSize(GOP_CTX_HAL_LOCAL *pGOPHalLocal,MS_U8 u8GOP, MS_U16 u16HSize, MS_U16 u16VSize)
3103 {
3104 MS_U32 u32BankOffSet=0;
3105
3106 _GetBnkOfstByGop(u8GOP, &u32BankOffSet);
3107 HAL_GOP_Write16Reg(pGOPHalLocal, u32BankOffSet + GOP_4G_BANK_HVAILDSIZE, u16HSize, GOP_REG_WORD_MASK);
3108 HAL_GOP_Write16Reg(pGOPHalLocal, u32BankOffSet + GOP_4G_BANK_VVAILDSIZE, u16VSize, GOP_REG_WORD_MASK);
3109 return GOP_SUCCESS;
3110 }
3111
HAL_GOP_DumpGOPReg(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_U32 u32GopIdx,MS_U16 u16BankIdx,MS_U16 u16Addr,MS_U16 * u16Val)3112 GOP_Result HAL_GOP_DumpGOPReg(GOP_CTX_HAL_LOCAL *pGOPHalLocal, MS_U32 u32GopIdx, MS_U16 u16BankIdx, MS_U16 u16Addr, MS_U16* u16Val)
3113 {
3114 MS_U32 u32BankOffSet=0;
3115 _GetBnkOfstByGop(u32GopIdx, &u32BankOffSet);
3116
3117 if (u32GopIdx < MAX_GOP_SUPPORT)
3118 {
3119 HAL_GOP_Read16Reg(pGOPHalLocal, (u32BankOffSet+ (u16BankIdx<<16) + u16Addr +GOP_4G_CTRL0), u16Val);
3120 }
3121 else
3122 {
3123 printf("[%s][%d] Data is zero!!!\n",__FUNCTION__,__LINE__);
3124 *u16Val = 0;
3125 }
3126 return GOP_SUCCESS;
3127 }
3128
HAL_GOP_RestoreGOPReg(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_U32 u32GopIdx,MS_U16 u16BankIdx,MS_U16 u16Addr,MS_U16 u16Val)3129 GOP_Result HAL_GOP_RestoreGOPReg(GOP_CTX_HAL_LOCAL *pGOPHalLocal, MS_U32 u32GopIdx, MS_U16 u16BankIdx, MS_U16 u16Addr, MS_U16 u16Val)
3130 {
3131 MS_U32 u32BankOffSet=0;
3132 _GetBnkOfstByGop(u32GopIdx, &u32BankOffSet);
3133
3134 if (u32GopIdx < MAX_GOP_SUPPORT)
3135 {
3136 HAL_GOP_Write16Reg(pGOPHalLocal, (u32BankOffSet+ (u16BankIdx<<16) + u16Addr +GOP_4G_CTRL0), u16Val, GOP_REG_WORD_MASK);
3137 }
3138 else
3139 {
3140 printf("[%s][%d] Data is zero!!!\n",__FUNCTION__,__LINE__);
3141 }
3142 return GOP_SUCCESS;
3143 }
3144
HAL_GOP_PowerState(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_U32 u32PowerState,GFLIP_REGS_SAVE_AREA * pGOP_STRPrivate)3145 GOP_Result HAL_GOP_PowerState(GOP_CTX_HAL_LOCAL *pGOPHalLocal, MS_U32 u32PowerState, GFLIP_REGS_SAVE_AREA* pGOP_STRPrivate)
3146 {
3147 switch(u32PowerState)
3148 {
3149 case E_POWER_SUSPEND:
3150 {
3151 //CLK
3152 HAL_GOP_Read16Reg(pGOPHalLocal, GOP_GOPCLK, &(pGOP_STRPrivate->CKG_GopReg[0]));
3153 HAL_GOP_Read16Reg(pGOPHalLocal, GOP_GOP2CLK, &(pGOP_STRPrivate->CKG_GopReg[1]));
3154 HAL_GOP_Read16Reg(pGOPHalLocal, GOP_GOP3CLK, &(pGOP_STRPrivate->CKG_GopReg[2]));
3155 HAL_GOP_Read16Reg(pGOPHalLocal, GOP_GOP5CLK, &(pGOP_STRPrivate->CKG_GopReg[3]));
3156 HAL_GOP_Read16Reg(pGOPHalLocal, GOP_SRAMCLK, &(pGOP_STRPrivate->CKG_GopReg[4]));
3157 // HAL_GOP_Read16Reg(pGOPHalLocal, GOP_LB_SRAMCLK, &(pGOP_STRPrivate->CKG_GopReg[5]));
3158
3159 //XC
3160 HAL_GOP_Read16Reg(pGOPHalLocal, GOP_SC_BANKSEL, &(pGOP_STRPrivate->XC_GopReg[0]));
3161 HAL_GOP_Read16Reg(pGOPHalLocal, GOP_SC_CHANNELSYNC, &(pGOP_STRPrivate->XC_GopReg[1]));
3162 HAL_GOP_Read16Reg(pGOPHalLocal, GOP_SC_GOPEN, &(pGOP_STRPrivate->XC_GopReg[2]));
3163 HAL_GOP_Read16Reg(pGOPHalLocal, GOP_SC_IP_SYNC, &(pGOP_STRPrivate->XC_GopReg[3]));
3164 HAL_GOP_Read16Reg(pGOPHalLocal, GOP_SC_IP2GOP_SRCSEL, &(pGOP_STRPrivate->XC_GopReg[4]));
3165 HAL_GOP_Read16Reg(pGOPHalLocal, GOP_SC_OSD_CHECK_ALPHA, &(pGOP_STRPrivate->XC_GopReg[5]));
3166 HAL_GOP_Read16Reg(pGOPHalLocal, GOP_SC_VOPNBL, &(pGOP_STRPrivate->XC_GopReg[6]));
3167 HAL_GOP_Read16Reg(pGOPHalLocal, GOP_SC_GOPENMODE1, &(pGOP_STRPrivate->XC_GopReg[7]));
3168 HAL_GOP_Read16Reg(pGOPHalLocal, GOP_SC_MIRRORCFG, &(pGOP_STRPrivate->XC_GopReg[8]));
3169 HAL_GOP_Read16Reg(pGOPHalLocal, GOP_SC_OCMIXER, &(pGOP_STRPrivate->XC_GopReg[9]));
3170 HAL_GOP_Read16Reg(pGOPHalLocal, GOP_SC_OCMISC, &(pGOP_STRPrivate->XC_GopReg[10]));
3171 HAL_GOP_Read16Reg(pGOPHalLocal, GOP_SC_OCALPHA, &(pGOP_STRPrivate->XC_GopReg[11]));
3172 HAL_GOP_Read16Reg(pGOPHalLocal, GOP_SC_GOPSC_SRAM_CTRL, &(pGOP_STRPrivate->XC_GopReg[12]));
3173 }
3174 break;
3175 case E_POWER_RESUME:
3176 {
3177 //CLK
3178 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_GOPCLK, pGOP_STRPrivate->CKG_GopReg[0], GOP_REG_WORD_MASK);
3179 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_GOP2CLK, pGOP_STRPrivate->CKG_GopReg[1], GOP_REG_WORD_MASK);
3180 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_GOP3CLK, pGOP_STRPrivate->CKG_GopReg[2], GOP_REG_WORD_MASK);
3181 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_GOP5CLK, pGOP_STRPrivate->CKG_GopReg[3], GOP_REG_WORD_MASK);
3182 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_SRAMCLK, pGOP_STRPrivate->CKG_GopReg[4], GOP_REG_WORD_MASK);
3183 // HAL_GOP_Write16Reg(pGOPHalLocal, GOP_LB_SRAMCLK, pGOP_STRPrivate->CKG_GopReg[5], GOP_REG_WORD_MASK);
3184
3185 //XC
3186 //HAL_GOP_Write16Reg(pGOPHalLocal, GOP_SC_BANKSEL, pGOP_STRPrivate->XC_GopReg[0], GOP_REG_WORD_MASK);
3187 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_SC_CHANNELSYNC, pGOP_STRPrivate->XC_GopReg[1], GOP_BIT11);
3188 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_SC_GOPEN, pGOP_STRPrivate->XC_GopReg[2], GOP_REG_WORD_MASK);
3189 //HAL_GOP_Write16Reg(pGOPHalLocal, GOP_SC_IP_SYNC, pGOP_STRPrivate->XC_GopReg[3], GOP_REG_WORD_MASK);
3190 //HAL_GOP_Write16Reg(pGOPHalLocal, GOP_SC_IP2GOP_SRCSEL, pGOP_STRPrivate->XC_GopReg[4], GOP_BIT15);
3191 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_SC_OSD_CHECK_ALPHA, pGOP_STRPrivate->XC_GopReg[5], GOP_BIT6);
3192 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_SC_VOPNBL, pGOP_STRPrivate->XC_GopReg[6], GOP_BIT5);
3193 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_SC_GOPENMODE1, pGOP_STRPrivate->XC_GopReg[7], GOP_REG_WORD_MASK);
3194 //HAL_GOP_Write16Reg(pGOPHalLocal, GOP_SC_MIRRORCFG, pGOP_STRPrivate->XC_GopReg[8], GOP_REG_WORD_MASK);
3195 //HAL_GOP_Write16Reg(pGOPHalLocal, GOP_SC_OCMIXER, pGOP_STRPrivate->XC_GopReg[9], GOP_REG_WORD_MASK);
3196 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_SC_OCMISC, pGOP_STRPrivate->XC_GopReg[10], GOP_BIT2);
3197 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_SC_OCALPHA, pGOP_STRPrivate->XC_GopReg[11], GOP_BIT2);
3198 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_SC_GOPSC_SRAM_CTRL, pGOP_STRPrivate->XC_GopReg[12], GOP_REG_WORD_MASK);
3199 }
3200 break;
3201 default:
3202 break;
3203 }
3204 return GOP_SUCCESS;
3205 }
HAL_GOP_GWIN_SetGPUTileMode(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_U8 gwinid,EN_DRV_GOP_GPU_TILE_MODE tile_mode)3206 GOP_Result HAL_GOP_GWIN_SetGPUTileMode(GOP_CTX_HAL_LOCAL *pGOPHalLocal,MS_U8 gwinid, EN_DRV_GOP_GPU_TILE_MODE tile_mode)
3207 {
3208 return GOP_FUN_NOT_SUPPORTED;
3209 }
3210
HAL_GOP_EnableTLB(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_U8 u8GOP,MS_BOOL bEnable)3211 GOP_Result HAL_GOP_EnableTLB(GOP_CTX_HAL_LOCAL *pGOPHalLocal,MS_U8 u8GOP, MS_BOOL bEnable)
3212 {
3213 MS_U32 u32BankOffSet=0xFFFF;
3214
3215 _GetBnkOfstByGop(u8GOP, &u32BankOffSet);
3216 HAL_GOP_Write16Reg(pGOPHalLocal, u32BankOffSet+GOP_4G_SRAM_BORROW, bEnable?GOP_BIT10:0, GOP_BIT10);
3217
3218 return GOP_SUCCESS;
3219 }
3220
HAL_GOP_SetTLBAddr(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_U8 u8GOP,MS_PHY u64TLBAddr,MS_U32 u32size)3221 GOP_Result HAL_GOP_SetTLBAddr(GOP_CTX_HAL_LOCAL *pGOPHalLocal, MS_U8 u8GOP, MS_PHY u64TLBAddr, MS_U32 u32size)
3222 {
3223 MS_U32 u32BankOffSet=0xFFFF;
3224 _GetBnkOfstByGop(u8GOP, &u32BankOffSet);
3225
3226 HAL_GOP_Write16Reg(pGOPHalLocal, u32BankOffSet+REG_TLB_TAG_ADDR_L, u32size&GOP_REG_WORD_MASK, GOP_REG_WORD_MASK);
3227 HAL_GOP_Write16Reg(pGOPHalLocal, u32BankOffSet+REG_TLB_TAG_ADDR_H, u32size>>16, GOP_REG_WORD_MASK);
3228
3229 HAL_GOP_Write16Reg(pGOPHalLocal, u32BankOffSet+REG_TLB_BASE_ADDR_L, u64TLBAddr&GOP_REG_WORD_MASK, GOP_REG_WORD_MASK);
3230 HAL_GOP_Write16Reg(pGOPHalLocal, u32BankOffSet+REG_TLB_BASE_ADDR_H, u64TLBAddr>>16, GOP_REG_WORD_MASK);
3231
3232 return GOP_SUCCESS;
3233 }
3234
HAL_GOP_SetTLBSubAddr(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_U8 u8GOP,MS_PHY u64TLBAddr)3235 GOP_Result HAL_GOP_SetTLBSubAddr(GOP_CTX_HAL_LOCAL *pGOPHalLocal, MS_U8 u8GOP, MS_PHY u64TLBAddr)
3236 {
3237 MS_U32 u32BankOffSet=0xFFFF;
3238 _GetBnkOfstByGop(u8GOP, &u32BankOffSet);
3239
3240 HAL_GOP_Write16Reg(pGOPHalLocal, u32BankOffSet+REG_TLB_BASE_ADDR_RVIEW_L, u64TLBAddr&GOP_REG_WORD_MASK, GOP_REG_WORD_MASK);
3241 HAL_GOP_Write16Reg(pGOPHalLocal, u32BankOffSet+REG_TLB_BASE_ADDR_RVIEW_H, u64TLBAddr>>16, GOP_REG_WORD_MASK);
3242
3243 return GOP_SUCCESS;
3244 }
3245
HAL_GOP_Set_GWIN_INTERNAL_MIU(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_U8 u8GOP,MS_U8 miusel)3246 GOP_Result HAL_GOP_Set_GWIN_INTERNAL_MIU(GOP_CTX_HAL_LOCAL *pGOPHalLocal, MS_U8 u8GOP,MS_U8 miusel)
3247 {
3248 MS_U32 u32BankOffSet=0xFFFF;
3249 _GetBnkOfstByGop(u8GOP, &u32BankOffSet);
3250
3251 HAL_GOP_Write16Reg(pGOPHalLocal, u32BankOffSet+GOP_4G_MIU_SEL, miusel<<0, GOP_BIT0|GOP_BIT1 );//GWIN MIU Select
3252 HAL_GOP_Write16Reg(pGOPHalLocal, u32BankOffSet+GOP_4G_MIU_SEL, miusel<<2, GOP_BIT2|GOP_BIT3 );//GWIN_3D MIU Select
3253
3254 return GOP_SUCCESS;
3255 }
3256
HAL_GOP_SetGopGwinHVPixel(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_U8 u8GOP,MS_U8 u8win,MS_U16 hstart,MS_U16 hend,MS_U16 vstart,MS_U16 vend)3257 GOP_Result HAL_GOP_SetGopGwinHVPixel(GOP_CTX_HAL_LOCAL *pGOPHalLocal, MS_U8 u8GOP, MS_U8 u8win, MS_U16 hstart, MS_U16 hend, MS_U16 vstart, MS_U16 vend)
3258 {
3259 GOP_Result ret = GOP_SUCCESS;
3260 MS_U32 u32BankOffSet=0xFFFF;
3261 _GetBnkOfstByGop(u8GOP, &u32BankOffSet);
3262 HAL_GOP_Write16Reg(pGOPHalLocal, u32BankOffSet + GOP_4G_HSTR(_GetGwinOffsetInGOP(u8win)), hstart, GOP_REG_WORD_MASK);
3263 HAL_GOP_Write16Reg(pGOPHalLocal, u32BankOffSet + GOP_4G_HEND(_GetGwinOffsetInGOP(u8win)), hend, GOP_REG_WORD_MASK);
3264 HAL_GOP_Write16Reg(pGOPHalLocal, u32BankOffSet + GOP_4G_VSTR(_GetGwinOffsetInGOP(u8win)), vstart, GOP_REG_WORD_MASK);
3265 HAL_GOP_Write16Reg(pGOPHalLocal, u32BankOffSet + GOP_4G_VEND(_GetGwinOffsetInGOP(u8win)), vend, GOP_REG_WORD_MASK);
3266
3267
3268 return ret;
3269 }
3270
HAL_GOP_Set_MIU(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_U8 u8GOP,MS_U8 miusel)3271 GOP_Result HAL_GOP_Set_MIU(GOP_CTX_HAL_LOCAL *pGOPHalLocal, MS_U8 u8GOP,MS_U8 miusel)
3272 {
3273 MS_U32 u32BankOffSet=0xFFFF;
3274 MS_U16 mask_shift=0xFF;
3275
3276 _GetBnkOfstByGop(u8GOP, &u32BankOffSet);
3277
3278 if(pGOPHalLocal->pGopChipPro->bInternalMIUSelect[u8GOP] == TRUE)
3279 {
3280 HAL_GOP_Write16Reg(pGOPHalLocal, u32BankOffSet+GOP_4G_MIU_SEL, miusel<<0, GOP_BIT0|GOP_BIT1 );//GWIN MIU Select
3281 HAL_GOP_Write16Reg(pGOPHalLocal, u32BankOffSet+GOP_4G_MIU_SEL, miusel<<2, GOP_BIT2|GOP_BIT3 );//GWIN_3D MIU Select
3282 }
3283 else
3284 {
3285 switch(u8GOP)
3286 {
3287 case E_GOP0:
3288 mask_shift = GOP_MIU_CLIENT_GOP0;
3289 break;
3290 case E_GOP1:
3291 mask_shift = GOP_MIU_CLIENT_GOP1;
3292 break;
3293 case E_GOP2:
3294 mask_shift = GOP_MIU_CLIENT_GOP2;
3295 break;
3296 case E_GOP3:
3297 mask_shift = GOP_MIU_CLIENT_GOP3;
3298 break;
3299 case E_GOP4: // K6 : GOP0~3 and GOP5, NO GOP4. Mapping E_GOP4 to GOP 5 reg
3300 mask_shift = GOP_MIU_CLIENT_GOP5;
3301 break;
3302 default:
3303 mask_shift = 0xFF;
3304 MS_CRITICAL_MSG(printf("ERROR gop miu client\n"));
3305 break;
3306 }
3307 if(u8GOP==E_GOP4) // K6 : GOP0~3 and GOP5, NO GOP4. Mapping E_GOP4 to GOP 5 reg
3308 HAL_GOP_Write16Reg(pGOPHalLocal, GOP5_MIU_GROUP1, miusel<<mask_shift, 1<<mask_shift );
3309 else
3310 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_MIU_GROUP1, miusel<<mask_shift, 1<<mask_shift );
3311 #ifdef GOP_MIU_GROUP2
3312 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_MIU_GROUP2, (miusel>>1)<<mask_shift, 1<<mask_shift );
3313 #endif
3314 }
3315
3316 return GOP_SUCCESS;
3317 }
3318
Hal_SetCropWindow(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_U8 u8GOP,EN_GOP_CROP_CTL crop_mode)3319 GOP_Result Hal_SetCropWindow(
3320 GOP_CTX_HAL_LOCAL *pGOPHalLocal,
3321 MS_U8 u8GOP,
3322 EN_GOP_CROP_CTL crop_mode
3323 )
3324 {
3325 return GOP_SUCCESS;
3326 }
3327
HAL_GOP_GetIPInterlace(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_BOOL * bInterlace)3328 GOP_Result HAL_GOP_GetIPInterlace(GOP_CTX_HAL_LOCAL *pGOPHalLocal, MS_BOOL *bInterlace)
3329 {
3330 MS_U16 reg_val = 0;
3331
3332 // Note: Kastor XC use hand-shake mode, this register is differ to Kano's
3333 HAL_GOP_Read16Reg(pGOPHalLocal, GOP_SC_IP_MAIN_USR_INTERLACE, ®_val);
3334 if(reg_val & BIT(1))
3335 *bInterlace = TRUE;
3336 else
3337 *bInterlace = FALSE;
3338 return GOP_SUCCESS;
3339 }
3340
HAL_GOP_IsHDREnabled(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_BOOL * pbHDREnable)3341 GOP_Result HAL_GOP_IsHDREnabled(GOP_CTX_HAL_LOCAL *pGOPHalLocal, MS_BOOL *pbHDREnable)
3342 {
3343 MS_U16 u16regval=0,u16GopMux;
3344 MS_U8 u8mux=0,u8mux_sel=0;
3345
3346 for (u8mux=0; u8mux<MAX_GOP_MUX; u8mux++)
3347 {
3348 HAL_GOP_Read16Reg(pGOPHalLocal, GOP_MUX, &u16GopMux);
3349 u8mux_sel = (u16GopMux >> (u8mux*GOP_MUX_SHIFT))& GOP_REGMUX_MASK;
3350 if (u8mux_sel==GOP_MIXER_MUX)
3351 {
3352 switch(u8mux)
3353 {
3354 case E_GOP_MUX0:
3355 {
3356 HAL_GOP_Read16Reg(pGOPHalLocal, GOP_SC_VOP2BLENDING_L, &u16regval);
3357 if(u16regval&GOP_BIT3)
3358 {
3359 *pbHDREnable = TRUE;
3360 return GOP_SUCCESS;
3361 }
3362 break;
3363 }
3364 case E_GOP_MUX1:
3365 {
3366 HAL_GOP_Read16Reg(pGOPHalLocal, GOP_SC_VOP2BLENDING_L, &u16regval);
3367 if(u16regval&GOP_BIT11)
3368 {
3369 *pbHDREnable = TRUE;
3370 return GOP_SUCCESS;
3371 }
3372 break;
3373 }
3374 case E_GOP_MUX2:
3375 {
3376 HAL_GOP_Read16Reg(pGOPHalLocal, GOP_SC_VOP2BLENDING_H, &u16regval);
3377 if(u16regval&GOP_BIT3)
3378 {
3379 *pbHDREnable = TRUE;
3380 return GOP_SUCCESS;
3381 }
3382 break;
3383 }
3384 case E_GOP_MUX3:
3385 {
3386 HAL_GOP_Read16Reg(pGOPHalLocal, GOP_SC_VOP2BLENDING_H, &u16regval);
3387 if(u16regval&GOP_BIT11)
3388 {
3389 *pbHDREnable = TRUE;
3390 return GOP_SUCCESS;
3391 }
3392 break;
3393 }
3394 case E_GOP_MUX4:
3395 {
3396 HAL_GOP_Read16Reg(pGOPHalLocal, GOP_SC_VOP2BLENDING_EX, &u16regval);
3397 if(u16regval&GOP_BIT3)
3398 {
3399 *pbHDREnable = TRUE;
3400 return GOP_SUCCESS;
3401 }
3402 break;
3403 }
3404 default:
3405 break;
3406
3407 }
3408 }
3409 }
3410
3411 *pbHDREnable = FALSE;
3412
3413 return GOP_SUCCESS;
3414 }
3415
3416
HAL_GOP_AFBC_GetCore(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_U8 u8GOP,MS_U8 * u8Core)3417 GOP_Result HAL_GOP_AFBC_GetCore(GOP_CTX_HAL_LOCAL *pGOPHalLocal, MS_U8 u8GOP,MS_U8* u8Core)
3418 {
3419 if(u8GOP==0)
3420 {
3421 *u8Core=0;
3422 }
3423 else
3424 {
3425 *u8Core=1;
3426 }
3427 return GOP_SUCCESS;
3428 }
3429
3430 #ifdef GOP_CMDQ_ENABLE
HAL_GOP_CMDQ_WriteCommand(GOP_CTX_HAL_LOCAL * pGOPHalLocal,CAF_Struct * cmdq_struct,MS_U32 * number,MS_U32 u32addr,MS_U16 u16val,MS_U16 mask)3431 GOP_Result HAL_GOP_CMDQ_WriteCommand(GOP_CTX_HAL_LOCAL *pGOPHalLocal,CAF_Struct *cmdq_struct,MS_U32 *number,MS_U32 u32addr, MS_U16 u16val, MS_U16 mask)
3432 {
3433 MS_U16 u16xcSubbank=0;
3434 MS_U32 bank;
3435 MS_U32 direct_addr;
3436
3437 switch (u32addr & 0xFF00)
3438 {
3439 case GOP_REG_BASE:
3440 {
3441 bank = (u32addr & 0xFF0000) >> 8;
3442 #if 0 //for GOP4
3443 if(bank==0xE00)//GOP4: 0x121B00
3444 {
3445 bank=GOP_REG_GOP4_BK_OFFSET;
3446 }
3447 else if(bank==0xF00)//GWIN4: 0x121E00
3448 {
3449 bank=GOP_REG_GOP4_GW_OFFSET;
3450 }
3451 else if(bank==0x1000) //GOP4_ST
3452 {
3453 bank=GOP_REG_GOP4_ST_OFFSET;
3454 }
3455 #endif
3456 direct_addr = GOP_REG_DIRECT_BASE + bank + (u32addr & 0xFF);
3457
3458 cmdq_struct[(*number)].destionation_address = (direct_addr&0xFFFFFF);
3459 cmdq_struct[(*number)].destionation_value = u16val;
3460 cmdq_struct[(*number)].mask = ((~mask)&0xFFFF);
3461 cmdq_struct[(*number)].operation = 0x57;
3462 (*number)++;
3463 break;
3464 }
3465 case SC1_REG_BASE:
3466 u16xcSubbank = (u32addr & 0xFF0000)>>8 ;
3467 direct_addr = SC1_DIRREG_BASE + u16xcSubbank+ (u32addr & 0xFF);
3468
3469 cmdq_struct[(*number)].destionation_address = (direct_addr&0xFFFFFF);
3470 cmdq_struct[(*number)].destionation_value = u16val;
3471 cmdq_struct[(*number)].mask = ((~mask)&0xFFFF);
3472 cmdq_struct[(*number)].operation = 0x57;
3473 (*number)++;
3474 break;
3475 case GE_REG_BASE:
3476 case CKG_REG_BASE:
3477 case MIU_REG_BASE:
3478 {
3479 cmdq_struct[(*number)].destionation_address = (u32addr&0xFFFFF)+0x100000;
3480 cmdq_struct[(*number)].destionation_value = u16val;
3481 cmdq_struct[(*number)].mask = ((~mask)&0xFFFF);
3482 cmdq_struct[(*number)].operation = 0x57;
3483 (*number)++;
3484 break;
3485 }
3486 #ifdef GOP_MIU_GROUP2
3487 case (MIU2_REG_BASE & 0xFF00):
3488 {
3489 direct_addr = MIU2_REG_BASE + (u32addr & 0xFF); //Direct_Base + addr_offset
3490
3491 cmdq_struct[(*number)].destionation_address = (direct_addr&0xFFFFFF);
3492 cmdq_struct[(*number)].destionation_value = u16val;
3493 cmdq_struct[(*number)].mask = ((~mask)&0xFFFF);
3494 cmdq_struct[(*number)].operation = 0x57;
3495 (*number)++;
3496 break;
3497 }
3498 #endif
3499 default:
3500 {
3501 //Gop lib current do not support this HW ip base
3502 MS_ASSERT(0);
3503 break;
3504 }
3505
3506 }
3507 return GOP_SUCCESS;
3508 }
HAL_GOP_CMDQ_BegineDraw(GOP_CTX_HAL_LOCAL * pGOPHalLocal,CAF_Struct * target,MS_U32 * number,MS_U32 * u32GopIdx)3509 GOP_Result HAL_GOP_CMDQ_BegineDraw(GOP_CTX_HAL_LOCAL *pGOPHalLocal,CAF_Struct *target,MS_U32 *number, MS_U32 *u32GopIdx)
3510 {
3511 MS_U32 u32BankOffSet=0xFFFF;
3512 MS_U16 u16RegVal1 = 0;
3513 MS_BOOL bCheckValidGop = FALSE;
3514 MS_U8 u8CheckTimeCnt = 0;
3515 MS_U8 u8CurrentCmdGop = 0;
3516
3517 while (!bCheckValidGop && (u8CheckTimeCnt < (GOPG3_GOP_CMDQ_INT_3 - GOPG0_GOP_CMDQ_INT_0 + 2)))
3518 {
3519 if (u8CurrentCmdGop > (GOPG3_GOP_CMDQ_INT_3 - GOPG0_GOP_CMDQ_INT_0))
3520 {
3521 u8CurrentCmdGop = 0;
3522 }
3523 _GetBnkOfstByGop(u8CurrentCmdGop, &u32BankOffSet);
3524 HAL_GOP_Read16Reg(pGOPHalLocal, u32BankOffSet + GOP_4G_CTRL0, &u16RegVal1);
3525 if ((u16RegVal1 & GOP_BIT0) != 0) // gop not init, cmdq won't work
3526 {
3527 bCheckValidGop = FALSE;
3528 }
3529 else
3530 {
3531 bCheckValidGop = TRUE;
3532 break;
3533 }
3534
3535 // if current gop not init, use next gop instead, check order 0->2->1->3
3536 switch (u8CurrentCmdGop)
3537 {
3538 case 0:
3539 u8CurrentCmdGop = 2;
3540 break;
3541 case 1:
3542 u8CurrentCmdGop = 0;
3543 break;
3544 case 2:
3545 u8CurrentCmdGop = 3;
3546 break;
3547 case 3:
3548 u8CurrentCmdGop = 1;
3549 break;
3550 default:
3551 u8CurrentCmdGop = 0;
3552 break;
3553 }
3554 u8CheckTimeCnt++;
3555 }
3556 if (!bCheckValidGop)
3557 {
3558 printf("[%s] Error message no avalible gop can support current cmdq!!\n",__FUNCTION__);
3559 }
3560
3561 *u32GopIdx = u8CurrentCmdGop;
3562 MDrv_CMDQ_Gen_WaitTrigger_Bus_Command(&(target[(*number)]),GOPG0_GOP_CMDQ_INT_0 + u8CurrentCmdGop,FALSE);
3563 (*number)++;
3564 return GOP_SUCCESS;
3565 }
HAL_GOP_CMDQ_EndDraw(GOP_CTX_HAL_LOCAL * pGOPHalLocal,CAF_Struct * target,MS_U32 * number,MS_U32 u32GopIdx)3566 GOP_Result HAL_GOP_CMDQ_EndDraw(GOP_CTX_HAL_LOCAL *pGOPHalLocal,CAF_Struct *target,MS_U32 *number, MS_U32 u32GopIdx)
3567 {
3568 CH_Struct ch_fire;
3569 MS_U32 Receive_Return_Value = 0,u32BankOffSet = 0,u32FireBankOffSet = 0,timer1 = 0x0,timer2 = 0x0;
3570 MS_U16 u16ret = 0,u16ret1 = 0;
3571 int i = 0;
3572
3573
3574 _GetBnkOfstByGop(0, &u32BankOffSet);
3575 HAL_GOP_Read16Reg(pGOPHalLocal,u32BankOffSet+GOP_4G_BG_CLR(1),&u16ret);
3576 HAL_GOP_CMDQ_WriteCommand(pGOPHalLocal,target,number,u32BankOffSet+GOP_4G_BG_CLR(1),u16ret+1,0xFFFF);//current GOP force write dis
3577 #if 0 //for Debug
3578 for(i=0;i<(*number);i++)
3579 {
3580 printf("\33[0;36m [%d]op = %d, addr = %lx,value = %x,mask = %x\33[m \n",i,target[i].operation,target[i].destionation_address,target[i].destionation_value,target[i].mask);
3581 }
3582 #endif
3583 ch_fire.Command_Number = *number;
3584 ch_fire.Pointer_To_CAFArray = target;
3585 Receive_Return_Value = MDrv_CMDQ_Receive(&ch_fire);
3586 if(Receive_Return_Value == DRVCMDQ_CMDQ_FULL)
3587 {
3588 Receive_Return_Value = 0;
3589 MDrv_CMDQ_Printf_Crash_Command();
3590 }
3591
3592 _GetBnkOfstByGop(u32GopIdx, &u32FireBankOffSet);
3593 MsOS_DelayTask(1);
3594 HAL_GOP_Write16Reg(pGOPHalLocal, u32FireBankOffSet+GOP_4G_MULTI_ALPHA, GOP_BIT4, GOP_BIT4);//reset mask
3595 HAL_GOP_Write16Reg(pGOPHalLocal, u32FireBankOffSet+GOP_4G_MULTI_ALPHA, 0, GOP_BIT4); //reset nable detect
3596
3597 HAL_GOP_Read16Reg(pGOPHalLocal,u32BankOffSet+GOP_4G_BG_CLR(1),&u16ret1);
3598 timer1 = MsOS_GetSystemTime();
3599 timer2 = MsOS_GetSystemTime();
3600 while( u16ret1 != (u16ret+1) && ((timer2 - timer1)<100))
3601 {
3602 HAL_GOP_Read16Reg(pGOPHalLocal,u32BankOffSet+GOP_4G_BG_CLR(1),&u16ret1);
3603 MsOS_DelayTask(1);
3604 timer2 = MsOS_GetSystemTime();
3605 }
3606 if(u16ret1 != (u16ret+1))
3607 {
3608 printf("\33[0;36m %s:%d timeout = %ld org = %d target = %d\33[m \n",__FUNCTION__,__LINE__,(timer2 - timer1),u16ret1,(u16ret+1));
3609 MDrv_CMDQ_Printf_Crash_Command();
3610 }
3611 return GOP_SUCCESS;
3612 }
3613
HAL_GOP_CMDQ_SetGOPACK(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_U8 gop)3614 GOP_Result HAL_GOP_CMDQ_SetGOPACK(GOP_CTX_HAL_LOCAL *pGOPHalLocal,MS_U8 gop)
3615 {
3616 CAF_Struct fire_struct[24];
3617 MS_U32 u32BankOffSet;
3618 MS_U32 number = 0;
3619 MS_U16 u16RegVal1 = 0,u16RegVal2 = 0,u16RegVal3 = 0,u16MiuClient = 0;
3620 MS_U16 u16RegMiu=0, u16RegCoreEna=0;
3621 MS_U32 fireGOP=0;
3622
3623 _GetBnkOfstByGop(gop, &u32BankOffSet);
3624
3625 if(gop == E_GOP4) // K6 : GOP0~3 and GOP5, NO GOP4. Mapping E_GOP4 to GOP 5 reg
3626 HAL_GOP_Read16Reg(pGOPHalLocal, GOP5_MIU_GROUP1, &u16RegVal1);
3627 else
3628 HAL_GOP_Read16Reg(pGOPHalLocal, GOP_MIU_GROUP1, &u16RegVal1);
3629 #ifdef GOP_MIU_GROUP2
3630 HAL_GOP_Read16Reg(pGOPHalLocal, GOP_MIU_GROUP2, &u16RegVal3);
3631 #endif
3632 HAL_GOP_Read16Reg(pGOPHalLocal, u32BankOffSet+GOP_4G_BANK_FWR,&u16RegVal2);
3633 HAL_GOP_CMDQ_BegineDraw(pGOPHalLocal,fire_struct,&number,&fireGOP);
3634
3635 switch(gop)
3636 {
3637 case E_GOP0:
3638 {
3639 u16MiuClient = GOP_MIU_CLIENT_GOP0;
3640 break;
3641 }
3642 case E_GOP1:
3643 {
3644 u16MiuClient = GOP_MIU_CLIENT_GOP1;
3645 break;
3646 }
3647 case E_GOP2:
3648 {
3649 u16MiuClient = GOP_MIU_CLIENT_GOP2;
3650 break;
3651 }
3652 case E_GOP3:
3653 {
3654 u16MiuClient = GOP_MIU_CLIENT_GOP3;
3655 break;
3656 }
3657 case E_GOP4: // K6 : GOP0~3 and GOP5, NO GOP4. Mapping E_GOP4 to GOP 5 reg
3658 {
3659 u16MiuClient = GOP_MIU_CLIENT_GOP5;
3660 break;
3661 }
3662 default:
3663 {
3664 MS_ASSERT(0);
3665 break;
3666 }
3667 }
3668 if(bMIUSelect[gop] == TRUE)
3669 {
3670 if(u16MIUSelect[gop] == 0)
3671 {
3672 u16RegVal1 &= ~(1<<u16MiuClient);
3673 u16RegVal3 &= ~(1<<u16MiuClient);
3674 }
3675 else if(u16MIUSelect[gop] == 1)
3676 {
3677 u16RegVal1 |= (1<<u16MiuClient);
3678 u16RegVal3 &= ~(1<<u16MiuClient);
3679 }
3680 else if(u16MIUSelect[gop] == 2)
3681 {
3682 u16RegVal1 &= ~(1<<u16MiuClient);
3683 u16RegVal3 |= (1<<u16MiuClient);
3684 }
3685 else if(u16MIUSelect[gop] == 3)
3686 {
3687 u16RegVal1 |= (1<<u16MiuClient);
3688 u16RegVal3 |= (1<<u16MiuClient);
3689 }
3690 bMIUSelect[gop] = FALSE;
3691 }
3692
3693 if(bAFBCMIUSelect[gop] == TRUE)
3694 {
3695 bAFBCMIUSelect[gop] = FALSE;
3696 }
3697 HAL_GOP_CMDQ_WriteCommand(pGOPHalLocal,fire_struct,&number,u32BankOffSet+GOP_4G_BANK_FWR,(u16RegVal2|(GOP_BIT0)) ,0xFFFF);//current GOP force write en
3698 HAL_GOP_CMDQ_WriteCommand(pGOPHalLocal,fire_struct,&number,u32BankOffSet+GOP_4G_BANK_FWR,(u16RegVal2&(~GOP_BIT0)) ,0xFFFF);//current GOP force write en
3699 if(gop == E_GOP4) // K6 : GOP0~3 and GOP5, NO GOP4. Mapping E_GOP4 to GOP 5 reg
3700 HAL_GOP_CMDQ_WriteCommand(pGOPHalLocal,fire_struct,&number,GOP5_MIU_GROUP1,u16RegVal1,0xFFFF);
3701 else
3702 HAL_GOP_CMDQ_WriteCommand(pGOPHalLocal,fire_struct,&number,GOP_MIU_GROUP1,u16RegVal1,0xFFFF);
3703
3704 MS_U8 u8Core=0;
3705 HAL_GOP_AFBC_GetCore(pGOPHalLocal, gop, &u8Core);
3706 if(g_GopChipPro.bAFBCCore_Merge_GOP_Trig[gop] ==FALSE)
3707 {
3708 if(bAFBCMIUSelect[gop] == TRUE)
3709 {
3710 HAL_GOP_CMDQ_WriteCommand(pGOPHalLocal,fire_struct,&number,REG_AFBC_MIU(u8Core),u16AFBCMIUSelect[gop]<<4, 0xFFFF);
3711 bAFBCMIUSelect[gop] = FALSE;
3712 }
3713 HAL_GOP_CMDQ_WriteCommand(pGOPHalLocal,fire_struct,&number,REG_AFBC_MIU(u8Core),u16AFBCMIUSelect[gop]<<4, 0xFFFF);
3714 HAL_GOP_CMDQ_WriteCommand(pGOPHalLocal,fire_struct,&number,REG_AFBC_TRIGGER(u8Core),GOP_BIT1, 0xFFFF);
3715 HAL_GOP_CMDQ_WriteCommand(pGOPHalLocal,fire_struct,&number,REG_AFBC_TRIGGER(u8Core),GOP_BIT0, 0xFFFF);
3716 }
3717 #ifdef GOP_MIU_GROUP2
3718 HAL_GOP_CMDQ_WriteCommand(pGOPHalLocal,fire_struct,&number,GOP_MIU_GROUP2,u16RegVal3,0xFFFF);
3719 #endif
3720
3721 HAL_GOP_CMDQ_EndDraw(pGOPHalLocal,fire_struct,&number,fireGOP);
3722 return GOP_SUCCESS;
3723 }
3724
HAL_GOP_CMDQ_SetGOPACKMask(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_U16 u16GopMask)3725 GOP_Result HAL_GOP_CMDQ_SetGOPACKMask(GOP_CTX_HAL_LOCAL *pGOPHalLocal,MS_U16 u16GopMask)
3726 {
3727 CAF_Struct fire_struct[24];
3728 MS_U32 u32BankOffSet=0;
3729 MS_U32 number = 0;
3730 MS_U8 gop=0;
3731 MS_U16 u16RegVal1=0,u16RegVal2=0,u16RegVal3 = 0,u16MiuClient = 0;
3732 MS_U16 u16RegMiu=0,u16RegCoreEna=0;
3733 MS_U8 u8Core=0;
3734 MS_U32 fireGOP=0;
3735 MS_BOOL bCoreTrig[AFBC_CORE_COUNT];
3736 MS_BOOL bCoreMiu[AFBC_CORE_COUNT];
3737 MS_U8 i=0;
3738
3739 for(i=0;i<AFBC_CORE_COUNT;i++)
3740 {
3741 bCoreTrig[i]=FALSE;
3742 }
3743
3744 if(gop == E_GOP4) // K6 : GOP0~3 and GOP5, NO GOP4. Mapping E_GOP4 to GOP 5 reg
3745 HAL_GOP_Read16Reg(pGOPHalLocal, GOP5_MIU_GROUP1, &u16RegVal1);
3746 else
3747 HAL_GOP_Read16Reg(pGOPHalLocal, GOP_MIU_GROUP1, &u16RegVal1);
3748 #ifdef GOP_MIU_GROUP2
3749 HAL_GOP_Read16Reg(pGOPHalLocal, GOP_MIU_GROUP2, &u16RegVal3);
3750 #endif
3751 HAL_GOP_CMDQ_BegineDraw(pGOPHalLocal,fire_struct,&number,&fireGOP);
3752
3753 for(gop = 0; gop<MAX_GOP_SUPPORT; gop++)
3754 {
3755 switch(gop)
3756 {
3757 case E_GOP0:
3758 {
3759 u16MiuClient = GOP_MIU_CLIENT_GOP0;
3760 HAL_GOP_AFBC_GetCore(pGOPHalLocal, (MS_U8)E_GOP0, &u8Core);
3761 bCoreTrig[u8Core]=TRUE;
3762 break;
3763 }
3764 case E_GOP1:
3765 {
3766 u16MiuClient = GOP_MIU_CLIENT_GOP1;
3767 HAL_GOP_AFBC_GetCore(pGOPHalLocal, (MS_U8)E_GOP1, &u8Core);
3768 bCoreTrig[u8Core]=TRUE;
3769 break;
3770 }
3771 case E_GOP2:
3772 {
3773 u16MiuClient = GOP_MIU_CLIENT_GOP2;
3774 HAL_GOP_AFBC_GetCore(pGOPHalLocal, (MS_U8)E_GOP2, &u8Core);
3775 bCoreTrig[u8Core]=TRUE;
3776 break;
3777 }
3778 case E_GOP3:
3779 {
3780 u16MiuClient = GOP_MIU_CLIENT_GOP3;
3781 HAL_GOP_AFBC_GetCore(pGOPHalLocal, (MS_U8)E_GOP3, &u8Core);
3782 bCoreTrig[u8Core]=TRUE;
3783 break;
3784 }
3785 case E_GOP4: // K6 : GOP0~3 and GOP5, NO GOP4. Mapping E_GOP4 to GOP 5 reg
3786 {
3787 u16MiuClient = GOP_MIU_CLIENT_GOP5;
3788 HAL_GOP_AFBC_GetCore(pGOPHalLocal, (MS_U8)E_GOP4, &u8Core);
3789 bCoreTrig[u8Core]=TRUE;
3790 break;
3791 }
3792 default:
3793 {
3794 continue;
3795 }
3796 }
3797 if( ( u16GopMask & (1<<gop) ) )
3798 {
3799 _GetBnkOfstByGop(gop, &u32BankOffSet);
3800 if(bMIUSelect[gop] == TRUE)
3801 {
3802 if(u16MIUSelect[gop] == 0)
3803 {
3804 u16RegVal1 &= ~(1<<u16MiuClient);
3805 u16RegVal3 &= ~(1<<u16MiuClient);
3806 }
3807 else if(u16MIUSelect[gop] == 1)
3808 {
3809 u16RegVal1 |= (1<<u16MiuClient);
3810 u16RegVal3 &= ~(1<<u16MiuClient);
3811 }
3812 else if(u16MIUSelect[gop] == 2)
3813 {
3814 u16RegVal1 &= ~(1<<u16MiuClient);
3815 u16RegVal3 |= (1<<u16MiuClient);
3816 }
3817 else if(u16MIUSelect[gop] == 3)
3818 {
3819 u16RegVal1 |= (1<<u16MiuClient);
3820 u16RegVal3 |= (1<<u16MiuClient);
3821 }
3822 bMIUSelect[gop] = FALSE;
3823 }
3824 HAL_GOP_Read16Reg(pGOPHalLocal, u32BankOffSet+GOP_4G_BANK_FWR,&u16RegVal2);
3825 HAL_GOP_CMDQ_WriteCommand(pGOPHalLocal,fire_struct,&number,u32BankOffSet+GOP_4G_BANK_FWR,(u16RegVal2|(GOP_BIT0)) ,0xFFFF);//current GOP force write en
3826 HAL_GOP_CMDQ_WriteCommand(pGOPHalLocal,fire_struct,&number,u32BankOffSet+GOP_4G_BANK_FWR,(u16RegVal2&(~GOP_BIT0)) ,0xFFFF);//current GOP force write en
3827 }
3828
3829 if(bAFBCMIUSelect[gop] == TRUE)
3830 {
3831 HAL_GOP_AFBC_GetCore(pGOPHalLocal, gop, &u8Core);
3832 bCoreMiu[gop]=TRUE;
3833 bAFBCMIUSelect[gop] = FALSE;
3834 }
3835 }
3836
3837 for(i=0;i<AFBC_CORE_COUNT;i++)
3838 {
3839 if(g_GopChipPro.bAFBCCore_Merge_GOP_Trig[i] == FALSE)
3840 {
3841 if(bCoreTrig[i]==TRUE)
3842 {
3843 if((g_GopChipPro.bAFBCMIUSelDoubleBuffer[i] == FALSE)&&(bCoreMiu[i]==TRUE))
3844 {
3845 HAL_GOP_CMDQ_WriteCommand(pGOPHalLocal,fire_struct,&number,REG_AFBC_MIU(i),u16AFBCMIUSelect[gop]<<4, 0xFFFF);
3846 }
3847 HAL_GOP_CMDQ_WriteCommand(pGOPHalLocal,fire_struct,&number,REG_AFBC_TRIGGER(i),GOP_BIT1, 0xFFFF);
3848 HAL_GOP_CMDQ_WriteCommand(pGOPHalLocal,fire_struct,&number,REG_AFBC_TRIGGER(i),GOP_BIT0, 0xFFFF);
3849 }
3850 }
3851 }
3852
3853 if(gop == E_GOP4) // K6 : GOP0~3 and GOP5, NO GOP4. Mapping E_GOP4 to GOP 5 reg
3854 HAL_GOP_CMDQ_WriteCommand(pGOPHalLocal,fire_struct,&number,GOP5_MIU_GROUP1,u16RegVal1,0xFFFF);
3855 else
3856 HAL_GOP_CMDQ_WriteCommand(pGOPHalLocal,fire_struct,&number,GOP_MIU_GROUP1,u16RegVal1,0xFFFF);
3857 #ifdef GOP_MIU_GROUP2
3858 HAL_GOP_CMDQ_WriteCommand(pGOPHalLocal,fire_struct,&number,GOP_MIU_GROUP2,u16RegVal3,0xFFFF);
3859 #endif
3860 HAL_GOP_CMDQ_EndDraw(pGOPHalLocal,fire_struct,&number,fireGOP);
3861 return GOP_SUCCESS;
3862 }
3863 #endif
3864