1 //<MStar Software> 2 //****************************************************************************** 3 // MStar Software 4 // Copyright (c) 2010 - 2012 MStar Semiconductor, Inc. All rights reserved. 5 // All software, firmware and related documentation herein ("MStar Software") are 6 // intellectual property of MStar Semiconductor, Inc. ("MStar") and protected by 7 // law, including, but not limited to, copyright law and international treaties. 8 // Any use, modification, reproduction, retransmission, or republication of all 9 // or part of MStar Software is expressly prohibited, unless prior written 10 // permission has been granted by MStar. 11 // 12 // By accessing, browsing and/or using MStar Software, you acknowledge that you 13 // have read, understood, and agree, to be bound by below terms ("Terms") and to 14 // comply with all applicable laws and regulations: 15 // 16 // 1. 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MStar hereby reserves the 91 // rights to any and all damages, losses, costs and expenses resulting therefrom. 92 // 93 //////////////////////////////////////////////////////////////////////////////// 94 95 #ifndef _REG_GOP_H_ 96 #define _REG_GOP_H_ 97 98 //------------------------------------------------------------------------------------------------- 99 // Hardware Capability 100 //------------------------------------------------------------------------------------------------- 101 102 103 //------------------------------------------------------------------------------------------------- 104 // Macro and Define 105 //------------------------------------------------------------------------------------------------- 106 //---------------------------------------------------------------------------- 107 // HW IP Reg Base Adr 108 //---------------------------------------------------------------------------- 109 #define GOP_REG_BASE 0x1F00UL 110 #define GE_REG_BASE 0x2800UL 111 #define SC1_REG_BASE 0x2F00UL 112 #define CKG_REG_BASE 0x0B00UL 113 #define MIU0_REG_BASE 0x0600UL 114 #define MIU_REG_BASE 0x1200UL 115 #define MIU2_REG_BASE 0x162000 116 #define MVOP_REG_BASE 0x1400UL 117 #define VE_REG_BASE 0x3B00UL 118 #define SC1_DIRREG_BASE 0x130000UL 119 120 //---------------------------------------------------------------------------- 121 // Scaler Reg 122 //---------------------------------------------------------------------------- 123 #define XC_REG(bk, reg) (SC1_REG_BASE+((MS_U32)(bk)<<16) + (reg) * 2) 124 125 #define REG_SC_BK00_00_L XC_REG(0x00, 0x00) 126 #define REG_SC_BK00_05_L XC_REG(0x00, 0x05) 127 #define REG_SC_BK00_06_L XC_REG(0x00, 0x06) 128 #define REG_SC_BK01_02_L XC_REG(0x01, 0x02) 129 #define REG_SC_BK01_05_L XC_REG(0x01, 0x05) 130 #define REG_SC_BK01_1E_L XC_REG(0x01, 0x1E) 131 #define REG_SC_BK01_21_L XC_REG(0x01, 0x21) 132 #define REG_SC_BK02_5F_L XC_REG(0x02, 0x5F) 133 #define REG_SC_BK0F_2B_L XC_REG(0x0F, 0x2B) 134 #define REG_SC_BK10_23_L XC_REG(0x10, 0x23) 135 #define REG_SC_BK10_5B_L XC_REG(0x10, 0x5B) 136 #define REG_SC_BK12_03_L XC_REG(0x12, 0x03) 137 #define REG_SC_BK2F_27_L XC_REG(0x2F, 0x27) 138 #define REG_SC_BK2F_37_L XC_REG(0x2F, 0x37) 139 #define REG_SC_BK2F_38_L XC_REG(0x2F, 0x38) 140 #define REG_SC_BK2F_39_L XC_REG(0x2F, 0x39) 141 #define REG_SC_BK2F_3A_L XC_REG(0x2F, 0x3A) 142 #define REG_SC_BK2F_3B_L XC_REG(0x2F, 0x3B) 143 #define REG_SC_BK2F_3C_L XC_REG(0x2F, 0x3C) 144 #define REG_SC_BK37_22_L XC_REG(0x37, 0x22) 145 #define REG_SC_BK37_24_L XC_REG(0x37, 0x24) 146 #define REG_SC_BK37_28_L XC_REG(0x37, 0x28) 147 #define REG_SC_BK3D_0D_L XC_REG(0x3D, 0x0D) 148 #define REG_SC_BK40_22_L XC_REG(0x40, 0x22) 149 #define REG_SC_BK40_23_L XC_REG(0x40, 0x23) 150 #define REG_SC_BK40_24_L XC_REG(0x40, 0x24) 151 #define REG_SC_BK40_25_L XC_REG(0x40, 0x25) 152 #define REG_SC_BK7F_10_L XC_REG(0x7F, 0x10) 153 #define REG_SC_BK7F_11_L XC_REG(0x7F, 0x11) 154 155 #define REG_SC1_BK00_05_L XC_REG(0x80+0x00, 0x05) 156 #define REG_SC1_BK00_06_L XC_REG(0x80+0x00, 0x06) 157 #define REG_SC1_BK10_23_L XC_REG(0x80+0x10, 0x23) 158 159 #define GOP_SC_BANKSEL REG_SC_BK00_00_L 160 #define GOP_SC_CHANNELSYNC REG_SC_BK00_05_L 161 #define GOP_SC_GOPEN REG_SC_BK00_06_L 162 #define GOP_SC_IP_SYNC REG_SC_BK01_02_L 163 #define GOP_SC_IP_MAIN_HSTART REG_SC_BK01_05_L 164 #define GOP_SC_IP_MAIN_INTERLACE REG_SC_BK01_1E_L 165 #define GOP_SC_IP_MAIN_USR_INTERLACE REG_SC_BK01_21_L 166 #define GOP_SC_IP2GOP_SRCSEL REG_SC_BK02_5F_L 167 #define GOP_SC_OSD_CHECK_ALPHA REG_SC_BK0F_2B_L 168 #define GOP_SC_VOPNBL REG_SC_BK10_23_L 169 #define GOP_SC_ALPHAMODE REG_SC_BK10_5B_L 170 #define GOP_SC_GOPENMODE1 REG_SC_BK10_5B_L 171 #define GOP_SC_MIRRORCFG REG_SC_BK12_03_L 172 #define GOP_SC_BLEND0_GOP_SWITCH REG_SC_BK2F_27_L 173 #define GOP_SC_VOP2BLENDING_L REG_SC_BK2F_37_L 174 #define GOP_SC_VOP2BLENDING_H REG_SC_BK2F_38_L 175 #define GOP_SC_VOP2BLENDING_EX REG_SC_BK2F_39_L 176 #define GOP_SC_VOPVTK REG_SC_BK2F_3A_L 177 #define GOP_SC_VOPVTK_L REG_SC_BK2F_3B_L 178 #define GOP_SC_VOPVTK_H REG_SC_BK2F_3C_L 179 #define GOP_SC_OCMIXER REG_SC_BK37_22_L 180 #define GOP_SC_OCMISC REG_SC_BK37_24_L 181 #define GOP_SC_OCALPHA REG_SC_BK37_28_L 182 #define GOP_SC_GOPSC_SRAM_CTRL REG_SC_BK3D_0D_L 183 #define GOP_SC_FRC_LAYER1_L_EN REG_SC_BK40_22_L 184 #define GOP_SC_FRC_LAYER1_R_EN REG_SC_BK40_23_L 185 #define GOP_SC_FRC_LAYER2_L_EN REG_SC_BK40_24_L 186 #define GOP_SC_FRC_LAYER2_R_EN REG_SC_BK40_25_L 187 #define GOP_SC_MIU_SEL REG_SC_BK7F_10_L 188 #define GOP_SC_MIU_IP_SEL REG_SC_BK7F_11_L 189 190 #define GOP_SC1_CHANNELSYNC REG_SC1_BK00_05_L 191 #define GOP_SC1_GOPEN REG_SC1_BK00_06_L 192 #define GOP_SC1_VOPNBL REG_SC1_BK10_23_L 193 //---------------------------------------------------------------------------- 194 // MVOP Reg 195 //---------------------------------------------------------------------------- 196 #define GOP_MVOP_MIRRORCFG (MVOP_REG_BASE+0x76) 197 198 //---------------------------------------------------------------------------- 199 // VE Reg 200 //---------------------------------------------------------------------------- 201 #define VE_REG(reg) (VE_REG_BASE + (reg) * 2) 202 203 #define GOP_VE_TVS_CTRL VE_REG(0x00) 204 #define GOP_VE_TVS_OSD_EN VE_REG(0x55) 205 #define GOP_VE_TVS_OSD_EN_ALPHA_INV VE_REG(0x5f) 206 #define GOP_VE_TVS_OSD1_EN VE_REG(0x60) 207 #define GOP_VE_TVE_SWRST VE_REG(0x07) 208 209 //---------------------------------------------------------------------------- 210 // GE Reg 211 //---------------------------------------------------------------------------- 212 #define GOP_GE_FMT_BLT (GE_REG_BASE+(0x01*2)) 213 #define GOP_GE_EN_CMDQ BIT(0) 214 #define GOP_GE_EN_VCMDQ BIT(1) 215 216 #define GOP_GE_VQ_FIFO_STATUS_L (GE_REG_BASE+(0x04*2)) 217 #define GOP_GE_VQ_FIFO_STATUS_H (GE_REG_BASE+(0x05*2)) 218 219 #define GOP_GE_STATUS (GE_REG_BASE+(0x07*2)) 220 #define GOP_GE_BUSY BIT(0) 221 #define GOP_GE_CMDQ1_STATUS BMASK(7:3) 222 #define GOP_GE_CMDQ2_STATUS BMASK(15:11) 223 224 #define GOP_GE_TAG (GE_REG_BASE+(0x2C*2)) 225 226 #define GOP_GE_DBBASE0 (GE_REG_BASE+(0x26*2)) 227 #define GOP_GE_DBBASE1 (GE_REG_BASE+(0x27*2)) 228 #define GOP_GE_DBPIT (GE_REG_BASE+(0x33*2)) 229 #define GOP_GE_FBFMT (GE_REG_BASE+(0x34*2)) 230 #define GOP_GE_SRCW (GE_REG_BASE+(0x6e*2)) 231 #define GOP_GE_SRCH (GE_REG_BASE+(0x6f*2)) 232 233 234 //---------------------------------------------------------------------------- 235 // ChipTop Reg 236 //---------------------------------------------------------------------------- 237 /* GOP0 and GOP1 CLK */ 238 #define GOP_GOPCLK (CKG_REG_BASE+(0x40<<1)) 239 #define CKG_GOPG0_DISABLE_CLK ~(GOP_BIT0) 240 #define CKG_GOPG0_ODCLK (0 << 2) 241 #define CKG_GOPG0_OD1CLK (2 << 2) 242 #define CKG_GOPG0_DIP (3 << 2) 243 #define CKG_GOPG0_IDCLK2 (6 << 2) 244 #define CKG_GOPG0_IDCLK1 (7 << 2) 245 #define CKG_GOPG0_DISABLE_CLK_MASK (GOP_BIT0) 246 #define CKG_GOPG0_MASK (GOP_BIT4 | GOP_BIT3 | GOP_BIT2) 247 248 #define CKG_GOPG1_DISABLE_CLK ~(GOP_BIT8) 249 #define CKG_GOPG1_ODCLK (0 << 10) 250 #define CKG_GOPG1_OD1CLK (2 << 10) 251 #define CKG_GOPG1_DIP (3 << 10) 252 #define CKG_GOPG1_IDCLK2 (6 << 10) 253 #define CKG_GOPG1_IDCLK1 (7 << 10) 254 #define CKG_GOPG1_DISABLE_CLK_MASK (GOP_BIT8) 255 #define CKG_GOPG1_MASK (GOP_BIT12 | GOP_BIT11 | GOP_BIT10) 256 257 /* GOP Mixer CLK */ 258 #define CKG_GOPMIXER_CLK (CKG_REG_BASE+(0x41<<1)) 259 #define CKG_GOPMIXER_ODCLK (4<<2) 260 #define CKG_GOPMIXER_VECLK (6<<2) 261 #define CKG_GOPMIXER_MASK (GOP_BIT4|GOP_BIT3 | GOP_BIT2) 262 263 /* GOPD CLK */ 264 #define GOP_GOPDCLK (CKG_REG_BASE+(0x41<<1)) 265 #define CKG_GOPD_CLK_IDCLK2 (0 << 10) 266 #define CKG_GOPD_CLK_ODCLK (1 << 10) 267 #define CKG_GOPD_CLK_DC0CLK (2 << 10) 268 #define CKG_GOPD_CLK_SUBDC0CLK (3 << 10) 269 #define CKG_GOPD_CLK_MIXERCLK_VE (4 << 10) 270 #define CKG_GOPD_MASK (GOP_BIT12 | GOP_BIT11 | GOP_BIT10) 271 272 /* GOP2 CLK */ 273 #define GOP_GOP2CLK (CKG_REG_BASE+(0x42<<1)) 274 #define CKG_GOPG2_DISABLE_CLK ~(GOP_BIT0) 275 #define CKG_GOPG2_ODCLK (0 << 2) 276 #define CKG_GOPG2_OD1CLK (2 << 2) 277 #define CKG_GOPG2_IDCLK1 (7 << 2) 278 #define CKG_GOPG2_DIP (3 << 2) 279 #define CKG_GOPG2_DISABLE_CLK_MASK (GOP_BIT0) 280 #define CKG_GOPG2_MASK (GOP_BIT4 | GOP_BIT3 | GOP_BIT2) 281 282 /* GOP3 CLK*/ 283 #define GOP_GOP3CLK (CKG_REG_BASE+(0x42<<1)) 284 #define CKG_GOPG3_ODCLK (0 << 10) 285 #define CKG_GOPG3_OD1CLK (2 << 10) 286 #define CKG_GOPG3_IDCLK1 (7 << 10) 287 #define CKG_GOPG3_DIP (3 << 10) 288 #define CKG_GOPG3_DISABLE_CLK_MASK (GOP_BIT8) 289 #define CKG_GOPG3_MASK (GOP_BIT12 | GOP_BIT11 | GOP_BIT10) 290 #define CKG_GOPD_DISABLE_CLK ~(GOP_BIT8) 291 292 /* GOP4 CLK*/ 293 #define GOP_GOP4CLK (CKG_REG_BASE+(0x44<<1)) 294 #define CKG_GOPG4_DISABLE_CLK_MASK (GOP_BIT0) 295 #define CKG_GOPG4_DISABLE_CLK_MASK (GOP_BIT0) 296 #define CKG_GOPG4_MASK (GOP_BIT4 | GOP_BIT3 | GOP_BIT2) 297 298 // K6 : GOP0~3 and GOP5, NO GOP4. Mapping E_GOP4 to GOP 5 reg 299 /* GOP5 CLK*/ 300 #define GOP_GOP5CLK (CKG_REG_BASE+(0x44<<1)) 301 #define CKG_GOPG5_DISABLE_CLK_MASK (GOP_BIT8) 302 #define CKG_GOPG5_ODCLK (0 << 10) 303 #define CKG_GOPG5_OD1CLK (2 << 10) 304 #define CKG_GOPG5_DIP (3 << 10) 305 #define CKG_GOPG5_IDCLK1 (7 << 10) 306 #define CKG_GOPG5_MASK (GOP_BIT12 | GOP_BIT11 | GOP_BIT10) 307 308 /* SRAM CLK */ 309 #define GOP_SRAMCLK (CKG_REG_BASE+(0x43<<1)) 310 #define CKG_SRAM0_DISABLE_CLK (GOP_BIT0) 311 #define CKG_SRAM1_DISABLE_CLK (GOP_BIT2) 312 #define CKG_SRAM0_MASK (GOP_BIT0|GOP_BIT1) 313 #define CKG_SRAM1_MASK (GOP_BIT2|GOP_BIT3) 314 315 /* LINE BUFFER SRAM CLK */ 316 #define GOP_LB_SRAMCLK (CKG_REG_BASE+(0x45<<1)) 317 #define CKG_LB_SRAM1_DISABLE_CLK (GOP_BIT0) /*GOP1*/ 318 #define CKG_LB_SRAM2_DISABLE_CLK (GOP_BIT4) /*GOP2*/ 319 #define CKG_LB_SRAM1_MASK (GOP_BIT2|GOP_BIT3) 320 #define CKG_LB_SRAM2_MASK (GOP_BIT6|GOP_BIT7) 321 322 /*AFBC CLK*/ 323 #define GOP_AFBCCLK (CKG_REG_BASE+(0x5F<<1)) 324 #define CKG_AFBCCLK_DISABLE_CLK (GOP_BIT0) 325 #define CKG_AFBCCLK_216 (0 << 2) 326 #define CKG_AFBCCLK_432 (1 << 2) 327 #define CKG_AFBCCLK_DISABLE_CLK_MASK (GOP_BIT0|GOP_BIT1|GOP_BIT2|GOP_BIT3) 328 329 //---------------------------------------------------------------------------- 330 // MIU Reg 331 //---------------------------------------------------------------------------- 332 #define GOP_CLIENT_REG 0x7D 333 #define GOP_MIU_GROUP (MIU0_REG_BASE+(GOP_CLIENT_REG*2)) 334 #define GOP_MIU_GROUP1 (MIU_REG_BASE+(GOP_CLIENT_REG*2)) 335 336 /*Define each gop miu clint bit*/ 337 #define GOP_MIU_CLIENT_DWIN 0xFF 338 #define GOP_MIU_CLIENT_GOP0 0x0 339 #define GOP_MIU_CLIENT_GOP1 0x1 340 #define GOP_MIU_CLIENT_GOP2 0x2 341 #define GOP_MIU_CLIENT_GOP3 0x3 342 #define GOP_MIU_CLIENT_GOP4 0x4 343 344 #define GOP5_CLIENT_REG 0x7C 345 #define GOP5_MIU_GROUP (MIU0_REG_BASE+(GOP5_CLIENT_REG*2)) 346 #define GOP5_MIU_GROUP1 (MIU_REG_BASE+(GOP5_CLIENT_REG*2)) 347 #define GOP_MIU_CLIENT_GOP5 0x2 348 349 //---------------------------------------------------------------------------- 350 // GOP Reg 351 //---------------------------------------------------------------------------- 352 #define GOP_REG(bk, reg) (GOP_REG_BASE+((MS_U32)(bk)<<16) + (reg) * 2) 353 #define __GOP_REG(reg) (GOP_REG_BASE+(reg) * 2) 354 #define GOP_REG_DIRECT_BASE (0x120200) 355 #define GOP_REG_GOP4_BK_OFFSET 0x1900 356 #define GOP_REG_GOP4_GW_OFFSET 0x1C00 357 #define GOP_REG_GOP4_ST_OFFSET 0x1D00 358 359 #define GOP_REG_VAL(x) (1<<x) 360 361 //MUX Setting 362 #define GOP_MUX_SHIFT 0x3 363 #define GOP_REGMUX_MASK BMASK((GOP_MUX_SHIFT-1):0) 364 #define GOP_MUX0_MASK (GOP_REGMUX_MASK<<(GOP_MUX_SHIFT*0)) 365 #define GOP_MUX1_MASK (GOP_REGMUX_MASK<<(GOP_MUX_SHIFT*1)) 366 #define GOP_MUX2_MASK (GOP_REGMUX_MASK<<(GOP_MUX_SHIFT*2)) 367 #define GOP_MUX3_MASK (GOP_REGMUX_MASK<<(GOP_MUX_SHIFT*3)) 368 #define GOP_MUX4_MASK (GOP_REGMUX_MASK<<(GOP_MUX_SHIFT*4)) 369 #define GOP_MUX4_SHIFT 1<<14 370 371 //Priority Setting 372 #define GOP_REGPRI_MASK BMASK(1:0) 373 #define GWIN0_PRI_SHIFT 0 374 #define GWIN0_PRI_MASK (GOP_REGPRI_MASK<<GWIN0_PRI_SHIFT) 375 #define GWIN1_PRI_SHIFT 4 376 #define GWIN1_PRI_MASK (GOP_REGPRI_MASK<<GWIN1_PRI_SHIFT) 377 #define GWIN2_PRI_SHIFT 8 378 #define GWIN2_PRI_MASK (GOP_REGPRI_MASK<<GWIN2_PRI_SHIFT) 379 #define GWIN3_PRI_SHIFT 12 380 #define GWIN3_PRI_MASK (GOP_REGPRI_MASK<<GWIN3_PRI_SHIFT) 381 382 //IP and VOP MUX Setting 383 #define GOP_IP_MAIN_MUX_SHIFT 0 384 #define GOP_IP_MAIN_MUX_MASK (BMASK((GOP_MUX_SHIFT-1):0))<<GOP_IP_MAIN_MUX_SHIFT 385 #define GOP_IP_SUB_MUX_SHIFT 3 386 #define GOP_IP_SUB_MUX_MASK (BMASK((GOP_MUX_SHIFT-1):0))<<GOP_IP_SUB_MUX_SHIFT 387 #define GOP_IP_VOP0_MUX_SHIFT 6 388 #define GOP_IP_VOP0_MUX_MASK (BMASK((GOP_MUX_SHIFT-1):0))<<GOP_IP_VOP0_MUX_SHIFT 389 #define GOP_IP_VOP1_MUX_SHIFT 9 390 #define GOP_IP_VOP1_MUX_MASK (BMASK((GOP_MUX_SHIFT-1):0))<<GOP_IP_VOP1_MUX_SHIFT 391 392 393 //IP and VOP MUX Setting 394 #define GOP_Mix_MUX0_SHIFT 0 395 #define GOP_Mix_MUX0_MASK (BMASK((GOP_MUX_SHIFT-1):0))<<GOP_Mix_MUX0_SHIFT 396 #define GOP_Mix_MUX1_SHIFT 3 397 #define GOP_Mix_MUX1_MASK (BMASK((GOP_MUX_SHIFT-1):0))<<GOP_Mix_MUX1_SHIFT 398 #define GOP_VE0_MUX_SHIFT 6 399 #define GOP_VE0_MUX_MASK (BMASK((GOP_MUX_SHIFT-1):0))<<GOP_VE0_MUX_SHIFT 400 #define GOP_VE1_MUX_SHIFT 9 401 #define GOP_VE1_MUX_MASK (BMASK((GOP_MUX_SHIFT-1):0))<<GOP_VE1_MUX_SHIFT 402 403 404 //4k2k FRC MUX Setting 405 #define GOP_FRC_MUX_SHIFT 0x3 406 #define GOP_FRC_REGMUX_MASK BMASK((GOP_MUX_SHIFT-1):0) 407 #define GOP_FRC_MUX0_MASK (GOP_REGMUX_MASK<<(GOP_MUX_SHIFT*0)) 408 #define GOP_FRC_MUX1_MASK (GOP_REGMUX_MASK<<(GOP_MUX_SHIFT*1)) 409 #define GOP_FRC_MUX2_MASK (GOP_REGMUX_MASK<<(GOP_MUX_SHIFT*2)) 410 #define GOP_FRC_MUX3_MASK (GOP_REGMUX_MASK<<(GOP_MUX_SHIFT*3)) 411 412 // for gwin color format mask 413 #define GOP_REG_COLORTYPE_MASK BMASK(4:0) 414 #define GOP_REG_COLORTYPE_SHIFT 4 415 416 //DIP Setting 417 #define GOP_DIP_MUX_SHIFT 12 418 #define GOP_DIP_MUX_MASK (BMASK((GOP_MUX_SHIFT-1):0))<<GOP_DIP_MUX_SHIFT 419 420 #define GOP_BANK_OFFSET 0x3 421 #define GOP_4G_OFST 0x0 422 #define GOP_2G_OFST (0x1*GOP_BANK_OFFSET) 423 #define GOP_1G_OFST (0x2*GOP_BANK_OFFSET) 424 #define GOP_1GX_OFST (0x3*GOP_BANK_OFFSET) 425 #define GOP_DW_OFST (0x4*GOP_BANK_OFFSET) 426 #define GOP_AFBC_OFST 0xE 427 #define GOP_MIXER_OFST 0xD 428 #define GOP_1GS0_OFST 0x15 429 #define GOP_1GS1_OFST 0x19 430 431 #define GOP_OFFSET_WR 8 432 #define GOP_VAL_WR GOP_REG_VAL(GOP_OFFSET_WR) 433 #define GOP_OFFSET_FWR 9 434 #define GOP_VAL_FWR GOP_REG_VAL(GOP_OFFSET_FWR) 435 #define GOP_OFFSET_FCLR 11 436 #define GOP_VAL_FCL GOP_REG_VAL(GOP_OFFSET_FCLR) 437 #define GOP4G_OFFSET_WR_ACK 12 438 #define GOP4G_VAL_WR_ACK GOP_REG_VAL(GOP4G_OFFSET_WR_ACK) 439 #define GOP2G_OFFSET_WR_ACK 13 440 #define GOP2G_VAL_WR_ACK GOP_REG_VAL(GOP2G_OFFSET_WR_ACK) 441 #define GOPD_OFFSET_WR_ACK 14 442 #define GOPD_VAL_WR_ACK GOP_REG_VAL(GOPD_OFFSET_WR_ACK) 443 #define GOP1G_OFFSET_WR_ACK 15 444 #define GOP1G_VAL_WR_ACK GOP_REG_VAL(GOPD_OFFSET_WR_ACK) 445 #define GOP_VAL_ACK(x) GOP_REG_VAL(GOP4G_OFFSET_WR_ACK+x) 446 447 #define GOP_4G_CTRL0 GOP_REG(GOP_4G_OFST, 0x00) 448 #define GOP_4G_CTRL1 GOP_REG(GOP_4G_OFST, 0x01) 449 #define GOP_4G_RATE GOP_REG(GOP_4G_OFST, 0x02) 450 #define GOP_4G_PALDATA_L GOP_REG(GOP_4G_OFST, 0x03) 451 #define GOP_4G_PALDATA_H GOP_REG(GOP_4G_OFST, 0x04) 452 #define GOP_4G_PALCTRL GOP_REG(GOP_4G_OFST, 0x05) 453 #define GOP_4G_REGDMA_END GOP_REG(GOP_4G_OFST, 0x06) 454 #define GOP_4G_REGDMA_STR GOP_REG(GOP_4G_OFST, 0x07) 455 #define GOP_4G_INT GOP_REG(GOP_4G_OFST, 0x08) 456 #define GOP_4G_HWSTATE GOP_REG(GOP_4G_OFST, 0x09) 457 #define GOP_4G_SVM_HSTR GOP_REG(GOP_4G_OFST, 0x0a) 458 #define GOP_4G_SVM_HEND GOP_REG(GOP_4G_OFST, 0x0b) 459 #define GOP_4G_SVM_VSTR GOP_REG(GOP_4G_OFST, 0x0c) 460 #define GOP_4G_SVM_VEND GOP_REG(GOP_4G_OFST, 0x0d) 461 #define GOP_4G_RDMA_HT GOP_REG(GOP_4G_OFST, 0x0e) 462 #define GOP_4G_HS_PIPE GOP_REG(GOP_4G_OFST, 0x0f) 463 #define GOP_4G_SLOW GOP_REG(GOP_4G_OFST, 0x10) 464 #define GOP_4G_BRI GOP_REG(GOP_4G_OFST, 0x11) 465 #define GOP_4G_CON GOP_REG(GOP_4G_OFST, 0x12) 466 #define GOP_4G_BW GOP_REG(GOP_4G_OFST, 0x19) 467 #define GOP_4G_H121 GOP_REG(GOP_4G_OFST, 0x1B) 468 #define GOP_4G_NEW_BW GOP_REG(GOP_4G_OFST, 0x1C) 469 #define GOP_4G_SRAM_BORROW GOP_REG(GOP_4G_OFST, 0x1D) 470 #define GOP_4G_3D_MIDDLE GOP_REG(GOP_4G_OFST, 0x1E) 471 #define GOP_4G_MIU_SEL GOP_REG(GOP_4G_OFST, 0x1F) 472 #define GOP_4G_PRI0 GOP_REG(GOP_4G_OFST, 0x20) 473 #define GOP_4G_BOT_HS GOP_REG(GOP_4G_OFST, 0x23) 474 #define GOP_4G_TRSCLR_L GOP_REG(GOP_4G_OFST, 0x24) 475 #define GOP_4G_TRSCLR_H GOP_REG(GOP_4G_OFST, 0x25) 476 #define GOP_4G_TRSCLR_TUV_L GOP_REG(GOP_4G_OFST, 0x26) 477 #define GOP_4G_TRSCLR_TUV_H GOP_REG(GOP_4G_OFST, 0x27) 478 #define GOP_4G_YUV_SWAP GOP_REG(GOP_4G_OFST, 0x28) 479 #define GOP_4G_OP_MUX_DBF GOP_REG(GOP_4G_OFST, 0x29) 480 #define GOP_4G_STRCH_HSZ GOP_REG(GOP_4G_OFST, 0x30) 481 #define GOP_4G_STRCH_VSZ GOP_REG(GOP_4G_OFST, 0x31) 482 #define GOP_4G_STRCH_HSTR GOP_REG(GOP_4G_OFST, 0x32) 483 #define GOP_4G_STRCH_VSTR GOP_REG(GOP_4G_OFST, 0x34) 484 #define GOP_4G_HSTRCH GOP_REG(GOP_4G_OFST, 0x35) 485 #define GOP_4G_VSTRCH GOP_REG(GOP_4G_OFST, 0x36) 486 #define GOP_4G_HSTRCH_INI GOP_REG(GOP_4G_OFST, 0x38) 487 #define GOP_4G_VSTRCH_INI GOP_REG(GOP_4G_OFST, 0x39) 488 #define GOP_4G_HVSTRCHMD GOP_REG(GOP_4G_OFST, 0x3a) 489 #define GOP_4G_OLDADDR GOP_REG(GOP_4G_OFST, 0x3b) 490 #define GOP_4G_MULTI_ALPHA GOP_REG(GOP_4G_OFST, 0x3c) 491 #define GOP_4G_VIP_VOP_TIMING_SEL GOP_4G_MULTI_ALPHA 492 #define GOP_4G_TWO_LINEBUFFER GOP_4G_MULTI_ALPHA 493 #define GOP_4G_HW_USAGE GOP_REG(GOP_4G_OFST, 0x40) 494 #define GOP_4G_BANK_FWR GOP_REG(GOP_4G_OFST, 0x50) 495 #define GOP_4G_BANK_HVAILDSIZE GOP_REG(GOP_4G_OFST, 0x52) 496 #define GOP_4G_BANK_VVAILDSIZE GOP_REG(GOP_4G_OFST, 0x53) 497 #define GOP_4G_SCALING_H_OUTPUTSIZE GOP_REG(GOP_4G_OFST, 0x56) 498 #define GOP_4G_SCALING_HRATIO_L GOP_REG(GOP_4G_OFST, 0x59) //GOP scaling down ratio dst / out * 2^20 499 #define GOP_4G_SCALING_HRATIO_H GOP_REG(GOP_4G_OFST, 0x5A) 500 #define GOP_4G_SCALING_CFG GOP_REG(GOP_4G_OFST, 0x5B) 501 #define GOP_4G_SCALING_VRATIO_L GOP_REG(GOP_4G_OFST, 0x5C) //GOP scaling down ratio dst / out * 2^20 502 #define GOP_4G_SCALING_VRATIO_H GOP_REG(GOP_4G_OFST, 0x5D) 503 504 505 #define GOP_4G_RBLK0_VOFFL GOP_REG(GOP_4G_OFST, 0x60) 506 #define GOP_4G_RBLK0_VOFFH GOP_REG(GOP_4G_OFST, 0x61) 507 #define GOP_4G_RBLK1_VOFFL GOP_REG(GOP_4G_OFST, 0x62) 508 #define GOP_4G_RBLK1_VOFFH GOP_REG(GOP_4G_OFST, 0x63) 509 #define GOP_4G_RBLK2_VOFFL GOP_REG(GOP_4G_OFST, 0x64) 510 #define GOP_4G_RBLK2_VOFFH GOP_REG(GOP_4G_OFST, 0x65) 511 #define GOP_4G_RBLK3_VOFFL GOP_REG(GOP_4G_OFST, 0x66) 512 #define GOP_4G_RBLK3_VOFFH GOP_REG(GOP_4G_OFST, 0x67) 513 #define GOP_4G_RBLK0_HOFF GOP_REG(GOP_4G_OFST, 0x70) 514 #define GOP_4G_RBLK1_HOFF GOP_REG(GOP_4G_OFST, 0x71) 515 #define GOP_4G_RBLK2_HOFF GOP_REG(GOP_4G_OFST, 0x72) 516 #define GOP_4G_RBLK3_HOFF GOP_REG(GOP_4G_OFST, 0x73) 517 #define GOP_4G_REGDMA_EN GOP_REG(GOP_4G_OFST, 0x78) 518 #define GOP_MUX_IPVOP __GOP_REG(0x77) 519 #define GOP_MUX_SC1 __GOP_REG(0x7A) 520 #define GOP_MUX4_MIX_VE __GOP_REG(0x7B) 521 #define GOP_BAK_SEL_EX __GOP_REG(0x7C) 522 #define GOP_MUX_4K2K __GOP_REG(0x7D) 523 #define GOP_MUX __GOP_REG(0x7e) 524 #define GOP_BAK_SEL __GOP_REG(0x7f) 525 526 #define GOP_4G_GWIN0_CTRL(id) GOP_REG(GOP_4G_OFST+1, 0x00 + (0x20*((id)%MAX_GOP0_GWIN))) 527 #define GOP_4G_DRAM_RBLK_L(id) GOP_REG(GOP_4G_OFST+1, 0x01 + (0x20*((id)%MAX_GOP0_GWIN))) 528 #define GOP_4G_DRAM_RBLK_H(id) GOP_REG(GOP_4G_OFST+1, 0x02 + (0x20*((id)%MAX_GOP0_GWIN))) 529 #define GOP_4G_DEL_PIXEL(id) GOP_REG(GOP_4G_OFST+1, 0x03 + (0x20*((id)%MAX_GOP1_GWIN))) 530 #define GOP_4G_HSTR(id) GOP_REG(GOP_4G_OFST+1, 0x04 + (0x20*((id)%MAX_GOP0_GWIN))) 531 #define GOP_4G_HEND(id) GOP_REG(GOP_4G_OFST+1, 0x05 + (0x20*((id)%MAX_GOP0_GWIN))) 532 #define GOP_4G_VSTR(id) GOP_REG(GOP_4G_OFST+1, 0x06 + (0x20*((id)%MAX_GOP0_GWIN))) 533 #define GOP_4G_GWIN_MIDDLE(id) GOP_REG(GOP_4G_OFST+1, 0x07 + (0x20*((id)%MAX_GOP0_GWIN))) 534 #define GOP_4G_VEND(id) GOP_REG(GOP_4G_OFST+1, 0x08 + (0x20*((id)%MAX_GOP0_GWIN))) 535 #define GOP_4G_DRAM_RBLK_HSIZE(id) GOP_REG(GOP_4G_OFST+1, 0x09 + (0x20*((id)%MAX_GOP0_GWIN))) 536 #define GOP_4G_GWIN_ALPHA01(id) GOP_REG(GOP_4G_OFST+1, 0x0A + (0x20*((id)%MAX_GOP0_GWIN))) 537 #define GOP_4G_DRAM_VSTR_L(id) GOP_REG(GOP_4G_OFST+1, 0x0C + (0x20*((id)%MAX_GOP0_GWIN))) 538 #define GOP_4G_DRAM_VSTR_H(id) GOP_REG(GOP_4G_OFST+1, 0x0D + (0x20*((id)%MAX_GOP0_GWIN))) 539 #define GOP_4G_DRAM_HSTR(id) GOP_REG(GOP_4G_OFST+1, 0x0E + (0x20*((id)%MAX_GOP0_GWIN))) 540 #define GOP_4G_DRAM_RBLK_SIZE_L(id) GOP_REG(GOP_4G_OFST+1, 0x10 + (0x20*((id)%MAX_GOP0_GWIN))) 541 #define GOP_4G_DRAM_RBLK_SIZE_H(id) GOP_REG(GOP_4G_OFST+1, 0x11 + (0x20*((id)%MAX_GOP0_GWIN))) 542 #define GOP_4G_DRAM_RLEN_L(id) GOP_REG(GOP_4G_OFST+1, 0x12 + (0x20*((id)%MAX_GOP0_GWIN))) 543 #define GOP_4G_DRAM_RLEN_H(id) GOP_REG(GOP_4G_OFST+1, 0x13 + (0x20*((id)%MAX_GOP0_GWIN))) 544 #define GOP_4G_DRAM_HVSTOP_L(id) GOP_REG(GOP_4G_OFST+1, 0x14 + (0x20*((id)%MAX_GOP0_GWIN))) 545 #define GOP_4G_DRAM_HVSTOP_H(id) GOP_REG(GOP_4G_OFST+1, 0x15 + (0x20*((id)%MAX_GOP0_GWIN))) 546 #define GOP_4G_DRAM_FADE(id) GOP_REG(GOP_4G_OFST+1, 0x16 + (0x20*((id)%MAX_GOP0_GWIN))) 547 #define GOP_4G_BG_CLR(id) GOP_REG(GOP_4G_OFST+1, 0x18 + (0x20*((id)%MAX_GOP0_GWIN))) 548 #define GOP_4G_BG_HSTR(id) GOP_REG(GOP_4G_OFST+1, 0x19 + (0x20*((id)%MAX_GOP0_GWIN))) 549 #define GOP_4G_BG_HEND(id) GOP_REG(GOP_4G_OFST+1, 0x1a + (0x20*((id)%MAX_GOP0_GWIN))) 550 #define GOP_4G_BG_VSTR(id) GOP_REG(GOP_4G_OFST+1, 0x1C + (0x20*((id)%MAX_GOP0_GWIN))) 551 #define GOP_4G_BG_VEND(id) GOP_REG(GOP_4G_OFST+1, 0x1D + (0x20*((id)%MAX_GOP0_GWIN))) 552 #define GOP_4G_3DOSD_SUB_RBLK_L(id) GOP_REG(GOP_4G_OFST+1, 0x1E + (0x20*((id)%MAX_GOP0_GWIN))) 553 #define GOP_4G_3DOSD_SUB_RBLK_H(id) GOP_REG(GOP_4G_OFST+1, 0x1F + (0x20*((id)%MAX_GOP0_GWIN))) 554 555 556 #define GOP_2G_CTRL0 GOP_REG(GOP_2G_OFST, 0x00) 557 #define GOP_2G_CTRL1 GOP_REG(GOP_2G_OFST, 0x01) 558 #define GOP_2G_RATE GOP_REG(GOP_2G_OFST, 0x02) 559 #define GOP_2G_PALDATA_L GOP_REG(GOP_2G_OFST, 0x03) 560 #define GOP_2G_PALDATA_H GOP_REG(GOP_2G_OFST, 0x04) 561 #define GOP_2G_PALCTRL GOP_REG(GOP_2G_OFST, 0x05) 562 #define GOP_2G_REGDMA_END GOP_REG(GOP_2G_OFST, 0x06) 563 #define GOP_2G_REGDMA_STR GOP_REG(GOP_2G_OFST, 0x07) 564 #define GOP_2G_INT GOP_REG(GOP_2G_OFST, 0x08) 565 #define GOP_2G_HWSTATE GOP_REG(GOP_2G_OFST, 0x09) 566 #define GOP_2G_RDMA_HT GOP_REG(GOP_2G_OFST, 0x0e) 567 #define GOP_2G_HS_PIPE GOP_REG(GOP_2G_OFST, 0x0f) 568 #define GOP_2G_SLOW GOP_REG(GOP_2G_OFST, 0x10) 569 #define GOP_2G_BRI GOP_REG(GOP_2G_OFST, 0x11) 570 #define GOP_2G_CON GOP_REG(GOP_2G_OFST, 0x12) 571 #define GOP_2G_BW GOP_REG(GOP_2G_OFST, 0x19) 572 #define GOP_2G_3D_MIDDLE GOP_REG(GOP_2G_OFST, 0x1E) 573 #define GOP_2G_PRI0 GOP_REG(GOP_2G_OFST, 0x20) 574 #define GOP_2G_TRSCLR_L GOP_REG(GOP_2G_OFST, 0x24) 575 #define GOP_2G_TRSCLR_H GOP_REG(GOP_2G_OFST, 0x25) 576 #define GOP_2G_STRCH_HSZ GOP_REG(GOP_2G_OFST, 0x30) 577 #define GOP_2G_STRCH_VSZ GOP_REG(GOP_2G_OFST, 0x31) 578 #define GOP_2G_STRCH_HSTR GOP_REG(GOP_2G_OFST, 0x32) 579 #define GOP_2G_STRCH_VSTR GOP_REG(GOP_2G_OFST, 0x34) 580 #define GOP_2G_HSTRCH GOP_REG(GOP_2G_OFST, 0x35) 581 #define GOP_2G_VSTRCH GOP_REG(GOP_2G_OFST, 0x36) 582 #define GOP_2G_HSTRCH_INI GOP_REG(GOP_2G_OFST, 0x38) 583 #define GOP_2G_VSTRCH_INI GOP_REG(GOP_2G_OFST, 0x39) 584 #define GOP_2G_HVStrch_MD GOP_REG(GOP_2G_OFST, 0x3a) 585 #define GOP_2G_OLDADDR GOP_REG(GOP_2G_OFST, 0x3b) 586 #define GOP_2G_MULTI_ALPHA GOP_REG(GOP_2G_OFST, 0x3c) 587 #define GOP_2G_REGDMA_EN GOP_REG(GOP_2G_OFST, 0x78) 588 589 590 #define GOP_2G_GWIN0_CTRL(id) GOP_REG(GOP_2G_OFST+1, 0x00 + (0x20*((id)%MAX_GOP1_GWIN))) 591 #define GOP_2G_GWIN_CTRL(id) GOP_REG(GOP_2G_OFST+1, 0x00 + (0x20*((id)%MAX_GOP1_GWIN))) 592 #define GOP_2G_DRAM_RBLK_L(id) GOP_REG(GOP_2G_OFST+1, 0x01 + (0x20*((id)%MAX_GOP1_GWIN))) 593 #define GOP_2G_DRAM_RBLK_H(id) GOP_REG(GOP_2G_OFST+1, 0x02 + (0x20*((id)%MAX_GOP1_GWIN))) 594 #define GOP_2G_DEL_PIXEL(id) GOP_REG(GOP_2G_OFST+1, 0x03 + (0x20*((id)%MAX_GOP1_GWIN))) 595 #define GOP_2G_HSTR(id) GOP_REG(GOP_2G_OFST+1, 0x04 + (0x20*((id)%MAX_GOP1_GWIN))) 596 #define GOP_2G_HEND(id) GOP_REG(GOP_2G_OFST+1, 0x05 + (0x20*((id)%MAX_GOP1_GWIN))) 597 #define GOP_2G_VSTR(id) GOP_REG(GOP_2G_OFST+1, 0x06 + (0x20*((id)%MAX_GOP1_GWIN))) 598 #define GOP_2G_VEND(id) GOP_REG(GOP_2G_OFST+1, 0x08 + (0x20*((id)%MAX_GOP1_GWIN))) 599 #define GOP_2G_DRAM_RBLK_HSIZE(id) GOP_REG(GOP_2G_OFST+1, 0x09 + (0x20*((id)%MAX_GOP1_GWIN))) 600 #define GOP_2G_GWIN_ALPHA01(id) GOP_REG(GOP_2G_OFST+1, 0x0A + (0x20*((id)%MAX_GOP1_GWIN))) 601 #define GOP_2G_DRAM_VSTR_L(id) GOP_REG(GOP_2G_OFST+1, 0x0C + (0x20*((id)%MAX_GOP1_GWIN))) 602 #define GOP_2G_DRAM_VSTR_H(id) GOP_REG(GOP_2G_OFST+1, 0x0D + (0x20*((id)%MAX_GOP1_GWIN))) 603 #define GOP_2G_DRAM_FADE(id) GOP_REG(GOP_2G_OFST+1, 0x16 + (0x20*((id)%MAX_GOP1_GWIN))) 604 #define GOP_2G_3DOSD_SUB_RBLK_L(id) GOP_REG(GOP_2G_OFST+1, 0x1E + (0x20*((id)%MAX_GOP1_GWIN))) 605 #define GOP_2G_3DOSD_SUB_RBLK_H(id) GOP_REG(GOP_2G_OFST+1, 0x1F + (0x20*((id)%MAX_GOP1_GWIN))) 606 607 // DWIN reg 608 #define GOP_DW_CTL0_EN GOP_REG(GOP_DW_OFST, 0x00) 609 #define GOP_DWIN_EN (0x00) 610 #define GOP_DWIN_EN_VAL GOP_REG_VAL(GOP_DWIN_EN) 611 #define GOP_DWIN_SHOT (0x07) 612 #define GOP_DWIN_SHOT_VAL GOP_REG_VAL(GOP_DWIN_SHOT) 613 614 #define GOP_DW_LSTR_WBE GOP_REG(GOP_DW_OFST, 0x01) 615 #define GOP_DW_INT_MASK GOP_REG(GOP_DW_OFST, 0x02) 616 #define GOP_DW_DEBUG GOP_REG(GOP_DW_OFST, 0x03) 617 #define GOP_DW_ALPHA GOP_REG(GOP_DW_OFST, 0x04) 618 #define GOP_DW_BW GOP_REG(GOP_DW_OFST, 0x05) 619 #define GOP_DW_VSTR GOP_REG(GOP_DW_OFST, 0x10) 620 #define GOP_DW_HSTR GOP_REG(GOP_DW_OFST, 0x11) 621 #define GOP_DW_VEND GOP_REG(GOP_DW_OFST, 0x12) 622 #define GOP_DW_HEND GOP_REG(GOP_DW_OFST, 0x13) 623 #define GOP_DW_HSIZE GOP_REG(GOP_DW_OFST, 0x14) 624 #define GOP_DW_JMPLEN GOP_REG(GOP_DW_OFST, 0x15) 625 #define GOP_DW_DSTR_L GOP_REG(GOP_DW_OFST, 0x16) 626 #define GOP_DW_DSTR_H GOP_REG(GOP_DW_OFST, 0x17) 627 #define GOP_DW_UB_L GOP_REG(GOP_DW_OFST, 0x18) 628 #define GOP_DW_UB_H GOP_REG(GOP_DW_OFST, 0x19) 629 630 #define GOP_DW_PON_DSTR_L GOP_REG(GOP_DW_OFST, 0x1a) 631 #define GOP_DW_PON_DSTR_H GOP_REG(GOP_DW_OFST, 0x1b) 632 #define GOP_DW_PON_UB_L GOP_REG(GOP_DW_OFST, 0x1c) 633 #define GOP_DW_PON_UB_H GOP_REG(GOP_DW_OFST, 0x1d) 634 #define GOP_DW_FRAME_CTRL GOP_REG(GOP_DW_OFST, 0x30) 635 636 #define GOP_VE_DATA_MUX GOP_REG(GOP_MIXER_OFST, 0x30) 637 638 #define GOP_1G_CTRL0 GOP_REG(GOP_1G_OFST, 0x00) 639 #define GOP_1G_CTRL1 GOP_REG(GOP_1G_OFST, 0x01) 640 #define GOP_1G_RATE GOP_REG(GOP_1G_OFST, 0x02) 641 #define GOP_1G_PALDATA_L GOP_REG(GOP_1G_OFST, 0x03) 642 #define GOP_1G_PALDATA_H GOP_REG(GOP_1G_OFST, 0x04) 643 #define GOP_1G_PALCTRL GOP_REG(GOP_1G_OFST, 0x05) 644 #define GOP_1G_REGDMA_END GOP_REG(GOP_1G_OFST, 0x06) 645 #define GOP_1G_REGDMA_STR GOP_REG(GOP_1G_OFST, 0x07) 646 #define GOP_1G_INT GOP_REG(GOP_1G_OFST, 0x08) 647 #define GOP_1G_HWSTATE GOP_REG(GOP_1G_OFST, 0x09) 648 #define GOP_1G_RDMA_HT GOP_REG(GOP_1G_OFST, 0x0e) 649 #define GOP_1G_HS_PIPE GOP_REG(GOP_1G_OFST, 0x0f) 650 #define GOP_1G_BRI GOP_REG(GOP_1G_OFST, 0x11) 651 #define GOP_1G_CON GOP_REG(GOP_1G_OFST, 0x12) 652 #define GOP_1G_BW GOP_REG(GOP_1G_OFST, 0x19) 653 #define GOP_1G_3D_MIDDLE GOP_REG(GOP_1G_OFST, 0x1E) 654 #define GOP_1G_TRSCLR_L GOP_REG(GOP_1G_OFST, 0x24) 655 #define GOP_1G_TRSCLR_H GOP_REG(GOP_1G_OFST, 0x25) 656 #define GOP_1G_STRCH_HSZ GOP_REG(GOP_1G_OFST, 0x30) 657 #define GOP_1G_STRCH_VSZ GOP_REG(GOP_1G_OFST, 0x31) 658 #define GOP_1G_STRCH_HSTR GOP_REG(GOP_1G_OFST, 0x32) 659 #define GOP_1G_STRCH_VSTR GOP_REG(GOP_1G_OFST, 0x34) 660 #define GOP_1G_HSTRCH GOP_REG(GOP_1G_OFST, 0x35) 661 #define GOP_1G_HSTRCH_INI GOP_REG(GOP_1G_OFST, 0x38) 662 #define GOP_1G_VSTRCH_INI GOP_REG(GOP_1G_OFST, 0x39) 663 #define GOP_1G_HStrch_MD GOP_REG(GOP_1G_OFST, 0x3a) 664 #define GOP_1G_OLDADDR GOP_REG(GOP_1G_OFST, 0x3b) 665 #define GOP_1G_MULTI_ALPHA GOP_REG(GOP_1G_OFST, 0x3c) 666 667 #define GOP_1G_GWIN0_CTRL GOP_REG(GOP_1G_OFST+1, 0x0) 668 #define GOP_1G_DRAM_RBLK_L GOP_REG(GOP_1G_OFST+1, 0x1) 669 #define GOP_1G_DRAM_RBLK_H GOP_REG(GOP_1G_OFST+1, 0x2) 670 #define GOP_1G_DEL_PIXEL GOP_REG(GOP_1G_OFST+1, 0x3) 671 #define GOP_1G_HSTR GOP_REG(GOP_1G_OFST+1, 0x4) 672 #define GOP_1G_HEND GOP_REG(GOP_1G_OFST+1, 0x5) 673 #define GOP_1G_VSTR GOP_REG(GOP_1G_OFST+1, 0x6) 674 #define GOP_1G_VEND GOP_REG(GOP_1G_OFST+1, 0x8) 675 #define GOP_1G_DRAM_RBLK_HSIZE GOP_REG(GOP_1G_OFST+1, 0x9) 676 #define GOP_1G_GWIN_ALPHA01 GOP_REG(GOP_1G_OFST+1, 0xA) 677 #define GOP_1G_DRAM_VSTR_L GOP_REG(GOP_1G_OFST+1, 0x0C) 678 #define GOP_1G_DRAM_VSTR_H GOP_REG(GOP_1G_OFST+1, 0x0D) 679 #define GOP_1G_DRAM_FADE GOP_REG(GOP_1G_OFST+1, 0x16) 680 #define GOP_1G_3DOSD_SUB_RBLK_L GOP_REG(GOP_1G_OFST+1, 0x1E) 681 #define GOP_1G_3DOSD_SUB_RBLK_H GOP_REG(GOP_1G_OFST+1, 0x1F) 682 683 #define GOP_1GX_CTRL0 GOP_REG(GOP_1GX_OFST, 0x00) 684 #define GOP_1GX_CTRL1 GOP_REG(GOP_1GX_OFST, 0x01) 685 #define GOP_1GX_RATE GOP_REG(GOP_1GX_OFST, 0x02) 686 #define GOP_1GX_PALDATA_L GOP_REG(GOP_1GX_OFST, 0x03) 687 #define GOP_1GX_PALDATA_H GOP_REG(GOP_1GX_OFST, 0x04) 688 #define GOP_1GX_PALCTRL GOP_REG(GOP_1GX_OFST, 0x05) 689 #define GOP_1GX_REGDMA_END GOP_REG(GOP_1GX_OFST, 0x06) 690 #define GOP_1GX_REGDMA_STR GOP_REG(GOP_1GX_OFST, 0x07) 691 #define GOP_1GX_INT GOP_REG(GOP_1GX_OFST, 0x08) 692 #define GOP_1GX_HWSTATE GOP_REG(GOP_1GX_OFST, 0x09) 693 #define GOP_1GX_RDMA_HT GOP_REG(GOP_1GX_OFST, 0x0e) 694 #define GOP_1GX_HS_PIPE GOP_REG(GOP_1GX_OFST, 0x0f) 695 #define GOP_1GX_BRI GOP_REG(GOP_1GX_OFST, 0x11) 696 #define GOP_1GX_CON GOP_REG(GOP_1GX_OFST, 0x12) 697 #define GOP_1GX_BW GOP_REG(GOP_1GX_OFST, 0x19) 698 #define GOP_1GX_3D_MIDDLE GOP_REG(GOP_1GX_OFST, 0x1E) 699 #define GOP_1GX_TRSCLR_L GOP_REG(GOP_1GX_OFST, 0x24) 700 #define GOP_1GX_TRSCLR_H GOP_REG(GOP_1GX_OFST, 0x25) 701 #define GOP_1GX_STRCH_HSZ GOP_REG(GOP_1GX_OFST, 0x30) 702 #define GOP_1GX_STRCH_VSZ GOP_REG(GOP_1GX_OFST, 0x31) 703 #define GOP_1GX_STRCH_HSTR GOP_REG(GOP_1GX_OFST, 0x32) 704 #define GOP_1GX_STRCH_VSTR GOP_REG(GOP_1GX_OFST, 0x34) 705 #define GOP_1GX_HSTRCH GOP_REG(GOP_1GX_OFST, 0x35) 706 #define GOP_1GX_HSTRCH_INI GOP_REG(GOP_1GX_OFST, 0x38) 707 #define GOP_1GX_VSTRCH_INI GOP_REG(GOP_1GX_OFST, 0x39) 708 #define GOP_1GX_HStrch_MD GOP_REG(GOP_1GX_OFST, 0x3a) 709 #define GOP_1GX_OLDADDR GOP_REG(GOP_1GX_OFST, 0x3b) 710 #define GOP_1GX_MULTI_ALPHA GOP_REG(GOP_1GX_OFST, 0x3c) 711 712 #define GOP_1GX_GWIN0_CTRL GOP_REG(GOP_1GX_OFST+1, 0x00) 713 #define GOP_1GX_DRAM_RBLK_L GOP_REG(GOP_1GX_OFST+1, 0x01) 714 #define GOP_1GX_DRAM_RBLK_H GOP_REG(GOP_1GX_OFST+1, 0x02) 715 #define GOP_1GX_DEL_PIXEL GOP_REG(GOP_1GX_OFST+1, 0x03) 716 #define GOP_1GX_HSTR GOP_REG(GOP_1GX_OFST+1, 0x04) 717 #define GOP_1GX_HEND GOP_REG(GOP_1GX_OFST+1, 0x05) 718 #define GOP_1GX_VSTR GOP_REG(GOP_1GX_OFST+1, 0x06) 719 #define GOP_1GX_VEND GOP_REG(GOP_1GX_OFST+1, 0x08) 720 #define GOP_1GX_DRAM_RBLK_HSIZE GOP_REG(GOP_1GX_OFST+1, 0x09) 721 #define GOP_1GX_GWIN_ALPHA01 GOP_REG(GOP_1GX_OFST+1, 0x0A) 722 #define GOP_1GX_DRAM_VSTR_L GOP_REG(GOP_1GX_OFST+1, 0x0C) 723 #define GOP_1GX_DRAM_VSTR_H GOP_REG(GOP_1GX_OFST+1, 0x0D) 724 #define GOP_1GX_DRAM_FADE GOP_REG(GOP_1GX_OFST+1, 0x16) 725 #define GOP_1GX_3DOSD_SUB_RBLK_L GOP_REG(GOP_1GX_OFST+1, 0x1E) 726 #define GOP_1GX_3DOSD_SUB_RBLK_H GOP_REG(GOP_1GX_OFST+1, 0x1F) 727 728 #define GOP_MIXER_CTRL GOP_REG(GOP_MIXER_OFST, 0x0) 729 730 #define GOP_MIXER_EN_GOP_MIX0 (1<<0) 731 #define GOP_MIXER_EN_GOP_MIX1 (1<<1) 732 #define GOP_MIXER_GOP_MIX_MODE (1<<2) 733 #define GOP_MIXER_HS_POL (1<<5) 734 #define GOP_MIXER_VS_POL (1<<6) 735 #define GOP_MIXER_EN_FLD_FREERUN_MD (1<<7) 736 #define GOP_MIXER_INV_FIELD_VEOSD (1<<8) 737 #define GOP_MIXER_ABL_POL (1<<9) 738 #define GOP_MIXER_EN_MIX (1<<15) 739 740 741 #define GOP_MIXER_FHST GOP_REG(GOP_MIXER_OFST, 0x1) 742 #define GOP_MIXER_FVST GOP_REG(GOP_MIXER_OFST, 0x2) 743 #define GOP_MIXER_FHEND GOP_REG(GOP_MIXER_OFST, 0x3) 744 #define GOP_MIXER_FVEND GOP_REG(GOP_MIXER_OFST, 0x4) 745 #define GOP_MIXER_HTT GOP_REG(GOP_MIXER_OFST, 0x5) 746 #define GOP_MIXER_HS_DELAY GOP_REG(GOP_MIXER_OFST, 0x6) 747 #define GOP_MIXER_FLD_DELAY_LINE GOP_REG(GOP_MIXER_OFST, 0x7) 748 #define GOP_MIXER_FLD_DE_ADJUST GOP_REG(GOP_MIXER_OFST, 0x8) 749 #define GOP_MIXER_C_FIL_COEF0COEF1 GOP_REG(GOP_MIXER_OFST, 0x9) 750 #define GOP_MIXER_C_FIL_COEF2COEF3 GOP_REG(GOP_MIXER_OFST, 0xa) 751 #define GOP_MIXER_VFIL_RATIO GOP_REG(GOP_MIXER_OFST, 0xb) 752 #define GOP_MIXER_MIX_DUMMY GOP_REG(GOP_MIXER_OFST, 0xc) 753 #define GOP_MIXER_DEBUG_H GOP_REG(GOP_MIXER_OFST, 0xd) 754 #define GOP_MIXER_DEBUG_V GOP_REG(GOP_MIXER_OFST, 0xe) 755 #define GOP_MIXER_DEBUG_PIXEL_L GOP_REG(GOP_MIXER_OFST, 0xf) 756 #define GOP_MIXER_DEBUG_PIXEL_H GOP_REG(GOP_MIXER_OFST, 0x10) 757 #define GOP_MIXER_VE GOP_REG(GOP_MIXER_OFST, 0x11) 758 #define GOP_MIXER_FULL_WIN_DE GOP_REG(GOP_MIXER_OFST, 0x20) 759 #define GOP_VE_DATA_MUX GOP_REG(GOP_MIXER_OFST, 0x30) 760 761 #define GOP_MIXER_EN_VFIL (1<<0) 762 #define GOP_MIXER_EN_VFIL_MASK GOP_BIT0 763 #define GOP_MIXER_VS_FLD_ON (1<<7) 764 #define GOP_MIXER_VS_FLD_ON_MASK GOP_BIT7 765 #define GOP_MIXER_REG_DUMMY GOP_REG(GOP_MIXER_OFST, 0x20) 766 767 #define GOP_1GS0_CTRL0 GOP_REG(GOP_1GS0_OFST, 0x00) 768 #define GOP_1GS0_CTRL1 GOP_REG(GOP_1GS0_OFST, 0x01) 769 #define GOP_1GS0_RATE GOP_REG(GOP_1GS0_OFST, 0x02) 770 #define GOP_1GS0_PALDATA_L GOP_REG(GOP_1GS0_OFST, 0x03) 771 #define GOP_1GS0_PALDATA_H GOP_REG(GOP_1GS0_OFST, 0x04) 772 #define GOP_1GS0_PALCTRL GOP_REG(GOP_1GS0_OFST, 0x05) 773 #define GOP_1GS0_REGDMA_END GOP_REG(GOP_1GS0_OFST, 0x06) 774 #define GOP_1GS0_REGDMA_STR GOP_REG(GOP_1GS0_OFST, 0x07) 775 #define GOP_1GS0_INT GOP_REG(GOP_1GS0_OFST, 0x08) 776 #define GOP_1GS0_HWSTATE GOP_REG(GOP_1GS0_OFST, 0x09) 777 #define GOP_1GS0_RDMA_HT GOP_REG(GOP_1GS0_OFST, 0x0e) 778 #define GOP_1GS0_HS_PIPE GOP_REG(GOP_1GS0_OFST, 0x0f) 779 #define GOP_1GS0_BRI GOP_REG(GOP_1GS0_OFST, 0x11) 780 #define GOP_1GS0_CON GOP_REG(GOP_1GS0_OFST, 0x12) 781 #define GOP_1GS0_BW GOP_REG(GOP_1GS0_OFST, 0x19) 782 #define GOP_1GS0_TRSCLR_L GOP_REG(GOP_1GS0_OFST, 0x24) 783 #define GOP_1GS0_TRSCLR_H GOP_REG(GOP_1GS0_OFST, 0x25) 784 #define GOP_1GS0_STRCH_HSZ GOP_REG(GOP_1GS0_OFST, 0x30) 785 #define GOP_1GS0_STRCH_VSZ GOP_REG(GOP_1GS0_OFST, 0x31) 786 #define GOP_1GS0_STRCH_HSTR GOP_REG(GOP_1GS0_OFST, 0x32) 787 #define GOP_1GS0_STRCH_VSTR GOP_REG(GOP_1GS0_OFST, 0x34) 788 #define GOP_1GS0_HSTRCH GOP_REG(GOP_1GS0_OFST, 0x35) 789 #define GOP_1GS0_HSTRCH_INI GOP_REG(GOP_1GS0_OFST, 0x38) 790 #define GOP_1GS0_VSTRCH_INI GOP_REG(GOP_1GS0_OFST, 0x39) 791 #define GOP_1GS0_HVStrch_MD GOP_REG(GOP_1GS0_OFST, 0x3a) 792 #define GOP_1GS0_OLDADDR GOP_REG(GOP_1GS0_OFST, 0x3b) 793 #define GOP_1GS0_MULTI_ALPHA GOP_REG(GOP_1GS0_OFST, 0x3c) 794 795 #define GOP_1GS0_GWIN0_CTRL GOP_REG(GOP_1GS0_OFST+1, 0x00) 796 #define GOP_1GS0_DRAM_RBLK_L GOP_REG(GOP_1GS0_OFST+1, 0x01) 797 #define GOP_1GS0_DRAM_RBLK_H GOP_REG(GOP_1GS0_OFST+1, 0x02) 798 #define GOP_1GS0_DEL_PIXEL GOP_REG(GOP_1GS0_OFST+1, 0x03) 799 #define GOP_1GS0_HSTR GOP_REG(GOP_1GS0_OFST+1, 0x04) 800 #define GOP_1GS0_HEND GOP_REG(GOP_1GS0_OFST+1, 0x05) 801 #define GOP_1GS0_VSTR GOP_REG(GOP_1GS0_OFST+1, 0x06) 802 #define GOP_1GS0_VEND GOP_REG(GOP_1GS0_OFST+1, 0x08) 803 #define GOP_1GS0_DRAM_RBLK_HSIZE GOP_REG(GOP_1GS0_OFST+1, 0x09) 804 #define GOP_1GS0_GWIN_ALPHA01 GOP_REG(GOP_1GS0_OFST+1, 0x0A) 805 #define GOP_1GS0_DRAM_VSTR_L GOP_REG(GOP_1GS0_OFST+1, 0x0C) 806 #define GOP_1GS0_DRAM_VSTR_H GOP_REG(GOP_1GS0_OFST+1, 0x0D) 807 #define GOP_1GS0_DRAM_FADE GOP_REG(GOP_1GS0_OFST+1, 0x16) 808 #define GOP_1GS0_3DOSD_SUB_RBLK_L GOP_REG(GOP_1GS0_OFST+1, 0x1E) 809 #define GOP_1GS0_3DOSD_SUB_RBLK_H GOP_REG(GOP_1GS0_OFST+1, 0x1F) 810 811 #define GOP_1GS1_CTRL0 GOP_REG(GOP_1GS1_OFST, 0x00) 812 #define GOP_1GS1_CTRL1 GOP_REG(GOP_1GS1_OFST, 0x01) 813 #define GOP_1GS1_RATE GOP_REG(GOP_1GS1_OFST, 0x02) 814 #define GOP_1GS1_PALDATA_L GOP_REG(GOP_1GS1_OFST, 0x03) 815 #define GOP_1GS1_PALDATA_H GOP_REG(GOP_1GS1_OFST, 0x04) 816 #define GOP_1GS1_PALCTRL GOP_REG(GOP_1GS1_OFST, 0x05) 817 #define GOP_1GS1_REGDMA_END GOP_REG(GOP_1GS1_OFST, 0x06) 818 #define GOP_1GS1_REGDMA_STR GOP_REG(GOP_1GS1_OFST, 0x07) 819 #define GOP_1GS1_INT GOP_REG(GOP_1GS1_OFST, 0x08) 820 #define GOP_1GS1_HWSTATE GOP_REG(GOP_1GS1_OFST, 0x09) 821 #define GOP_1GS1_RDMA_HT GOP_REG(GOP_1GS1_OFST, 0x0e) 822 #define GOP_1GS1_HS_PIPE GOP_REG(GOP_1GS1_OFST, 0x0f) 823 #define GOP_1GS1_BRI GOP_REG(GOP_1GS1_OFST, 0x11) 824 #define GOP_1GS1_CON GOP_REG(GOP_1GS1_OFST, 0x12) 825 #define GOP_1GS1_BW GOP_REG(GOP_1GS1_OFST, 0x19) 826 #define GOP_1GS1_TRSCLR_L GOP_REG(GOP_1GS1_OFST, 0x24) 827 #define GOP_1GS1_TRSCLR_H GOP_REG(GOP_1GS1_OFST, 0x25) 828 #define GOP_1GS1_STRCH_HSZ GOP_REG(GOP_1GS1_OFST, 0x30) 829 #define GOP_1GS1_STRCH_VSZ GOP_REG(GOP_1GS1_OFST, 0x31) 830 #define GOP_1GS1_STRCH_HSTR GOP_REG(GOP_1GS1_OFST, 0x32) 831 #define GOP_1GS1_STRCH_VSTR GOP_REG(GOP_1GS1_OFST, 0x34) 832 #define GOP_1GS1_HSTRCH GOP_REG(GOP_1GS1_OFST, 0x35) 833 #define GOP_1GS1_HSTRCH_INI GOP_REG(GOP_1GS1_OFST, 0x38) 834 #define GOP_1GS1_VSTRCH_INI GOP_REG(GOP_1GS1_OFST, 0x39) 835 #define GOP_1GS1_HVStrch_MD GOP_REG(GOP_1GS1_OFST, 0x3a) 836 #define GOP_1GS1_OLDADDR GOP_REG(GOP_1GS1_OFST, 0x3b) 837 #define GOP_1GS1_MULTI_ALPHA GOP_REG(GOP_1GS1_OFST, 0x3c) 838 839 #define GOP_1GS1_GWIN0_CTRL GOP_REG(GOP_1GS1_OFST+1, 0x00) 840 #define GOP_1GS1_DRAM_RBLK_L GOP_REG(GOP_1GS1_OFST+1, 0x01) 841 #define GOP_1GS1_DRAM_RBLK_H GOP_REG(GOP_1GS1_OFST+1, 0x02) 842 #define GOP_1GS1_DEL_PIXEL GOP_REG(GOP_1GS1_OFST+1, 0x03) 843 #define GOP_1GS1_HSTR GOP_REG(GOP_1GS1_OFST+1, 0x04) 844 #define GOP_1GS1_HEND GOP_REG(GOP_1GS1_OFST+1, 0x05) 845 #define GOP_1GS1_VSTR GOP_REG(GOP_1GS1_OFST+1, 0x06) 846 #define GOP_1GS1_VEND GOP_REG(GOP_1GS1_OFST+1, 0x08) 847 #define GOP_1GS1_DRAM_RBLK_HSIZE GOP_REG(GOP_1GS1_OFST+1, 0x09) 848 #define GOP_1GS1_GWIN_ALPHA01 GOP_REG(GOP_1GS1_OFST+1, 0x0A) 849 #define GOP_1GS1_DRAM_VSTR_L GOP_REG(GOP_1GS1_OFST+1, 0x0C) 850 #define GOP_1GS1_DRAM_VSTR_H GOP_REG(GOP_1GS1_OFST+1, 0x0D) 851 #define GOP_1GS1_DRAM_FADE GOP_REG(GOP_1GS1_OFST+1, 0x16) 852 #define GOP_1GS1_3DOSD_SUB_RBLK_L GOP_REG(GOP_1GS1_OFST+1, 0x1E) 853 #define GOP_1GS1_3DOSD_SUB_RBLK_H GOP_REG(GOP_1GS1_OFST+1, 0x1F) 854 //------------------------------------------------------------------------------------------------- 855 // Type and Structure 856 //------------------------------------------------------------------------------------------------- 857 858 //---------------------------------------------------------------------------- 859 // GOP Test Pattern Reg 860 //---------------------------------------------------------------------------- 861 #define REG_TSTCLR_EN GOP_REG(GOP_4G_OFST, 0x00) 862 #define REG_TSTCLR_ALPHA_EN GOP_REG(GOP_4G_OFST+2, 0x00) 863 #define REG_TLB_TAG_ADDR_L GOP_REG(GOP_4G_OFST+2, 0x2C) 864 #define REG_TLB_TAG_ADDR_H GOP_REG(GOP_4G_OFST+2, 0x2D) 865 #define REG_TLB_TAG_ADDR_RVIEW_L GOP_REG(GOP_4G_OFST+2, 0x2E) 866 #define REG_TLB_TAG_ADDR_RVIEW_H GOP_REG(GOP_4G_OFST+2, 0x2F) 867 #define REG_TSTCLR_ALPHA GOP_REG(GOP_4G_OFST+2, 0x40) 868 #define REG_R_STC GOP_REG(GOP_4G_OFST+2, 0x41) 869 #define REG_G_STC GOP_REG(GOP_4G_OFST+2, 0x48) 870 #define REG_B_STC GOP_REG(GOP_4G_OFST+2, 0x49) 871 #define REG_TSTCLR_HDUP GOP_REG(GOP_4G_OFST+2, 0x01) 872 #define REG_TSTCLR_VDUP GOP_REG(GOP_4G_OFST+2, 0x01) 873 #define REG_HR_INC GOP_REG(GOP_4G_OFST+2, 0x42) 874 #define REG_HR_INC_SIGNZ GOP_REG(GOP_4G_OFST+2, 0x42) 875 #define REG_HG_INC GOP_REG(GOP_4G_OFST+2, 0x43) 876 #define REG_HG_INC_SIGNZ GOP_REG(GOP_4G_OFST+2, 0x43) 877 #define REG_HB_INC GOP_REG(GOP_4G_OFST+2, 0x44) 878 #define REG_HB_INC_SIGNZ GOP_REG(GOP_4G_OFST+2, 0x44) 879 #define REG_HR_STEP GOP_REG(GOP_4G_OFST+2, 0x4A) 880 #define REG_HG_STEP GOP_REG(GOP_4G_OFST+2, 0x4B) 881 #define REG_HB_STEP GOP_REG(GOP_4G_OFST+2, 0x4C) 882 #define REG_VR_INC GOP_REG(GOP_4G_OFST+2, 0x45) 883 #define REG_VR_INC_SIGNZ GOP_REG(GOP_4G_OFST+2, 0x45) 884 #define REG_VG_INC GOP_REG(GOP_4G_OFST+2, 0x46) 885 #define REG_VG_INC_SIGNZ GOP_REG(GOP_4G_OFST+2, 0x46) 886 #define REG_VB_INC GOP_REG(GOP_4G_OFST+2, 0x47) 887 #define REG_VB_INC_SIGNZ GOP_REG(GOP_4G_OFST+2, 0x47) 888 #define REG_VR_STEP GOP_REG(GOP_4G_OFST+2, 0x4D) 889 #define REG_VG_STEP GOP_REG(GOP_4G_OFST+2, 0x4E) 890 #define REG_VB_STEP GOP_REG(GOP_4G_OFST+2, 0x4F) 891 #define REG_TLB_BASE_ADDR_L GOP_REG(GOP_4G_OFST+2, 0x58) 892 #define REG_TLB_BASE_ADDR_H GOP_REG(GOP_4G_OFST+2, 0x59) 893 #define REG_TLB_BASE_ADDR_RVIEW_L GOP_REG(GOP_4G_OFST+2, 0x5A) 894 #define REG_TLB_BASE_ADDR_RVIEW_H GOP_REG(GOP_4G_OFST+2, 0x5B) 895 896 #define MASK_TSTCLR_EN GOP_BIT6 897 #define MASK_TSTCLR_ALPHA_EN GOP_BIT1 898 #define MASK_TSTCLR_ALPHA BMASK(11:8)|BMASK(3:0) 899 #define MASK_RGB_STC_VALID BMASK(7:0) 900 #define MASK_R_STC BMASK(11:8)|BMASK(3:0) 901 #define MASK_G_STC BMASK(11:8)|BMASK(3:0) 902 #define MASK_B_STC BMASK(11:8)|BMASK(3:0) 903 #define MASK_INI_TSTCLR_EN GOP_BIT0 904 #define MASK_TSTCLR_HDUP BMASK(3:2) 905 #define MASK_TSTCLR_VDUP BMASK(1:0) 906 #define MASK_HR_INC BMASK(10:8)|BMASK(3:0) 907 #define MASK_HR_INC_SIGNZ GOP_BIT11 908 #define MASK_HG_INC BMASK(10:8)|BMASK(3:0) 909 #define MASK_HG_INC_SIGNZ GOP_BIT11 910 #define MASK_HB_INC BMASK(10:8)|BMASK(3:0) 911 #define MASK_HB_INC_SIGNZ GOP_BIT11 912 #define MASK_HR_STEP BMASK(11:8)|BMASK(3:0) 913 #define MASK_HG_STEP BMASK(11:8)|BMASK(3:0) 914 #define MASK_HB_STEP BMASK(11:8)|BMASK(3:0) 915 #define MASK_VR_INC BMASK(10:8)|BMASK(3:0) 916 #define MASK_VR_INC_SIGNZ GOP_BIT11 917 #define MASK_VG_INC BMASK(10:8)|BMASK(3:0) 918 #define MASK_VG_INC_SIGNZ GOP_BIT11 919 #define MASK_VB_INC BMASK(10:8)|BMASK(3:0) 920 #define MASK_VB_INC_SIGNZ GOP_BIT11 921 #define MASK_VR_STEP BMASK(11:8)|BMASK(3:0) 922 #define MASK_VG_STEP BMASK(11:8)|BMASK(3:0) 923 #define MASK_VB_STEP BMASK(11:8)|BMASK(3:0) 924 925 #define SHIFT_TSTCLR_EN 6 926 #define SHIFT_TSTCLR_ALPHA_EN 1 927 #define SHIFT_TSTCLR_ALPHA 8 928 #define SHIFT_R_STC 0 929 #define SHIFT_G_STC 0 930 #define SHIFT_B_STC 0 931 #define SHIFT_INI_TSTCLR_EN 0 932 #define SHIFT_TSTCLR_HDUP 2 933 #define SHIFT_TSTCLR_VDUP 0 934 #define SHIFT_HR_INC 0 935 #define SHIFT_HR_INC_SIGNZ 11 936 #define SHIFT_HG_INC 0 937 #define SHIFT_HG_INC_SIGNZ 11 938 #define SHIFT_HB_INC 0 939 #define SHIFT_HB_INC_SIGNZ 11 940 #define SHIFT_HR_STEP 0 941 #define SHIFT_HG_STEP 0 942 #define SHIFT_HB_STEP 0 943 #define SHIFT_VR_INC 0 944 #define SHIFT_VR_INC_SIGNZ 11 945 #define SHIFT_VG_INC 0 946 #define SHIFT_VG_INC_SIGNZ 11 947 #define SHIFT_VB_INC 0 948 #define SHIFT_VB_INC_SIGNZ 11 949 #define SHIFT_VR_STEP 0 950 #define SHIFT_VG_STEP 0 951 #define SHIFT_VB_STEP 0 952 953 954 //---------------------------------------------------------------------------- 955 // GOP AFBC Reg 956 //---------------------------------------------------------------------------- 957 #define REG_AFBC_CORE_EN(id) GOP_REG(GOP_4G_OFST+GOP_AFBC_OFST, 0x00+(0x20*id)) 958 #define REG_AFBC_ADDR_L(id) GOP_REG(GOP_4G_OFST+GOP_AFBC_OFST, 0x01+(0x20*id)) 959 #define REG_AFBC_ADDR_H(id) GOP_REG(GOP_4G_OFST+GOP_AFBC_OFST, 0x02+(0x20*id)) 960 #define REG_AFBC_FMT(id) GOP_REG(GOP_4G_OFST+GOP_AFBC_OFST, 0x0C+(0x20*id)) 961 #define REG_AFBC_WIDTH(id) GOP_REG(GOP_4G_OFST+GOP_AFBC_OFST, 0x0A+(0x20*id)) 962 #define REG_AFBC_HEIGHT(id) GOP_REG(GOP_4G_OFST+GOP_AFBC_OFST, 0x0B+(0x20*id)) 963 #define REG_AFBC_RESP(id) GOP_REG(GOP_4G_OFST+GOP_AFBC_OFST, 0x0F+(0x20*id)) 964 #define REG_AFBC_MIU GOP_REG(GOP_4G_OFST+GOP_AFBC_OFST, 0x43) 965 #define REG_AFBC_DEBUG(id) GOP_REG(GOP_4G_OFST+GOP_AFBC_OFST, 0x44+(0x20*id)) 966 #define REG_AFBC_READCNT(id) GOP_REG(GOP_4G_OFST+GOP_AFBC_OFST, 0x4C+(0x20*id)) 967 #define REG_AFBC_TRIGGER GOP_REG(GOP_4G_OFST+GOP_AFBC_OFST, 0x50) 968 969 #endif // _REG_GOP_H_ 970