xref: /utopia/UTPA2-700.0.x/modules/graphic/hal/mooney/gop/regGOP.h (revision 53ee8cc121a030b8d368113ac3e966b4705770ef)
1*53ee8cc1Swenshuai.xi //<MStar Software>
2*53ee8cc1Swenshuai.xi //******************************************************************************
3*53ee8cc1Swenshuai.xi // MStar Software
4*53ee8cc1Swenshuai.xi // Copyright (c) 2010 - 2012 MStar Semiconductor, Inc. All rights reserved.
5*53ee8cc1Swenshuai.xi // All software, firmware and related documentation herein ("MStar Software") are
6*53ee8cc1Swenshuai.xi // intellectual property of MStar Semiconductor, Inc. ("MStar") and protected by
7*53ee8cc1Swenshuai.xi // law, including, but not limited to, copyright law and international treaties.
8*53ee8cc1Swenshuai.xi // Any use, modification, reproduction, retransmission, or republication of all
9*53ee8cc1Swenshuai.xi // or part of MStar Software is expressly prohibited, unless prior written
10*53ee8cc1Swenshuai.xi // permission has been granted by MStar.
11*53ee8cc1Swenshuai.xi //
12*53ee8cc1Swenshuai.xi // By accessing, browsing and/or using MStar Software, you acknowledge that you
13*53ee8cc1Swenshuai.xi // have read, understood, and agree, to be bound by below terms ("Terms") and to
14*53ee8cc1Swenshuai.xi // comply with all applicable laws and regulations:
15*53ee8cc1Swenshuai.xi //
16*53ee8cc1Swenshuai.xi // 1. MStar shall retain any and all right, ownership and interest to MStar
17*53ee8cc1Swenshuai.xi //    Software and any modification/derivatives thereof.
18*53ee8cc1Swenshuai.xi //    No right, ownership, or interest to MStar Software and any
19*53ee8cc1Swenshuai.xi //    modification/derivatives thereof is transferred to you under Terms.
20*53ee8cc1Swenshuai.xi //
21*53ee8cc1Swenshuai.xi // 2. You understand that MStar Software might include, incorporate or be
22*53ee8cc1Swenshuai.xi //    supplied together with third party`s software and the use of MStar
23*53ee8cc1Swenshuai.xi //    Software may require additional licenses from third parties.
24*53ee8cc1Swenshuai.xi //    Therefore, you hereby agree it is your sole responsibility to separately
25*53ee8cc1Swenshuai.xi //    obtain any and all third party right and license necessary for your use of
26*53ee8cc1Swenshuai.xi //    such third party`s software.
27*53ee8cc1Swenshuai.xi //
28*53ee8cc1Swenshuai.xi // 3. MStar Software and any modification/derivatives thereof shall be deemed as
29*53ee8cc1Swenshuai.xi //    MStar`s confidential information and you agree to keep MStar`s
30*53ee8cc1Swenshuai.xi //    confidential information in strictest confidence and not disclose to any
31*53ee8cc1Swenshuai.xi //    third party.
32*53ee8cc1Swenshuai.xi //
33*53ee8cc1Swenshuai.xi // 4. MStar Software is provided on an "AS IS" basis without warranties of any
34*53ee8cc1Swenshuai.xi //    kind. Any warranties are hereby expressly disclaimed by MStar, including
35*53ee8cc1Swenshuai.xi //    without limitation, any warranties of merchantability, non-infringement of
36*53ee8cc1Swenshuai.xi //    intellectual property rights, fitness for a particular purpose, error free
37*53ee8cc1Swenshuai.xi //    and in conformity with any international standard.  You agree to waive any
38*53ee8cc1Swenshuai.xi //    claim against MStar for any loss, damage, cost or expense that you may
39*53ee8cc1Swenshuai.xi //    incur related to your use of MStar Software.
40*53ee8cc1Swenshuai.xi //    In no event shall MStar be liable for any direct, indirect, incidental or
41*53ee8cc1Swenshuai.xi //    consequential damages, including without limitation, lost of profit or
42*53ee8cc1Swenshuai.xi //    revenues, lost or damage of data, and unauthorized system use.
43*53ee8cc1Swenshuai.xi //    You agree that this Section 4 shall still apply without being affected
44*53ee8cc1Swenshuai.xi //    even if MStar Software has been modified by MStar in accordance with your
45*53ee8cc1Swenshuai.xi //    request or instruction for your use, except otherwise agreed by both
46*53ee8cc1Swenshuai.xi //    parties in writing.
47*53ee8cc1Swenshuai.xi //
48*53ee8cc1Swenshuai.xi // 5. If requested, MStar may from time to time provide technical supports or
49*53ee8cc1Swenshuai.xi //    services in relation with MStar Software to you for your use of
50*53ee8cc1Swenshuai.xi //    MStar Software in conjunction with your or your customer`s product
51*53ee8cc1Swenshuai.xi //    ("Services").
52*53ee8cc1Swenshuai.xi //    You understand and agree that, except otherwise agreed by both parties in
53*53ee8cc1Swenshuai.xi //    writing, Services are provided on an "AS IS" basis and the warranty
54*53ee8cc1Swenshuai.xi //    disclaimer set forth in Section 4 above shall apply.
55*53ee8cc1Swenshuai.xi //
56*53ee8cc1Swenshuai.xi // 6. Nothing contained herein shall be construed as by implication, estoppels
57*53ee8cc1Swenshuai.xi //    or otherwise:
58*53ee8cc1Swenshuai.xi //    (a) conferring any license or right to use MStar name, trademark, service
59*53ee8cc1Swenshuai.xi //        mark, symbol or any other identification;
60*53ee8cc1Swenshuai.xi //    (b) obligating MStar or any of its affiliates to furnish any person,
61*53ee8cc1Swenshuai.xi //        including without limitation, you and your customers, any assistance
62*53ee8cc1Swenshuai.xi //        of any kind whatsoever, or any information; or
63*53ee8cc1Swenshuai.xi //    (c) conferring any license or right under any intellectual property right.
64*53ee8cc1Swenshuai.xi //
65*53ee8cc1Swenshuai.xi // 7. These terms shall be governed by and construed in accordance with the laws
66*53ee8cc1Swenshuai.xi //    of Taiwan, R.O.C., excluding its conflict of law rules.
67*53ee8cc1Swenshuai.xi //    Any and all dispute arising out hereof or related hereto shall be finally
68*53ee8cc1Swenshuai.xi //    settled by arbitration referred to the Chinese Arbitration Association,
69*53ee8cc1Swenshuai.xi //    Taipei in accordance with the ROC Arbitration Law and the Arbitration
70*53ee8cc1Swenshuai.xi //    Rules of the Association by three (3) arbitrators appointed in accordance
71*53ee8cc1Swenshuai.xi //    with the said Rules.
72*53ee8cc1Swenshuai.xi //    The place of arbitration shall be in Taipei, Taiwan and the language shall
73*53ee8cc1Swenshuai.xi //    be English.
74*53ee8cc1Swenshuai.xi //    The arbitration award shall be final and binding to both parties.
75*53ee8cc1Swenshuai.xi //
76*53ee8cc1Swenshuai.xi //******************************************************************************
77*53ee8cc1Swenshuai.xi //<MStar Software>
78*53ee8cc1Swenshuai.xi ////////////////////////////////////////////////////////////////////////////////
79*53ee8cc1Swenshuai.xi //
80*53ee8cc1Swenshuai.xi // Copyright (c) 2008-2009 MStar Semiconductor, Inc.
81*53ee8cc1Swenshuai.xi // All rights reserved.
82*53ee8cc1Swenshuai.xi //
83*53ee8cc1Swenshuai.xi // Unless otherwise stipulated in writing, any and all information contained
84*53ee8cc1Swenshuai.xi // herein regardless in any format shall remain the sole proprietary of
85*53ee8cc1Swenshuai.xi // MStar Semiconductor Inc. and be kept in strict confidence
86*53ee8cc1Swenshuai.xi // ("MStar Confidential Information") by the recipient.
87*53ee8cc1Swenshuai.xi // Any unauthorized act including without limitation unauthorized disclosure,
88*53ee8cc1Swenshuai.xi // copying, use, reproduction, sale, distribution, modification, disassembling,
89*53ee8cc1Swenshuai.xi // reverse engineering and compiling of the contents of MStar Confidential
90*53ee8cc1Swenshuai.xi // Information is unlawful and strictly prohibited. MStar hereby reserves the
91*53ee8cc1Swenshuai.xi // rights to any and all damages, losses, costs and expenses resulting therefrom.
92*53ee8cc1Swenshuai.xi //
93*53ee8cc1Swenshuai.xi ////////////////////////////////////////////////////////////////////////////////
94*53ee8cc1Swenshuai.xi 
95*53ee8cc1Swenshuai.xi #ifndef _REG_GOP_H_
96*53ee8cc1Swenshuai.xi #define _REG_GOP_H_
97*53ee8cc1Swenshuai.xi 
98*53ee8cc1Swenshuai.xi //-------------------------------------------------------------------------------------------------
99*53ee8cc1Swenshuai.xi //  Hardware Capability
100*53ee8cc1Swenshuai.xi //-------------------------------------------------------------------------------------------------
101*53ee8cc1Swenshuai.xi 
102*53ee8cc1Swenshuai.xi 
103*53ee8cc1Swenshuai.xi //-------------------------------------------------------------------------------------------------
104*53ee8cc1Swenshuai.xi //  Macro and Define
105*53ee8cc1Swenshuai.xi //-------------------------------------------------------------------------------------------------
106*53ee8cc1Swenshuai.xi //----------------------------------------------------------------------------
107*53ee8cc1Swenshuai.xi // HW IP Reg Base Adr
108*53ee8cc1Swenshuai.xi //----------------------------------------------------------------------------
109*53ee8cc1Swenshuai.xi #define GOP_REG_BASE                           0x1F00UL
110*53ee8cc1Swenshuai.xi #define GE_REG_BASE                            0x2800UL
111*53ee8cc1Swenshuai.xi #define SC1_REG_BASE                           0x2F00UL
112*53ee8cc1Swenshuai.xi #define CKG_REG_BASE                           0x0B00UL
113*53ee8cc1Swenshuai.xi #define MIU0_REG_BASE                          0x0600UL
114*53ee8cc1Swenshuai.xi #define MIU_REG_BASE                           0x1200UL
115*53ee8cc1Swenshuai.xi #define MIU2_REG_BASE                          0x162000
116*53ee8cc1Swenshuai.xi #define MVOP_REG_BASE                          0x1400UL
117*53ee8cc1Swenshuai.xi #define SC1_DIRREG_BASE                        0x130000UL
118*53ee8cc1Swenshuai.xi 
119*53ee8cc1Swenshuai.xi //----------------------------------------------------------------------------
120*53ee8cc1Swenshuai.xi // Scaler Reg
121*53ee8cc1Swenshuai.xi //----------------------------------------------------------------------------
122*53ee8cc1Swenshuai.xi #define XC_REG(bk, reg)                        (SC1_REG_BASE+((MS_U32)(bk)<<16) + (reg) * 2)
123*53ee8cc1Swenshuai.xi 
124*53ee8cc1Swenshuai.xi #define REG_SC_BK00_00_L                        XC_REG(0x00, 0x00)
125*53ee8cc1Swenshuai.xi #define REG_SC_BK00_05_L                        XC_REG(0x00, 0x05)
126*53ee8cc1Swenshuai.xi #define REG_SC_BK00_06_L                        XC_REG(0x00, 0x06)
127*53ee8cc1Swenshuai.xi #define REG_SC_BK01_02_L                        XC_REG(0x01, 0x02)
128*53ee8cc1Swenshuai.xi #define REG_SC_BK02_5F_L                        XC_REG(0x02, 0x5F)
129*53ee8cc1Swenshuai.xi #define REG_SC_BK0F_2B_L                        XC_REG(0x0F, 0x2B)
130*53ee8cc1Swenshuai.xi #define REG_SC_BK10_23_L                        XC_REG(0x10, 0x23)
131*53ee8cc1Swenshuai.xi #define REG_SC_BK10_5B_L                        XC_REG(0x10, 0x5B)
132*53ee8cc1Swenshuai.xi #define REG_SC_BK12_03_L                        XC_REG(0x12, 0x03)
133*53ee8cc1Swenshuai.xi #define REG_SC_BK37_22_L                        XC_REG(0x37, 0x22)
134*53ee8cc1Swenshuai.xi #define REG_SC_BK37_24_L                        XC_REG(0x37, 0x24)
135*53ee8cc1Swenshuai.xi #define REG_SC_BK37_28_L                        XC_REG(0x37, 0x28)
136*53ee8cc1Swenshuai.xi #define REG_SC_BK3D_0D_L                        XC_REG(0x3D, 0x0D)
137*53ee8cc1Swenshuai.xi #define REG_SC_BK40_22_L                        XC_REG(0x40, 0x22)
138*53ee8cc1Swenshuai.xi #define REG_SC_BK40_23_L                        XC_REG(0x40, 0x23)
139*53ee8cc1Swenshuai.xi #define REG_SC_BK40_24_L                        XC_REG(0x40, 0x24)
140*53ee8cc1Swenshuai.xi #define REG_SC_BK40_25_L                        XC_REG(0x40, 0x25)
141*53ee8cc1Swenshuai.xi #define REG_SC_BK7F_10_L                        XC_REG(0x7F, 0x10)
142*53ee8cc1Swenshuai.xi 
143*53ee8cc1Swenshuai.xi #define GOP_SC_BANKSEL                          REG_SC_BK00_00_L
144*53ee8cc1Swenshuai.xi #define GOP_SC_CHANNELSYNC                      REG_SC_BK00_05_L
145*53ee8cc1Swenshuai.xi #define GOP_SC_GOPEN                            REG_SC_BK00_06_L
146*53ee8cc1Swenshuai.xi #define GOP_SC_IP_SYNC                          REG_SC_BK01_02_L
147*53ee8cc1Swenshuai.xi #define GOP_SC_IP2GOP_SRCSEL                    REG_SC_BK02_5F_L
148*53ee8cc1Swenshuai.xi #define GOP_SC_OSD_CHECK_ALPHA                  REG_SC_BK0F_2B_L
149*53ee8cc1Swenshuai.xi #define GOP_SC_VOPNBL                           REG_SC_BK10_23_L
150*53ee8cc1Swenshuai.xi #define GOP_SC_GOPENMODE1                       REG_SC_BK10_5B_L
151*53ee8cc1Swenshuai.xi #define GOP_SC_MIRRORCFG                        REG_SC_BK12_03_L
152*53ee8cc1Swenshuai.xi #define GOP_SC_OCMIXER                          REG_SC_BK37_22_L
153*53ee8cc1Swenshuai.xi #define GOP_SC_OCMISC                           REG_SC_BK37_24_L
154*53ee8cc1Swenshuai.xi #define GOP_SC_OCALPHA                          REG_SC_BK37_28_L
155*53ee8cc1Swenshuai.xi #define GOP_SC_GOPSC_SRAM_CTRL                  REG_SC_BK3D_0D_L
156*53ee8cc1Swenshuai.xi #define GOP_SC_FRC_LAYER1_L_EN                  REG_SC_BK40_22_L
157*53ee8cc1Swenshuai.xi #define GOP_SC_FRC_LAYER1_R_EN                  REG_SC_BK40_23_L
158*53ee8cc1Swenshuai.xi #define GOP_SC_FRC_LAYER2_L_EN                  REG_SC_BK40_24_L
159*53ee8cc1Swenshuai.xi #define GOP_SC_FRC_LAYER2_R_EN                  REG_SC_BK40_25_L
160*53ee8cc1Swenshuai.xi #define GOP_SC_MIU_SEL                          REG_SC_BK7F_10_L
161*53ee8cc1Swenshuai.xi 
162*53ee8cc1Swenshuai.xi //----------------------------------------------------------------------------
163*53ee8cc1Swenshuai.xi // MVOP Reg
164*53ee8cc1Swenshuai.xi //----------------------------------------------------------------------------
165*53ee8cc1Swenshuai.xi #define GOP_MVOP_MIRRORCFG                      (MVOP_REG_BASE+(0x3B*2))
166*53ee8cc1Swenshuai.xi 
167*53ee8cc1Swenshuai.xi 
168*53ee8cc1Swenshuai.xi //----------------------------------------------------------------------------
169*53ee8cc1Swenshuai.xi // GE Reg
170*53ee8cc1Swenshuai.xi //----------------------------------------------------------------------------
171*53ee8cc1Swenshuai.xi #define GOP_GE_FMT_BLT                          (GE_REG_BASE+(0x01*2))
172*53ee8cc1Swenshuai.xi #define GOP_GE_EN_CMDQ                          BIT(0)
173*53ee8cc1Swenshuai.xi #define GOP_GE_EN_VCMDQ                         BIT(1)
174*53ee8cc1Swenshuai.xi 
175*53ee8cc1Swenshuai.xi #define GOP_GE_VQ_FIFO_STATUS_L                 (GE_REG_BASE+(0x04*2))
176*53ee8cc1Swenshuai.xi #define GOP_GE_VQ_FIFO_STATUS_H                 (GE_REG_BASE+(0x05*2))
177*53ee8cc1Swenshuai.xi 
178*53ee8cc1Swenshuai.xi #define GOP_GE_STATUS                           (GE_REG_BASE+(0x07*2))
179*53ee8cc1Swenshuai.xi #define GOP_GE_BUSY                             BIT(0)
180*53ee8cc1Swenshuai.xi #define GOP_GE_CMDQ1_STATUS                     BMASK(7:3)
181*53ee8cc1Swenshuai.xi #define GOP_GE_CMDQ2_STATUS                     BMASK(15:11)
182*53ee8cc1Swenshuai.xi 
183*53ee8cc1Swenshuai.xi #define GOP_GE_TAG                              (GE_REG_BASE+(0x2C*2))
184*53ee8cc1Swenshuai.xi 
185*53ee8cc1Swenshuai.xi #define GOP_GE_DBBASE0                          (GE_REG_BASE+(0x26*2))
186*53ee8cc1Swenshuai.xi #define GOP_GE_DBBASE1                          (GE_REG_BASE+(0x27*2))
187*53ee8cc1Swenshuai.xi #define GOP_GE_DBPIT                            (GE_REG_BASE+(0x33*2))
188*53ee8cc1Swenshuai.xi #define GOP_GE_FBFMT                            (GE_REG_BASE+(0x34*2))
189*53ee8cc1Swenshuai.xi #define GOP_GE_SRCW                             (GE_REG_BASE+(0x6e*2))
190*53ee8cc1Swenshuai.xi #define GOP_GE_SRCH                             (GE_REG_BASE+(0x6f*2))
191*53ee8cc1Swenshuai.xi 
192*53ee8cc1Swenshuai.xi 
193*53ee8cc1Swenshuai.xi //----------------------------------------------------------------------------
194*53ee8cc1Swenshuai.xi // ChipTop Reg
195*53ee8cc1Swenshuai.xi //----------------------------------------------------------------------------
196*53ee8cc1Swenshuai.xi /* GOP0 and GOP1 CLK */
197*53ee8cc1Swenshuai.xi #define GOP_GOPCLK              (CKG_REG_BASE+(0x40<<1))
198*53ee8cc1Swenshuai.xi #define CKG_GOPG0_DISABLE_CLK   ~(GOP_BIT0)
199*53ee8cc1Swenshuai.xi #define CKG_GOPG0_ODCLK         (0 << 2)
200*53ee8cc1Swenshuai.xi #define CKG_GOPG0_IDCLK2        (1 << 2)
201*53ee8cc1Swenshuai.xi #define CKG_GOPG0_IDCLK1        (2 << 2)
202*53ee8cc1Swenshuai.xi #define CKG_GOPG0_OCC_FRCCLK    (3 << 2)
203*53ee8cc1Swenshuai.xi #define CKG_GOPG0_FCLK          (8 << 2)
204*53ee8cc1Swenshuai.xi #define CKG_GOPG0_DISABLE_CLK_MASK    (GOP_BIT0)
205*53ee8cc1Swenshuai.xi #define CKG_GOPG0_MASK          (GOP_BIT5 | GOP_BIT4 | GOP_BIT3 | GOP_BIT2)
206*53ee8cc1Swenshuai.xi 
207*53ee8cc1Swenshuai.xi #define CKG_GOPG1_DISABLE_CLK   ~(GOP_BIT8)
208*53ee8cc1Swenshuai.xi #define CKG_GOPG1_ODCLK         (0 << 10)
209*53ee8cc1Swenshuai.xi #define CKG_GOPG1_IDCLK2        (1 << 10)
210*53ee8cc1Swenshuai.xi #define CKG_GOPG1_IDCLK1        (2 << 10)
211*53ee8cc1Swenshuai.xi #define CKG_GOPG1_OCC_FRCCLK    (3 << 10)
212*53ee8cc1Swenshuai.xi #define CKG_GOPG1_FCLK          (8 << 10)
213*53ee8cc1Swenshuai.xi #define CKG_GOPG1_DISABLE_CLK_MASK    (GOP_BIT8)
214*53ee8cc1Swenshuai.xi #define CKG_GOPG1_MASK          (GOP_BIT13 | GOP_BIT12 | GOP_BIT11 | GOP_BIT10)
215*53ee8cc1Swenshuai.xi 
216*53ee8cc1Swenshuai.xi #define CKG_GOPG0_SCALING       (CKG_REG_BASE+0x88)
217*53ee8cc1Swenshuai.xi #define CKG_GOPG0_MG            (CKG_REG_BASE+0xFE)
218*53ee8cc1Swenshuai.xi #define CKG_GOPG0_MG_MASK       (GOP_BIT3 | GOP_BIT2)
219*53ee8cc1Swenshuai.xi #define CKG_GOPG2_MG_MASK       (GOP_BIT7 | GOP_BIT6)
220*53ee8cc1Swenshuai.xi 
221*53ee8cc1Swenshuai.xi /* GOP2 and GOPDWIN CLK */
222*53ee8cc1Swenshuai.xi #define GOP_GOP2CLK             (CKG_REG_BASE+(0x41<<1))
223*53ee8cc1Swenshuai.xi #define CKG_GOPG2_DISABLE_CLK   ~(GOP_BIT0)
224*53ee8cc1Swenshuai.xi #define CKG_GOPG2_ODCLK         (0<<2)
225*53ee8cc1Swenshuai.xi #define CKG_GOPG2_IDCLK2        (1 << 2)
226*53ee8cc1Swenshuai.xi #define CKG_GOPG2_IDCLK1        (2 << 2)
227*53ee8cc1Swenshuai.xi #define CKG_GOPG2_OCC_FRCCLK    (3 << 2)
228*53ee8cc1Swenshuai.xi #define CKG_GOPG2_FCLK          (8 << 2)
229*53ee8cc1Swenshuai.xi #define CKG_GOPG2_DISABLE_CLK_MASK    (GOP_BIT0)
230*53ee8cc1Swenshuai.xi #define CKG_GOPG2_MASK           (GOP_BIT5 |GOP_BIT4 | GOP_BIT3 | GOP_BIT2)
231*53ee8cc1Swenshuai.xi 
232*53ee8cc1Swenshuai.xi #define CKG_GOPD_CLK_IDCLK2      (0 << 10)
233*53ee8cc1Swenshuai.xi #define CKG_GOPD_CLK_ODCLK       (1 << 10)
234*53ee8cc1Swenshuai.xi #define CKG_GOPD_CLK_DC0CLK      (2 << 10)
235*53ee8cc1Swenshuai.xi #define CKG_GOPD_CLK_SUBDC0CLK   (3 << 10)
236*53ee8cc1Swenshuai.xi #define CKG_GOPD_MASK            (GOP_BIT12 | GOP_BIT11 | GOP_BIT10)
237*53ee8cc1Swenshuai.xi 
238*53ee8cc1Swenshuai.xi 
239*53ee8cc1Swenshuai.xi /* GOP3 CLK*/
240*53ee8cc1Swenshuai.xi #define GOP_GOP3CLK             (CKG_REG_BASE+(0x42<<1))
241*53ee8cc1Swenshuai.xi #define CKG_GOPG3_ODCLK         (0<<2)
242*53ee8cc1Swenshuai.xi #define CKG_GOPG3_IDCLK2        (1 << 2)
243*53ee8cc1Swenshuai.xi #define CKG_GOPG3_IDCLK1        (2 << 2)
244*53ee8cc1Swenshuai.xi #define CKG_GOPG3_OCC_FRCCLK    (3 << 2)
245*53ee8cc1Swenshuai.xi #define CKG_GOPG3_FCLK          (8 << 2)
246*53ee8cc1Swenshuai.xi #define CKG_GOPG3_DISABLE_CLK_MASK    (GOP_BIT0)
247*53ee8cc1Swenshuai.xi #define CKG_GOPG3_MASK          (GOP_BIT5 | GOP_BIT4 | GOP_BIT3 | GOP_BIT2)
248*53ee8cc1Swenshuai.xi #define CKG_GOPD_DISABLE_CLK   ~(GOP_BIT8)
249*53ee8cc1Swenshuai.xi 
250*53ee8cc1Swenshuai.xi 
251*53ee8cc1Swenshuai.xi /* GOP4 CLK*/
252*53ee8cc1Swenshuai.xi #define GOP_GOP4CLK             (CKG_REG_BASE+(0x7E<<1))
253*53ee8cc1Swenshuai.xi #define CKG_GOPG4_ODCLK         (0 << 10)
254*53ee8cc1Swenshuai.xi #define CKG_GOPG4_IDCLK2        (1 << 10)
255*53ee8cc1Swenshuai.xi #define CKG_GOPG4_IDCLK1        (2 << 10)
256*53ee8cc1Swenshuai.xi #define CKG_GOPG4_OCC_FRCCLK    (3 << 10)
257*53ee8cc1Swenshuai.xi #define CKG_GOPG4_FCLK          (8 << 10)
258*53ee8cc1Swenshuai.xi #define CKG_GOPG4_DISABLE_CLK_MASK    (GOP_BIT8)
259*53ee8cc1Swenshuai.xi #define CKG_GOPG4_MASK          (GOP_BIT13 |GOP_BIT12 | GOP_BIT11 | GOP_BIT10)
260*53ee8cc1Swenshuai.xi 
261*53ee8cc1Swenshuai.xi 
262*53ee8cc1Swenshuai.xi /* SRAM CLK */
263*53ee8cc1Swenshuai.xi #define GOP_SRAMCLK             (CKG_REG_BASE+(0x43<<1))
264*53ee8cc1Swenshuai.xi #define CKG_SRAM0_DISABLE_CLK   (GOP_BIT0)
265*53ee8cc1Swenshuai.xi #define CKG_SRAM1_DISABLE_CLK   (GOP_BIT8)
266*53ee8cc1Swenshuai.xi #define CKG_SRAM0_MASK          (GOP_BIT0|GOP_BIT1)
267*53ee8cc1Swenshuai.xi #define CKG_SRAM1_MASK          (GOP_BIT8|GOP_BIT9)
268*53ee8cc1Swenshuai.xi 
269*53ee8cc1Swenshuai.xi /* LINE BUFFER SRAM CLK */
270*53ee8cc1Swenshuai.xi #define GOP_LB_SRAMCLK            (CKG_REG_BASE+(0x45<<1))
271*53ee8cc1Swenshuai.xi #define CKG_LB_SRAM1_DISABLE_CLK   (GOP_BIT0)                   /*GOP1*/
272*53ee8cc1Swenshuai.xi #define CKG_LB_SRAM2_DISABLE_CLK   (GOP_BIT4)                   /*GOP2*/
273*53ee8cc1Swenshuai.xi #define CKG_LB_SRAM1_MASK          (GOP_BIT2|GOP_BIT3)
274*53ee8cc1Swenshuai.xi #define CKG_LB_SRAM2_MASK          (GOP_BIT6|GOP_BIT7)
275*53ee8cc1Swenshuai.xi //----------------------------------------------------------------------------
276*53ee8cc1Swenshuai.xi // MIU Reg
277*53ee8cc1Swenshuai.xi //----------------------------------------------------------------------------
278*53ee8cc1Swenshuai.xi #define GOP_CLIENT_REG          0x7D
279*53ee8cc1Swenshuai.xi #define GOP_MIU_GROUP           (MIU0_REG_BASE+(GOP_CLIENT_REG*2))
280*53ee8cc1Swenshuai.xi #define GOP_MIU_GROUP1          (MIU_REG_BASE+(GOP_CLIENT_REG*2))
281*53ee8cc1Swenshuai.xi 
282*53ee8cc1Swenshuai.xi /*Define each gop miu clint bit*/
283*53ee8cc1Swenshuai.xi #define GOP_MIU_CLIENT_DWIN     0xFF
284*53ee8cc1Swenshuai.xi #define GOP_MIU_CLIENT_GOP0     0x5
285*53ee8cc1Swenshuai.xi #define GOP_MIU_CLIENT_GOP1     0x6
286*53ee8cc1Swenshuai.xi #define GOP_MIU_CLIENT_GOP2     0x7
287*53ee8cc1Swenshuai.xi #define GOP_MIU_CLIENT_GOP3     0xFF
288*53ee8cc1Swenshuai.xi #define GOP_MIU_CLIENT_GOP4     0xFF
289*53ee8cc1Swenshuai.xi #define GOP_MIU_CLIENT_GOP5     0xFF
290*53ee8cc1Swenshuai.xi 
291*53ee8cc1Swenshuai.xi //----------------------------------------------------------------------------
292*53ee8cc1Swenshuai.xi // VE Reg
293*53ee8cc1Swenshuai.xi //----------------------------------------------------------------------------
294*53ee8cc1Swenshuai.xi #define GOP_VE_TVS_OSD_EN           0x60
295*53ee8cc1Swenshuai.xi #define GOP_VE_TVS_OSD1_EN          0x61
296*53ee8cc1Swenshuai.xi 
297*53ee8cc1Swenshuai.xi //----------------------------------------------------------------------------
298*53ee8cc1Swenshuai.xi // GOP Reg
299*53ee8cc1Swenshuai.xi //----------------------------------------------------------------------------
300*53ee8cc1Swenshuai.xi #define GOP_REG(bk, reg)                     (GOP_REG_BASE+((MS_U32)(bk)<<16) + (reg) * 2)
301*53ee8cc1Swenshuai.xi #define __GOP_REG(reg)                       (GOP_REG_BASE+(reg) * 2)
302*53ee8cc1Swenshuai.xi #define GOP_REG_DIRECT_BASE                  (0x120200)
303*53ee8cc1Swenshuai.xi #define GOP_REG_GOP4_BK_OFFSET               0x1900
304*53ee8cc1Swenshuai.xi #define GOP_REG_GOP4_GW_OFFSET               0x1C00
305*53ee8cc1Swenshuai.xi #define GOP_REG_GOP4_ST_OFFSET               0x1D00
306*53ee8cc1Swenshuai.xi 
307*53ee8cc1Swenshuai.xi #define GOP_REG_VAL(x)                       (1<<x)
308*53ee8cc1Swenshuai.xi 
309*53ee8cc1Swenshuai.xi //MUX Setting
310*53ee8cc1Swenshuai.xi #define GOP_MUX_SHIFT                       0x3
311*53ee8cc1Swenshuai.xi #define GOP_REGMUX_MASK                     BMASK((GOP_MUX_SHIFT-1):0)
312*53ee8cc1Swenshuai.xi #define GOP_MUX0_MASK                       (GOP_REGMUX_MASK<<(GOP_MUX_SHIFT*0))
313*53ee8cc1Swenshuai.xi #define GOP_MUX1_MASK                       (GOP_REGMUX_MASK<<(GOP_MUX_SHIFT*1))
314*53ee8cc1Swenshuai.xi #define GOP_MUX2_MASK                       (GOP_REGMUX_MASK<<(GOP_MUX_SHIFT*2))
315*53ee8cc1Swenshuai.xi #define GOP_MUX3_MASK                       (GOP_REGMUX_MASK<<(GOP_MUX_SHIFT*3))
316*53ee8cc1Swenshuai.xi #define GOP_MUX4_MASK                       (GOP_REGMUX_MASK<<(GOP_MUX_SHIFT*4))
317*53ee8cc1Swenshuai.xi 
318*53ee8cc1Swenshuai.xi //IP and VOP MUX Setting
319*53ee8cc1Swenshuai.xi #define GOP_IP_MAIN_MUX_SHIFT                 0
320*53ee8cc1Swenshuai.xi #define GOP_IP_MAIN_MUX_MASK                 (BMASK((GOP_MUX_SHIFT-1):0))<<GOP_IP_MAIN_MUX_SHIFT
321*53ee8cc1Swenshuai.xi #define GOP_IP_SUB_MUX_SHIFT                  3
322*53ee8cc1Swenshuai.xi #define GOP_IP_SUB_MUX_MASK                  (BMASK((GOP_MUX_SHIFT-1):0))<<GOP_IP_SUB_MUX_SHIFT
323*53ee8cc1Swenshuai.xi #define GOP_IP_VOP0_MUX_SHIFT                 6
324*53ee8cc1Swenshuai.xi #define GOP_IP_VOP0_MUX_MASK                 (BMASK((GOP_MUX_SHIFT-1):0))<<GOP_IP_VOP0_MUX_SHIFT
325*53ee8cc1Swenshuai.xi #define GOP_IP_VOP1_MUX_SHIFT                 9
326*53ee8cc1Swenshuai.xi #define GOP_IP_VOP1_MUX_MASK                 (BMASK((GOP_MUX_SHIFT-1):0))<<GOP_IP_VOP1_MUX_SHIFT
327*53ee8cc1Swenshuai.xi 
328*53ee8cc1Swenshuai.xi 
329*53ee8cc1Swenshuai.xi //IP and VOP MUX Setting
330*53ee8cc1Swenshuai.xi #define GOP_Mix_MUX0_SHIFT                    0
331*53ee8cc1Swenshuai.xi #define GOP_Mix_MUX0_MASK                    (BMASK((GOP_MUX_SHIFT-1):0))<<GOP_Mix_MUX0_SHIFT
332*53ee8cc1Swenshuai.xi #define GOP_Mix_MUX1_SHIFT                    3
333*53ee8cc1Swenshuai.xi #define GOP_Mix_MUX1_MASK                    (BMASK((GOP_MUX_SHIFT-1):0))<<GOP_Mix_MUX1_SHIFT
334*53ee8cc1Swenshuai.xi #define GOP_VE0_MUX_SHIFT                     6
335*53ee8cc1Swenshuai.xi #define GOP_VE0_MUX_MASK                     (BMASK((GOP_MUX_SHIFT-1):0))<<GOP_VE0_MUX_SHIFT
336*53ee8cc1Swenshuai.xi #define GOP_VE1_MUX_SHIFT                     9
337*53ee8cc1Swenshuai.xi #define GOP_VE1_MUX_MASK                     (BMASK((GOP_MUX_SHIFT-1):0))<<GOP_VE1_MUX_SHIFT
338*53ee8cc1Swenshuai.xi 
339*53ee8cc1Swenshuai.xi 
340*53ee8cc1Swenshuai.xi //4k2k FRC MUX Setting
341*53ee8cc1Swenshuai.xi #define GOP_FRC_MUX_SHIFT                     0x3
342*53ee8cc1Swenshuai.xi #define GOP_FRC_REGMUX_MASK                   BMASK((GOP_MUX_SHIFT-1):0)
343*53ee8cc1Swenshuai.xi #define GOP_FRC_MUX0_MASK                     (GOP_REGMUX_MASK<<(GOP_MUX_SHIFT*0))
344*53ee8cc1Swenshuai.xi #define GOP_FRC_MUX1_MASK                     (GOP_REGMUX_MASK<<(GOP_MUX_SHIFT*1))
345*53ee8cc1Swenshuai.xi #define GOP_FRC_MUX2_MASK                     (GOP_REGMUX_MASK<<(GOP_MUX_SHIFT*2))
346*53ee8cc1Swenshuai.xi #define GOP_FRC_MUX3_MASK                     (GOP_REGMUX_MASK<<(GOP_MUX_SHIFT*3))
347*53ee8cc1Swenshuai.xi 
348*53ee8cc1Swenshuai.xi //DIP Setting
349*53ee8cc1Swenshuai.xi #define GOP_DIP_MUX_SHIFT                     12
350*53ee8cc1Swenshuai.xi #define GOP_DIP_MUX_MASK                     (BMASK((GOP_MUX_SHIFT-1):0))<<GOP_DIP_MUX_SHIFT
351*53ee8cc1Swenshuai.xi 
352*53ee8cc1Swenshuai.xi #define GOP_BANK_OFFSET                       0x3
353*53ee8cc1Swenshuai.xi #define GOP_4G_OFST                           0x0
354*53ee8cc1Swenshuai.xi #define GOP_2G_OFST                           (0x1*GOP_BANK_OFFSET)
355*53ee8cc1Swenshuai.xi #define GOP_1G_OFST                           (0x2*GOP_BANK_OFFSET)
356*53ee8cc1Swenshuai.xi #define GOP_1GX_OFST                          (0x3*GOP_BANK_OFFSET)
357*53ee8cc1Swenshuai.xi #define GOP_DW_OFST                           (0x4*GOP_BANK_OFFSET)
358*53ee8cc1Swenshuai.xi #define GOP_1GS0_OFST                         0xE
359*53ee8cc1Swenshuai.xi #define GOP_1GS1_OFST                         0x11
360*53ee8cc1Swenshuai.xi 
361*53ee8cc1Swenshuai.xi #define GOP_OFFSET_WR                       8
362*53ee8cc1Swenshuai.xi #define GOP_VAL_WR                          GOP_REG_VAL(GOP_OFFSET_WR)
363*53ee8cc1Swenshuai.xi #define GOP_OFFSET_FWR                      9
364*53ee8cc1Swenshuai.xi #define GOP_VAL_FWR                         GOP_REG_VAL(GOP_OFFSET_FWR)
365*53ee8cc1Swenshuai.xi #define GOP_OFFSET_FCLR                     11
366*53ee8cc1Swenshuai.xi #define GOP_VAL_FCL                         GOP_REG_VAL(GOP_OFFSET_FCLR)
367*53ee8cc1Swenshuai.xi #define GOP4G_OFFSET_WR_ACK                 12
368*53ee8cc1Swenshuai.xi #define GOP4G_VAL_WR_ACK                    GOP_REG_VAL(GOP4G_OFFSET_WR_ACK)
369*53ee8cc1Swenshuai.xi #define GOP2G_OFFSET_WR_ACK                 13
370*53ee8cc1Swenshuai.xi #define GOP2G_VAL_WR_ACK                    GOP_REG_VAL(GOP2G_OFFSET_WR_ACK)
371*53ee8cc1Swenshuai.xi #define GOPD_OFFSET_WR_ACK                  14
372*53ee8cc1Swenshuai.xi #define GOPD_VAL_WR_ACK                     GOP_REG_VAL(GOPD_OFFSET_WR_ACK)
373*53ee8cc1Swenshuai.xi #define GOP1G_OFFSET_WR_ACK                 15
374*53ee8cc1Swenshuai.xi #define GOP1G_VAL_WR_ACK                    GOP_REG_VAL(GOPD_OFFSET_WR_ACK)
375*53ee8cc1Swenshuai.xi #define GOP_VAL_ACK(x)                      GOP_REG_VAL(GOP4G_OFFSET_WR_ACK+x)
376*53ee8cc1Swenshuai.xi 
377*53ee8cc1Swenshuai.xi #define GOP_4G_CTRL0                        GOP_REG(GOP_4G_OFST, 0x00)
378*53ee8cc1Swenshuai.xi #define GOP_4G_CTRL1                        GOP_REG(GOP_4G_OFST, 0x01)
379*53ee8cc1Swenshuai.xi #define GOP_4G_RATE                         GOP_REG(GOP_4G_OFST, 0x02)
380*53ee8cc1Swenshuai.xi #define GOP_4G_PALDATA_L                    GOP_REG(GOP_4G_OFST, 0x03)
381*53ee8cc1Swenshuai.xi #define GOP_4G_PALDATA_H                    GOP_REG(GOP_4G_OFST, 0x04)
382*53ee8cc1Swenshuai.xi #define GOP_4G_PALCTRL                      GOP_REG(GOP_4G_OFST, 0x05)
383*53ee8cc1Swenshuai.xi #define GOP_4G_REGDMA_END                   GOP_REG(GOP_4G_OFST, 0x06)
384*53ee8cc1Swenshuai.xi #define GOP_4G_REGDMA_STR                   GOP_REG(GOP_4G_OFST, 0x07)
385*53ee8cc1Swenshuai.xi #define GOP_4G_INT                          GOP_REG(GOP_4G_OFST, 0x08)
386*53ee8cc1Swenshuai.xi #define GOP_4G_HWSTATE                      GOP_REG(GOP_4G_OFST, 0x09)
387*53ee8cc1Swenshuai.xi #define GOP_4G_SVM_HSTR                     GOP_REG(GOP_4G_OFST, 0x0a)
388*53ee8cc1Swenshuai.xi #define GOP_4G_SVM_HEND                     GOP_REG(GOP_4G_OFST, 0x0b)
389*53ee8cc1Swenshuai.xi #define GOP_4G_SVM_VSTR                     GOP_REG(GOP_4G_OFST, 0x0c)
390*53ee8cc1Swenshuai.xi #define GOP_4G_SVM_VEND                     GOP_REG(GOP_4G_OFST, 0x0d)
391*53ee8cc1Swenshuai.xi #define GOP_4G_RDMA_HT                      GOP_REG(GOP_4G_OFST, 0x0e)
392*53ee8cc1Swenshuai.xi #define GOP_4G_HS_PIPE                      GOP_REG(GOP_4G_OFST, 0x0f)
393*53ee8cc1Swenshuai.xi #define GOP_4G_SLOW                         GOP_REG(GOP_4G_OFST, 0x10)
394*53ee8cc1Swenshuai.xi #define GOP_4G_BRI                          GOP_REG(GOP_4G_OFST, 0x11)
395*53ee8cc1Swenshuai.xi #define GOP_4G_CON                          GOP_REG(GOP_4G_OFST, 0x12)
396*53ee8cc1Swenshuai.xi #define GOP_4G_BW                           GOP_REG(GOP_4G_OFST, 0x19)
397*53ee8cc1Swenshuai.xi #define GOP_4G_NEW_BW                       GOP_REG(GOP_4G_OFST, 0x1C)
398*53ee8cc1Swenshuai.xi #define GOP_4G_SRAM_BORROW                  GOP_REG(GOP_4G_OFST, 0x1D)
399*53ee8cc1Swenshuai.xi #define GOP_4G_3D_MIDDLE                    GOP_REG(GOP_4G_OFST, 0x1E)
400*53ee8cc1Swenshuai.xi #define GOP_4G_MIU_SEL                      GOP_REG(GOP_4G_OFST, 0x1F)
401*53ee8cc1Swenshuai.xi #define GOP_4G_PRI0                         GOP_REG(GOP_4G_OFST, 0x20)
402*53ee8cc1Swenshuai.xi #define GOP_4G_BOT_HS                       GOP_REG(GOP_4G_OFST, 0x23)
403*53ee8cc1Swenshuai.xi #define GOP_4G_TRSCLR_L                     GOP_REG(GOP_4G_OFST, 0x24)
404*53ee8cc1Swenshuai.xi #define GOP_4G_TRSCLR_H                     GOP_REG(GOP_4G_OFST, 0x25)
405*53ee8cc1Swenshuai.xi #define GOP_4G_YUV_SWAP                     GOP_REG(GOP_4G_OFST, 0x28)
406*53ee8cc1Swenshuai.xi #define GOP_4G_STRCH_HSZ                    GOP_REG(GOP_4G_OFST, 0x30)
407*53ee8cc1Swenshuai.xi #define GOP_4G_STRCH_VSZ                    GOP_REG(GOP_4G_OFST, 0x31)
408*53ee8cc1Swenshuai.xi #define GOP_4G_STRCH_HSTR                   GOP_REG(GOP_4G_OFST, 0x32)
409*53ee8cc1Swenshuai.xi #define GOP_4G_STRCH_VSTR                   GOP_REG(GOP_4G_OFST, 0x34)
410*53ee8cc1Swenshuai.xi #define GOP_4G_HSTRCH                       GOP_REG(GOP_4G_OFST, 0x35)
411*53ee8cc1Swenshuai.xi #define GOP_4G_VSTRCH                       GOP_REG(GOP_4G_OFST, 0x36)
412*53ee8cc1Swenshuai.xi #define GOP_4G_HSTRCH_INI                   GOP_REG(GOP_4G_OFST, 0x38)
413*53ee8cc1Swenshuai.xi #define GOP_4G_VSTRCH_INI                   GOP_REG(GOP_4G_OFST, 0x39)
414*53ee8cc1Swenshuai.xi #define GOP_4G_HVSTRCHMD                    GOP_REG(GOP_4G_OFST, 0x3a)
415*53ee8cc1Swenshuai.xi #define GOP_4G_OLDADDR                      GOP_REG(GOP_4G_OFST, 0x3b)
416*53ee8cc1Swenshuai.xi #define GOP_4G_MULTI_ALPHA                  GOP_REG(GOP_4G_OFST, 0x3c)
417*53ee8cc1Swenshuai.xi #define GOP_4G_HW_USAGE                     GOP_REG(GOP_4G_OFST, 0x40)
418*53ee8cc1Swenshuai.xi #define GOP_4G_BANK_FWR                     GOP_REG(GOP_4G_OFST, 0x50)
419*53ee8cc1Swenshuai.xi #define GOP_4G_BANK_HVAILDSIZE              GOP_REG(GOP_4G_OFST, 0x52)
420*53ee8cc1Swenshuai.xi #define GOP_4G_BANK_VVAILDSIZE              GOP_REG(GOP_4G_OFST, 0x53)
421*53ee8cc1Swenshuai.xi #define GOP_4G_SCALING_H_OUTPUTSIZE         GOP_REG(GOP_4G_OFST, 0x56)
422*53ee8cc1Swenshuai.xi #define GOP_4G_SCALING_HRATIO_L             GOP_REG(GOP_4G_OFST, 0x59)  //GOP scaling down ratio  dst / out * 2^20
423*53ee8cc1Swenshuai.xi #define GOP_4G_SCALING_HRATIO_H             GOP_REG(GOP_4G_OFST, 0x5A)
424*53ee8cc1Swenshuai.xi #define GOP_4G_SCALING_CFG                  GOP_REG(GOP_4G_OFST, 0x5B)
425*53ee8cc1Swenshuai.xi #define GOP_4G_SCALING_VRATIO_L             GOP_REG(GOP_4G_OFST, 0x5C)  //GOP scaling down ratio  dst / out * 2^20
426*53ee8cc1Swenshuai.xi #define GOP_4G_SCALING_VRATIO_H             GOP_REG(GOP_4G_OFST, 0x5D)
427*53ee8cc1Swenshuai.xi 
428*53ee8cc1Swenshuai.xi 
429*53ee8cc1Swenshuai.xi #define GOP_4G_RBLK0_VOFFL                  GOP_REG(GOP_4G_OFST, 0x60)
430*53ee8cc1Swenshuai.xi #define GOP_4G_RBLK0_VOFFH                  GOP_REG(GOP_4G_OFST, 0x61)
431*53ee8cc1Swenshuai.xi #define GOP_4G_RBLK1_VOFFL                  GOP_REG(GOP_4G_OFST, 0x62)
432*53ee8cc1Swenshuai.xi #define GOP_4G_RBLK1_VOFFH                  GOP_REG(GOP_4G_OFST, 0x63)
433*53ee8cc1Swenshuai.xi #define GOP_4G_RBLK2_VOFFL                  GOP_REG(GOP_4G_OFST, 0x64)
434*53ee8cc1Swenshuai.xi #define GOP_4G_RBLK2_VOFFH                  GOP_REG(GOP_4G_OFST, 0x65)
435*53ee8cc1Swenshuai.xi #define GOP_4G_RBLK3_VOFFL                  GOP_REG(GOP_4G_OFST, 0x66)
436*53ee8cc1Swenshuai.xi #define GOP_4G_RBLK3_VOFFH                  GOP_REG(GOP_4G_OFST, 0x67)
437*53ee8cc1Swenshuai.xi #define GOP_4G_RBLK0_HOFF                   GOP_REG(GOP_4G_OFST, 0x70)
438*53ee8cc1Swenshuai.xi #define GOP_4G_RBLK1_HOFF                   GOP_REG(GOP_4G_OFST, 0x71)
439*53ee8cc1Swenshuai.xi #define GOP_4G_RBLK2_HOFF                   GOP_REG(GOP_4G_OFST, 0x72)
440*53ee8cc1Swenshuai.xi #define GOP_4G_RBLK3_HOFF                   GOP_REG(GOP_4G_OFST, 0x73)
441*53ee8cc1Swenshuai.xi #define GOP_4G_REGDMA_EN                    GOP_REG(GOP_4G_OFST, 0x78)
442*53ee8cc1Swenshuai.xi #define GOP_MUX_IPVOP                       __GOP_REG(0x77)
443*53ee8cc1Swenshuai.xi #define GOP_MUX4_MIX_VE                     __GOP_REG(0x7B)
444*53ee8cc1Swenshuai.xi #define GOP_BAK_SEL_EX                      __GOP_REG(0x7C)
445*53ee8cc1Swenshuai.xi #define GOP_MUX_4K2K                        __GOP_REG(0x7D)
446*53ee8cc1Swenshuai.xi #define GOP_MUX                             __GOP_REG(0x7e)
447*53ee8cc1Swenshuai.xi #define GOP_BAK_SEL                         __GOP_REG(0x7f)
448*53ee8cc1Swenshuai.xi 
449*53ee8cc1Swenshuai.xi #define GOP_4G_GWIN0_CTRL(id)               GOP_REG(GOP_4G_OFST+1, 0x00 + (0x20*((id)%MAX_GOP0_GWIN)))
450*53ee8cc1Swenshuai.xi #define GOP_4G_DRAM_RBLK_L(id)              GOP_REG(GOP_4G_OFST+1, 0x01 + (0x20*((id)%MAX_GOP0_GWIN)))
451*53ee8cc1Swenshuai.xi #define GOP_4G_DRAM_RBLK_H(id)              GOP_REG(GOP_4G_OFST+1, 0x02 + (0x20*((id)%MAX_GOP0_GWIN)))
452*53ee8cc1Swenshuai.xi #define GOP_4G_DEL_PIXEL(id)                GOP_REG(GOP_4G_OFST+1, 0x03 + (0x20*((id)%MAX_GOP1_GWIN)))
453*53ee8cc1Swenshuai.xi #define GOP_4G_HSTR(id)                     GOP_REG(GOP_4G_OFST+1, 0x04 + (0x20*((id)%MAX_GOP0_GWIN)))
454*53ee8cc1Swenshuai.xi #define GOP_4G_HEND(id)                     GOP_REG(GOP_4G_OFST+1, 0x05 + (0x20*((id)%MAX_GOP0_GWIN)))
455*53ee8cc1Swenshuai.xi #define GOP_4G_VSTR(id)                     GOP_REG(GOP_4G_OFST+1, 0x06 + (0x20*((id)%MAX_GOP0_GWIN)))
456*53ee8cc1Swenshuai.xi #define GOP_4G_GWIN_MIDDLE(id)              GOP_REG(GOP_4G_OFST+1, 0x07 + (0x20*((id)%MAX_GOP0_GWIN)))
457*53ee8cc1Swenshuai.xi #define GOP_4G_VEND(id)                     GOP_REG(GOP_4G_OFST+1, 0x08 + (0x20*((id)%MAX_GOP0_GWIN)))
458*53ee8cc1Swenshuai.xi #define GOP_4G_DRAM_RBLK_HSIZE(id)          GOP_REG(GOP_4G_OFST+1, 0x09 + (0x20*((id)%MAX_GOP0_GWIN)))
459*53ee8cc1Swenshuai.xi #define GOP_4G_GWIN_ALPHA01(id)             GOP_REG(GOP_4G_OFST+1, 0x0A + (0x20*((id)%MAX_GOP0_GWIN)))
460*53ee8cc1Swenshuai.xi #define GOP_4G_DRAM_VSTR_L(id)              GOP_REG(GOP_4G_OFST+1, 0x0C + (0x20*((id)%MAX_GOP0_GWIN)))
461*53ee8cc1Swenshuai.xi #define GOP_4G_DRAM_VSTR_H(id)              GOP_REG(GOP_4G_OFST+1, 0x0D + (0x20*((id)%MAX_GOP0_GWIN)))
462*53ee8cc1Swenshuai.xi #define GOP_4G_DRAM_HSTR(id)                GOP_REG(GOP_4G_OFST+1, 0x0E + (0x20*((id)%MAX_GOP0_GWIN)))
463*53ee8cc1Swenshuai.xi #define GOP_4G_DRAM_RBLK_SIZE_L(id)         GOP_REG(GOP_4G_OFST+1, 0x10 + (0x20*((id)%MAX_GOP0_GWIN)))
464*53ee8cc1Swenshuai.xi #define GOP_4G_DRAM_RBLK_SIZE_H(id)         GOP_REG(GOP_4G_OFST+1, 0x11 + (0x20*((id)%MAX_GOP0_GWIN)))
465*53ee8cc1Swenshuai.xi #define GOP_4G_DRAM_RLEN_L(id)              GOP_REG(GOP_4G_OFST+1, 0x12 + (0x20*((id)%MAX_GOP0_GWIN)))
466*53ee8cc1Swenshuai.xi #define GOP_4G_DRAM_RLEN_H(id)              GOP_REG(GOP_4G_OFST+1, 0x13 + (0x20*((id)%MAX_GOP0_GWIN)))
467*53ee8cc1Swenshuai.xi #define GOP_4G_DRAM_HVSTOP_L(id)            GOP_REG(GOP_4G_OFST+1, 0x14 + (0x20*((id)%MAX_GOP0_GWIN)))
468*53ee8cc1Swenshuai.xi #define GOP_4G_DRAM_HVSTOP_H(id)            GOP_REG(GOP_4G_OFST+1, 0x15 + (0x20*((id)%MAX_GOP0_GWIN)))
469*53ee8cc1Swenshuai.xi #define GOP_4G_DRAM_FADE(id)                GOP_REG(GOP_4G_OFST+1, 0x16 + (0x20*((id)%MAX_GOP0_GWIN)))
470*53ee8cc1Swenshuai.xi #define GOP_4G_BG_CLR(id)                   GOP_REG(GOP_4G_OFST+1, 0x18 + (0x20*((id)%MAX_GOP0_GWIN)))
471*53ee8cc1Swenshuai.xi #define GOP_4G_BG_HSTR(id)                  GOP_REG(GOP_4G_OFST+1, 0x19 + (0x20*((id)%MAX_GOP0_GWIN)))
472*53ee8cc1Swenshuai.xi #define GOP_4G_BG_HEND(id)                  GOP_REG(GOP_4G_OFST+1, 0x1a + (0x20*((id)%MAX_GOP0_GWIN)))
473*53ee8cc1Swenshuai.xi #define GOP_4G_BG_VSTR(id)                  GOP_REG(GOP_4G_OFST+1, 0x1C + (0x20*((id)%MAX_GOP0_GWIN)))
474*53ee8cc1Swenshuai.xi #define GOP_4G_BG_VEND(id)                  GOP_REG(GOP_4G_OFST+1, 0x1D + (0x20*((id)%MAX_GOP0_GWIN)))
475*53ee8cc1Swenshuai.xi #define GOP_4G_3DOSD_SUB_RBLK_L(id)         GOP_REG(GOP_4G_OFST+1, 0x1E + (0x20*((id)%MAX_GOP0_GWIN)))
476*53ee8cc1Swenshuai.xi #define GOP_4G_3DOSD_SUB_RBLK_H(id)         GOP_REG(GOP_4G_OFST+1, 0x1F + (0x20*((id)%MAX_GOP0_GWIN)))
477*53ee8cc1Swenshuai.xi 
478*53ee8cc1Swenshuai.xi 
479*53ee8cc1Swenshuai.xi #define GOP_2G_CTRL0                        GOP_REG(GOP_2G_OFST, 0x00)
480*53ee8cc1Swenshuai.xi #define GOP_2G_CTRL1                        GOP_REG(GOP_2G_OFST, 0x01)
481*53ee8cc1Swenshuai.xi #define GOP_2G_RATE                         GOP_REG(GOP_2G_OFST, 0x02)
482*53ee8cc1Swenshuai.xi #define GOP_2G_PALDATA_L                    GOP_REG(GOP_2G_OFST, 0x03)
483*53ee8cc1Swenshuai.xi #define GOP_2G_PALDATA_H                    GOP_REG(GOP_2G_OFST, 0x04)
484*53ee8cc1Swenshuai.xi #define GOP_2G_PALCTRL                      GOP_REG(GOP_2G_OFST, 0x05)
485*53ee8cc1Swenshuai.xi #define GOP_2G_REGDMA_END                   GOP_REG(GOP_2G_OFST, 0x06)
486*53ee8cc1Swenshuai.xi #define GOP_2G_REGDMA_STR                   GOP_REG(GOP_2G_OFST, 0x07)
487*53ee8cc1Swenshuai.xi #define GOP_2G_INT                          GOP_REG(GOP_2G_OFST, 0x08)
488*53ee8cc1Swenshuai.xi #define GOP_2G_HWSTATE                      GOP_REG(GOP_2G_OFST, 0x09)
489*53ee8cc1Swenshuai.xi #define GOP_2G_RDMA_HT                      GOP_REG(GOP_2G_OFST, 0x0e)
490*53ee8cc1Swenshuai.xi #define GOP_2G_HS_PIPE                      GOP_REG(GOP_2G_OFST, 0x0f)
491*53ee8cc1Swenshuai.xi #define GOP_2G_SLOW                         GOP_REG(GOP_2G_OFST, 0x10)
492*53ee8cc1Swenshuai.xi #define GOP_2G_BRI                          GOP_REG(GOP_2G_OFST, 0x11)
493*53ee8cc1Swenshuai.xi #define GOP_2G_CON                          GOP_REG(GOP_2G_OFST, 0x12)
494*53ee8cc1Swenshuai.xi #define GOP_2G_BW                           GOP_REG(GOP_2G_OFST, 0x19)
495*53ee8cc1Swenshuai.xi #define GOP_2G_3D_MIDDLE                    GOP_REG(GOP_2G_OFST, 0x1E)
496*53ee8cc1Swenshuai.xi #define GOP_2G_PRI0                         GOP_REG(GOP_2G_OFST, 0x20)
497*53ee8cc1Swenshuai.xi #define GOP_2G_TRSCLR_L                     GOP_REG(GOP_2G_OFST, 0x24)
498*53ee8cc1Swenshuai.xi #define GOP_2G_TRSCLR_H                     GOP_REG(GOP_2G_OFST, 0x25)
499*53ee8cc1Swenshuai.xi #define GOP_2G_STRCH_HSZ                    GOP_REG(GOP_2G_OFST, 0x30)
500*53ee8cc1Swenshuai.xi #define GOP_2G_STRCH_VSZ                    GOP_REG(GOP_2G_OFST, 0x31)
501*53ee8cc1Swenshuai.xi #define GOP_2G_STRCH_HSTR                   GOP_REG(GOP_2G_OFST, 0x32)
502*53ee8cc1Swenshuai.xi #define GOP_2G_STRCH_VSTR                   GOP_REG(GOP_2G_OFST, 0x34)
503*53ee8cc1Swenshuai.xi #define GOP_2G_HSTRCH                       GOP_REG(GOP_2G_OFST, 0x35)
504*53ee8cc1Swenshuai.xi #define GOP_2G_VSTRCH                       GOP_REG(GOP_2G_OFST, 0x36)
505*53ee8cc1Swenshuai.xi #define GOP_2G_HSTRCH_INI                   GOP_REG(GOP_2G_OFST, 0x38)
506*53ee8cc1Swenshuai.xi #define GOP_2G_VSTRCH_INI                   GOP_REG(GOP_2G_OFST, 0x39)
507*53ee8cc1Swenshuai.xi #define GOP_2G_HVStrch_MD                   GOP_REG(GOP_2G_OFST, 0x3a)
508*53ee8cc1Swenshuai.xi #define GOP_2G_OLDADDR                      GOP_REG(GOP_2G_OFST, 0x3b)
509*53ee8cc1Swenshuai.xi #define GOP_2G_MULTI_ALPHA                  GOP_REG(GOP_2G_OFST, 0x3c)
510*53ee8cc1Swenshuai.xi #define GOP_2G_REGDMA_EN                    GOP_REG(GOP_2G_OFST, 0x78)
511*53ee8cc1Swenshuai.xi 
512*53ee8cc1Swenshuai.xi 
513*53ee8cc1Swenshuai.xi #define GOP_2G_GWIN0_CTRL(id)               GOP_REG(GOP_2G_OFST+1, 0x00 + (0x20*((id)%MAX_GOP1_GWIN)))
514*53ee8cc1Swenshuai.xi #define GOP_2G_GWIN_CTRL(id)                GOP_REG(GOP_2G_OFST+1, 0x00 + (0x20*((id)%MAX_GOP1_GWIN)))
515*53ee8cc1Swenshuai.xi #define GOP_2G_DRAM_RBLK_L(id)              GOP_REG(GOP_2G_OFST+1, 0x01 + (0x20*((id)%MAX_GOP1_GWIN)))
516*53ee8cc1Swenshuai.xi #define GOP_2G_DRAM_RBLK_H(id)              GOP_REG(GOP_2G_OFST+1, 0x02 + (0x20*((id)%MAX_GOP1_GWIN)))
517*53ee8cc1Swenshuai.xi #define GOP_2G_DEL_PIXEL(id)                GOP_REG(GOP_2G_OFST+1, 0x03 + (0x20*((id)%MAX_GOP1_GWIN)))
518*53ee8cc1Swenshuai.xi #define GOP_2G_HSTR(id)                     GOP_REG(GOP_2G_OFST+1, 0x04 + (0x20*((id)%MAX_GOP1_GWIN)))
519*53ee8cc1Swenshuai.xi #define GOP_2G_HEND(id)                     GOP_REG(GOP_2G_OFST+1, 0x05 + (0x20*((id)%MAX_GOP1_GWIN)))
520*53ee8cc1Swenshuai.xi #define GOP_2G_VSTR(id)                     GOP_REG(GOP_2G_OFST+1, 0x06 + (0x20*((id)%MAX_GOP1_GWIN)))
521*53ee8cc1Swenshuai.xi #define GOP_2G_VEND(id)                     GOP_REG(GOP_2G_OFST+1, 0x08 + (0x20*((id)%MAX_GOP1_GWIN)))
522*53ee8cc1Swenshuai.xi #define GOP_2G_DRAM_RBLK_HSIZE(id)          GOP_REG(GOP_2G_OFST+1, 0x09 + (0x20*((id)%MAX_GOP1_GWIN)))
523*53ee8cc1Swenshuai.xi #define GOP_2G_GWIN_ALPHA01(id)             GOP_REG(GOP_2G_OFST+1, 0x0A + (0x20*((id)%MAX_GOP1_GWIN)))
524*53ee8cc1Swenshuai.xi #define GOP_2G_DRAM_VSTR_L(id)              GOP_REG(GOP_2G_OFST+1, 0x0C + (0x20*((id)%MAX_GOP1_GWIN)))
525*53ee8cc1Swenshuai.xi #define GOP_2G_DRAM_VSTR_H(id)              GOP_REG(GOP_2G_OFST+1, 0x0D + (0x20*((id)%MAX_GOP1_GWIN)))
526*53ee8cc1Swenshuai.xi #define GOP_2G_DRAM_FADE(id)                GOP_REG(GOP_2G_OFST+1, 0x16 + (0x20*((id)%MAX_GOP1_GWIN)))
527*53ee8cc1Swenshuai.xi #define GOP_2G_3DOSD_SUB_RBLK_L(id)         GOP_REG(GOP_2G_OFST+1, 0x1E + (0x20*((id)%MAX_GOP1_GWIN)))
528*53ee8cc1Swenshuai.xi #define GOP_2G_3DOSD_SUB_RBLK_H(id)         GOP_REG(GOP_2G_OFST+1, 0x1F + (0x20*((id)%MAX_GOP1_GWIN)))
529*53ee8cc1Swenshuai.xi 
530*53ee8cc1Swenshuai.xi // DWIN reg
531*53ee8cc1Swenshuai.xi #define GOP_DW_CTL0_EN                          GOP_REG(GOP_DW_OFST, 0x00)
532*53ee8cc1Swenshuai.xi #define GOP_DWIN_EN                             (0x00)
533*53ee8cc1Swenshuai.xi #define GOP_DWIN_EN_VAL                         GOP_REG_VAL(GOP_DWIN_EN)
534*53ee8cc1Swenshuai.xi #define GOP_DWIN_SHOT                           (0x07)
535*53ee8cc1Swenshuai.xi #define GOP_DWIN_SHOT_VAL                       GOP_REG_VAL(GOP_DWIN_SHOT)
536*53ee8cc1Swenshuai.xi 
537*53ee8cc1Swenshuai.xi #define GOP_DW_LSTR_WBE                         GOP_REG(GOP_DW_OFST, 0x01)
538*53ee8cc1Swenshuai.xi #define GOP_DW_INT_MASK                         GOP_REG(GOP_DW_OFST, 0x02)
539*53ee8cc1Swenshuai.xi #define GOP_DW_DEBUG                            GOP_REG(GOP_DW_OFST, 0x03)
540*53ee8cc1Swenshuai.xi #define GOP_DW_ALPHA                            GOP_REG(GOP_DW_OFST, 0x04)
541*53ee8cc1Swenshuai.xi #define GOP_DW_BW                               GOP_REG(GOP_DW_OFST, 0x05)
542*53ee8cc1Swenshuai.xi #define GOP_DW_VSTR                             GOP_REG(GOP_DW_OFST, 0x10)
543*53ee8cc1Swenshuai.xi #define GOP_DW_HSTR                             GOP_REG(GOP_DW_OFST, 0x11)
544*53ee8cc1Swenshuai.xi #define GOP_DW_VEND                             GOP_REG(GOP_DW_OFST, 0x12)
545*53ee8cc1Swenshuai.xi #define GOP_DW_HEND                             GOP_REG(GOP_DW_OFST, 0x13)
546*53ee8cc1Swenshuai.xi #define GOP_DW_HSIZE                            GOP_REG(GOP_DW_OFST, 0x14)
547*53ee8cc1Swenshuai.xi #define GOP_DW_JMPLEN                           GOP_REG(GOP_DW_OFST, 0x15)
548*53ee8cc1Swenshuai.xi #define GOP_DW_DSTR_L                           GOP_REG(GOP_DW_OFST, 0x16)
549*53ee8cc1Swenshuai.xi #define GOP_DW_DSTR_H                           GOP_REG(GOP_DW_OFST, 0x17)
550*53ee8cc1Swenshuai.xi #define GOP_DW_UB_L                             GOP_REG(GOP_DW_OFST, 0x18)
551*53ee8cc1Swenshuai.xi #define GOP_DW_UB_H                             GOP_REG(GOP_DW_OFST, 0x19)
552*53ee8cc1Swenshuai.xi 
553*53ee8cc1Swenshuai.xi #define GOP_DW_PON_DSTR_L                       GOP_REG(GOP_DW_OFST, 0x1a)
554*53ee8cc1Swenshuai.xi #define GOP_DW_PON_DSTR_H                       GOP_REG(GOP_DW_OFST, 0x1b)
555*53ee8cc1Swenshuai.xi #define GOP_DW_PON_UB_L                         GOP_REG(GOP_DW_OFST, 0x1c)
556*53ee8cc1Swenshuai.xi #define GOP_DW_PON_UB_H                         GOP_REG(GOP_DW_OFST, 0x1d)
557*53ee8cc1Swenshuai.xi #define GOP_DW_FRAME_CTRL                       GOP_REG(GOP_DW_OFST, 0x30)
558*53ee8cc1Swenshuai.xi 
559*53ee8cc1Swenshuai.xi #define GOP_1G_CTRL0                        GOP_REG(GOP_1G_OFST, 0x00)
560*53ee8cc1Swenshuai.xi #define GOP_1G_CTRL1                        GOP_REG(GOP_1G_OFST, 0x01)
561*53ee8cc1Swenshuai.xi #define GOP_1G_RATE                         GOP_REG(GOP_1G_OFST, 0x02)
562*53ee8cc1Swenshuai.xi #define GOP_1G_PALDATA_L                    GOP_REG(GOP_1G_OFST, 0x03)
563*53ee8cc1Swenshuai.xi #define GOP_1G_PALDATA_H                    GOP_REG(GOP_1G_OFST, 0x04)
564*53ee8cc1Swenshuai.xi #define GOP_1G_PALCTRL                      GOP_REG(GOP_1G_OFST, 0x05)
565*53ee8cc1Swenshuai.xi #define GOP_1G_REGDMA_END                   GOP_REG(GOP_1G_OFST, 0x06)
566*53ee8cc1Swenshuai.xi #define GOP_1G_REGDMA_STR                   GOP_REG(GOP_1G_OFST, 0x07)
567*53ee8cc1Swenshuai.xi #define GOP_1G_INT                          GOP_REG(GOP_1G_OFST, 0x08)
568*53ee8cc1Swenshuai.xi #define GOP_1G_HWSTATE                      GOP_REG(GOP_1G_OFST, 0x09)
569*53ee8cc1Swenshuai.xi #define GOP_1G_RDMA_HT                      GOP_REG(GOP_1G_OFST, 0x0e)
570*53ee8cc1Swenshuai.xi #define GOP_1G_HS_PIPE                      GOP_REG(GOP_1G_OFST, 0x0f)
571*53ee8cc1Swenshuai.xi #define GOP_1G_BRI                          GOP_REG(GOP_1G_OFST, 0x11)
572*53ee8cc1Swenshuai.xi #define GOP_1G_CON                          GOP_REG(GOP_1G_OFST, 0x12)
573*53ee8cc1Swenshuai.xi #define GOP_1G_BW                           GOP_REG(GOP_1G_OFST, 0x19)
574*53ee8cc1Swenshuai.xi #define GOP_1G_3D_MIDDLE                    GOP_REG(GOP_1G_OFST, 0x1E)
575*53ee8cc1Swenshuai.xi #define GOP_1G_TRSCLR_L                     GOP_REG(GOP_1G_OFST, 0x24)
576*53ee8cc1Swenshuai.xi #define GOP_1G_TRSCLR_H                     GOP_REG(GOP_1G_OFST, 0x25)
577*53ee8cc1Swenshuai.xi #define GOP_1G_STRCH_HSZ                    GOP_REG(GOP_1G_OFST, 0x30)
578*53ee8cc1Swenshuai.xi #define GOP_1G_STRCH_VSZ                    GOP_REG(GOP_1G_OFST, 0x31)
579*53ee8cc1Swenshuai.xi #define GOP_1G_STRCH_HSTR                   GOP_REG(GOP_1G_OFST, 0x32)
580*53ee8cc1Swenshuai.xi #define GOP_1G_STRCH_VSTR                   GOP_REG(GOP_1G_OFST, 0x34)
581*53ee8cc1Swenshuai.xi #define GOP_1G_HSTRCH                       GOP_REG(GOP_1G_OFST, 0x35)
582*53ee8cc1Swenshuai.xi #define GOP_1G_HSTRCH_INI                   GOP_REG(GOP_1G_OFST, 0x38)
583*53ee8cc1Swenshuai.xi #define GOP_1G_VSTRCH_INI                   GOP_REG(GOP_1G_OFST, 0x39)
584*53ee8cc1Swenshuai.xi #define GOP_1G_HStrch_MD                    GOP_REG(GOP_1G_OFST, 0x3a)
585*53ee8cc1Swenshuai.xi #define GOP_1G_OLDADDR                      GOP_REG(GOP_1G_OFST, 0x3b)
586*53ee8cc1Swenshuai.xi #define GOP_1G_MULTI_ALPHA                  GOP_REG(GOP_1G_OFST, 0x3c)
587*53ee8cc1Swenshuai.xi 
588*53ee8cc1Swenshuai.xi #define GOP_1G_GWIN0_CTRL                   GOP_REG(GOP_1G_OFST+1, 0x0)
589*53ee8cc1Swenshuai.xi #define GOP_1G_DRAM_RBLK_L                  GOP_REG(GOP_1G_OFST+1, 0x1)
590*53ee8cc1Swenshuai.xi #define GOP_1G_DRAM_RBLK_H                  GOP_REG(GOP_1G_OFST+1, 0x2)
591*53ee8cc1Swenshuai.xi #define GOP_1G_DEL_PIXEL                    GOP_REG(GOP_1G_OFST+1, 0x3)
592*53ee8cc1Swenshuai.xi #define GOP_1G_HSTR                         GOP_REG(GOP_1G_OFST+1, 0x4)
593*53ee8cc1Swenshuai.xi #define GOP_1G_HEND                         GOP_REG(GOP_1G_OFST+1, 0x5)
594*53ee8cc1Swenshuai.xi #define GOP_1G_VSTR                         GOP_REG(GOP_1G_OFST+1, 0x6)
595*53ee8cc1Swenshuai.xi #define GOP_1G_VEND                         GOP_REG(GOP_1G_OFST+1, 0x8)
596*53ee8cc1Swenshuai.xi #define GOP_1G_DRAM_RBLK_HSIZE              GOP_REG(GOP_1G_OFST+1, 0x9)
597*53ee8cc1Swenshuai.xi #define GOP_1G_GWIN_ALPHA01                 GOP_REG(GOP_1G_OFST+1, 0xA)
598*53ee8cc1Swenshuai.xi #define GOP_1G_DRAM_VSTR_L                  GOP_REG(GOP_1G_OFST+1, 0x0C)
599*53ee8cc1Swenshuai.xi #define GOP_1G_DRAM_VSTR_H                  GOP_REG(GOP_1G_OFST+1, 0x0D)
600*53ee8cc1Swenshuai.xi #define GOP_1G_DRAM_FADE                    GOP_REG(GOP_1G_OFST+1, 0x16)
601*53ee8cc1Swenshuai.xi #define GOP_1G_3DOSD_SUB_RBLK_L             GOP_REG(GOP_1G_OFST+1, 0x1E)
602*53ee8cc1Swenshuai.xi #define GOP_1G_3DOSD_SUB_RBLK_H             GOP_REG(GOP_1G_OFST+1, 0x1F)
603*53ee8cc1Swenshuai.xi 
604*53ee8cc1Swenshuai.xi #define GOP_1GX_CTRL0                        GOP_REG(GOP_1GX_OFST, 0x00)
605*53ee8cc1Swenshuai.xi #define GOP_1GX_CTRL1                        GOP_REG(GOP_1GX_OFST, 0x01)
606*53ee8cc1Swenshuai.xi #define GOP_1GX_RATE                         GOP_REG(GOP_1GX_OFST, 0x02)
607*53ee8cc1Swenshuai.xi #define GOP_1GX_PALDATA_L                    GOP_REG(GOP_1GX_OFST, 0x03)
608*53ee8cc1Swenshuai.xi #define GOP_1GX_PALDATA_H                    GOP_REG(GOP_1GX_OFST, 0x04)
609*53ee8cc1Swenshuai.xi #define GOP_1GX_PALCTRL                      GOP_REG(GOP_1GX_OFST, 0x05)
610*53ee8cc1Swenshuai.xi #define GOP_1GX_REGDMA_END                   GOP_REG(GOP_1GX_OFST, 0x06)
611*53ee8cc1Swenshuai.xi #define GOP_1GX_REGDMA_STR                   GOP_REG(GOP_1GX_OFST, 0x07)
612*53ee8cc1Swenshuai.xi #define GOP_1GX_INT                          GOP_REG(GOP_1GX_OFST, 0x08)
613*53ee8cc1Swenshuai.xi #define GOP_1GX_HWSTATE                      GOP_REG(GOP_1GX_OFST, 0x09)
614*53ee8cc1Swenshuai.xi #define GOP_1GX_RDMA_HT                      GOP_REG(GOP_1GX_OFST, 0x0e)
615*53ee8cc1Swenshuai.xi #define GOP_1GX_HS_PIPE                      GOP_REG(GOP_1GX_OFST, 0x0f)
616*53ee8cc1Swenshuai.xi #define GOP_1GX_BRI                          GOP_REG(GOP_1GX_OFST, 0x11)
617*53ee8cc1Swenshuai.xi #define GOP_1GX_CON                          GOP_REG(GOP_1GX_OFST, 0x12)
618*53ee8cc1Swenshuai.xi #define GOP_1GX_BW                           GOP_REG(GOP_1GX_OFST, 0x19)
619*53ee8cc1Swenshuai.xi #define GOP_1GX_3D_MIDDLE                    GOP_REG(GOP_1GX_OFST, 0x1E)
620*53ee8cc1Swenshuai.xi #define GOP_1GX_TRSCLR_L                     GOP_REG(GOP_1GX_OFST, 0x24)
621*53ee8cc1Swenshuai.xi #define GOP_1GX_TRSCLR_H                     GOP_REG(GOP_1GX_OFST, 0x25)
622*53ee8cc1Swenshuai.xi #define GOP_1GX_STRCH_HSZ                    GOP_REG(GOP_1GX_OFST, 0x30)
623*53ee8cc1Swenshuai.xi #define GOP_1GX_STRCH_VSZ                    GOP_REG(GOP_1GX_OFST, 0x31)
624*53ee8cc1Swenshuai.xi #define GOP_1GX_STRCH_HSTR                   GOP_REG(GOP_1GX_OFST, 0x32)
625*53ee8cc1Swenshuai.xi #define GOP_1GX_STRCH_VSTR                   GOP_REG(GOP_1GX_OFST, 0x34)
626*53ee8cc1Swenshuai.xi #define GOP_1GX_HSTRCH                       GOP_REG(GOP_1GX_OFST, 0x35)
627*53ee8cc1Swenshuai.xi #define GOP_1GX_HSTRCH_INI                   GOP_REG(GOP_1GX_OFST, 0x38)
628*53ee8cc1Swenshuai.xi #define GOP_1GX_VSTRCH_INI                   GOP_REG(GOP_1GX_OFST, 0x39)
629*53ee8cc1Swenshuai.xi #define GOP_1GX_HStrch_MD                    GOP_REG(GOP_1GX_OFST, 0x3a)
630*53ee8cc1Swenshuai.xi #define GOP_1GX_OLDADDR                      GOP_REG(GOP_1GX_OFST, 0x3b)
631*53ee8cc1Swenshuai.xi #define GOP_1GX_MULTI_ALPHA                  GOP_REG(GOP_1GX_OFST, 0x3c)
632*53ee8cc1Swenshuai.xi 
633*53ee8cc1Swenshuai.xi #define GOP_1GX_GWIN0_CTRL                   GOP_REG(GOP_1GX_OFST+1, 0x00)
634*53ee8cc1Swenshuai.xi #define GOP_1GX_DRAM_RBLK_L                  GOP_REG(GOP_1GX_OFST+1, 0x01)
635*53ee8cc1Swenshuai.xi #define GOP_1GX_DRAM_RBLK_H                  GOP_REG(GOP_1GX_OFST+1, 0x02)
636*53ee8cc1Swenshuai.xi #define GOP_1GX_DEL_PIXEL                    GOP_REG(GOP_1GX_OFST+1, 0x03)
637*53ee8cc1Swenshuai.xi #define GOP_1GX_HSTR                         GOP_REG(GOP_1GX_OFST+1, 0x04)
638*53ee8cc1Swenshuai.xi #define GOP_1GX_HEND                         GOP_REG(GOP_1GX_OFST+1, 0x05)
639*53ee8cc1Swenshuai.xi #define GOP_1GX_VSTR                         GOP_REG(GOP_1GX_OFST+1, 0x06)
640*53ee8cc1Swenshuai.xi #define GOP_1GX_VEND                         GOP_REG(GOP_1GX_OFST+1, 0x08)
641*53ee8cc1Swenshuai.xi #define GOP_1GX_DRAM_RBLK_HSIZE              GOP_REG(GOP_1GX_OFST+1, 0x09)
642*53ee8cc1Swenshuai.xi #define GOP_1GX_GWIN_ALPHA01                 GOP_REG(GOP_1GX_OFST+1, 0x0A)
643*53ee8cc1Swenshuai.xi #define GOP_1GX_DRAM_VSTR_L                  GOP_REG(GOP_1GX_OFST+1, 0x0C)
644*53ee8cc1Swenshuai.xi #define GOP_1GX_DRAM_VSTR_H                  GOP_REG(GOP_1GX_OFST+1, 0x0D)
645*53ee8cc1Swenshuai.xi #define GOP_1GX_DRAM_FADE                    GOP_REG(GOP_1GX_OFST+1, 0x16)
646*53ee8cc1Swenshuai.xi #define GOP_1GX_3DOSD_SUB_RBLK_L             GOP_REG(GOP_1GX_OFST+1, 0x1E)
647*53ee8cc1Swenshuai.xi #define GOP_1GX_3DOSD_SUB_RBLK_H             GOP_REG(GOP_1GX_OFST+1, 0x1F)
648*53ee8cc1Swenshuai.xi 
649*53ee8cc1Swenshuai.xi #define GOP_1GS0_CTRL0                        GOP_REG(GOP_1GS0_OFST, 0x00)
650*53ee8cc1Swenshuai.xi #define GOP_1GS0_CTRL1                        GOP_REG(GOP_1GS0_OFST, 0x01)
651*53ee8cc1Swenshuai.xi #define GOP_1GS0_RATE                         GOP_REG(GOP_1GS0_OFST, 0x02)
652*53ee8cc1Swenshuai.xi #define GOP_1GS0_PALDATA_L                    GOP_REG(GOP_1GS0_OFST, 0x03)
653*53ee8cc1Swenshuai.xi #define GOP_1GS0_PALDATA_H                    GOP_REG(GOP_1GS0_OFST, 0x04)
654*53ee8cc1Swenshuai.xi #define GOP_1GS0_PALCTRL                      GOP_REG(GOP_1GS0_OFST, 0x05)
655*53ee8cc1Swenshuai.xi #define GOP_1GS0_REGDMA_END                   GOP_REG(GOP_1GS0_OFST, 0x06)
656*53ee8cc1Swenshuai.xi #define GOP_1GS0_REGDMA_STR                   GOP_REG(GOP_1GS0_OFST, 0x07)
657*53ee8cc1Swenshuai.xi #define GOP_1GS0_INT                          GOP_REG(GOP_1GS0_OFST, 0x08)
658*53ee8cc1Swenshuai.xi #define GOP_1GS0_HWSTATE                      GOP_REG(GOP_1GS0_OFST, 0x09)
659*53ee8cc1Swenshuai.xi #define GOP_1GS0_RDMA_HT                      GOP_REG(GOP_1GS0_OFST, 0x0e)
660*53ee8cc1Swenshuai.xi #define GOP_1GS0_HS_PIPE                      GOP_REG(GOP_1GS0_OFST, 0x0f)
661*53ee8cc1Swenshuai.xi #define GOP_1GS0_BRI                          GOP_REG(GOP_1GS0_OFST, 0x11)
662*53ee8cc1Swenshuai.xi #define GOP_1GS0_CON                          GOP_REG(GOP_1GS0_OFST, 0x12)
663*53ee8cc1Swenshuai.xi #define GOP_1GS0_BW                           GOP_REG(GOP_1GS0_OFST, 0x19)
664*53ee8cc1Swenshuai.xi #define GOP_1GS0_TRSCLR_L                     GOP_REG(GOP_1GS0_OFST, 0x24)
665*53ee8cc1Swenshuai.xi #define GOP_1GS0_TRSCLR_H                     GOP_REG(GOP_1GS0_OFST, 0x25)
666*53ee8cc1Swenshuai.xi #define GOP_1GS0_STRCH_HSZ                    GOP_REG(GOP_1GS0_OFST, 0x30)
667*53ee8cc1Swenshuai.xi #define GOP_1GS0_STRCH_VSZ                    GOP_REG(GOP_1GS0_OFST, 0x31)
668*53ee8cc1Swenshuai.xi #define GOP_1GS0_STRCH_HSTR                   GOP_REG(GOP_1GS0_OFST, 0x32)
669*53ee8cc1Swenshuai.xi #define GOP_1GS0_STRCH_VSTR                   GOP_REG(GOP_1GS0_OFST, 0x34)
670*53ee8cc1Swenshuai.xi #define GOP_1GS0_HSTRCH                       GOP_REG(GOP_1GS0_OFST, 0x35)
671*53ee8cc1Swenshuai.xi #define GOP_1GS0_HSTRCH_INI                   GOP_REG(GOP_1GS0_OFST, 0x38)
672*53ee8cc1Swenshuai.xi #define GOP_1GS0_VSTRCH_INI                   GOP_REG(GOP_1GS0_OFST, 0x39)
673*53ee8cc1Swenshuai.xi #define GOP_1GS0_HVStrch_MD                    GOP_REG(GOP_1GS0_OFST, 0x3a)
674*53ee8cc1Swenshuai.xi #define GOP_1GS0_OLDADDR                      GOP_REG(GOP_1GS0_OFST, 0x3b)
675*53ee8cc1Swenshuai.xi #define GOP_1GS0_MULTI_ALPHA                  GOP_REG(GOP_1GS0_OFST, 0x3c)
676*53ee8cc1Swenshuai.xi 
677*53ee8cc1Swenshuai.xi #define GOP_1GS0_GWIN0_CTRL                   GOP_REG(GOP_1GS0_OFST+1, 0x00)
678*53ee8cc1Swenshuai.xi #define GOP_1GS0_DRAM_RBLK_L                  GOP_REG(GOP_1GS0_OFST+1, 0x01)
679*53ee8cc1Swenshuai.xi #define GOP_1GS0_DRAM_RBLK_H                  GOP_REG(GOP_1GS0_OFST+1, 0x02)
680*53ee8cc1Swenshuai.xi #define GOP_1GS0_DEL_PIXEL                    GOP_REG(GOP_1GS0_OFST+1, 0x03)
681*53ee8cc1Swenshuai.xi #define GOP_1GS0_HSTR                         GOP_REG(GOP_1GS0_OFST+1, 0x04)
682*53ee8cc1Swenshuai.xi #define GOP_1GS0_HEND                         GOP_REG(GOP_1GS0_OFST+1, 0x05)
683*53ee8cc1Swenshuai.xi #define GOP_1GS0_VSTR                         GOP_REG(GOP_1GS0_OFST+1, 0x06)
684*53ee8cc1Swenshuai.xi #define GOP_1GS0_VEND                         GOP_REG(GOP_1GS0_OFST+1, 0x08)
685*53ee8cc1Swenshuai.xi #define GOP_1GS0_DRAM_RBLK_HSIZE              GOP_REG(GOP_1GS0_OFST+1, 0x09)
686*53ee8cc1Swenshuai.xi #define GOP_1GS0_GWIN_ALPHA01                 GOP_REG(GOP_1GS0_OFST+1, 0x0A)
687*53ee8cc1Swenshuai.xi #define GOP_1GS0_DRAM_VSTR_L                  GOP_REG(GOP_1GS0_OFST+1, 0x0C)
688*53ee8cc1Swenshuai.xi #define GOP_1GS0_DRAM_VSTR_H                  GOP_REG(GOP_1GS0_OFST+1, 0x0D)
689*53ee8cc1Swenshuai.xi #define GOP_1GS0_DRAM_FADE                    GOP_REG(GOP_1GS0_OFST+1, 0x16)
690*53ee8cc1Swenshuai.xi #define GOP_1GS0_3DOSD_SUB_RBLK_L             GOP_REG(GOP_1GS0_OFST+1, 0x1E)
691*53ee8cc1Swenshuai.xi #define GOP_1GS0_3DOSD_SUB_RBLK_H             GOP_REG(GOP_1GS0_OFST+1, 0x1F)
692*53ee8cc1Swenshuai.xi 
693*53ee8cc1Swenshuai.xi #define GOP_1GS1_CTRL0                        GOP_REG(GOP_1GS1_OFST, 0x00)
694*53ee8cc1Swenshuai.xi #define GOP_1GS1_CTRL1                        GOP_REG(GOP_1GS1_OFST, 0x01)
695*53ee8cc1Swenshuai.xi #define GOP_1GS1_RATE                         GOP_REG(GOP_1GS1_OFST, 0x02)
696*53ee8cc1Swenshuai.xi #define GOP_1GS1_PALDATA_L                    GOP_REG(GOP_1GS1_OFST, 0x03)
697*53ee8cc1Swenshuai.xi #define GOP_1GS1_PALDATA_H                    GOP_REG(GOP_1GS1_OFST, 0x04)
698*53ee8cc1Swenshuai.xi #define GOP_1GS1_PALCTRL                      GOP_REG(GOP_1GS1_OFST, 0x05)
699*53ee8cc1Swenshuai.xi #define GOP_1GS1_REGDMA_END                   GOP_REG(GOP_1GS1_OFST, 0x06)
700*53ee8cc1Swenshuai.xi #define GOP_1GS1_REGDMA_STR                   GOP_REG(GOP_1GS1_OFST, 0x07)
701*53ee8cc1Swenshuai.xi #define GOP_1GS1_INT                          GOP_REG(GOP_1GS1_OFST, 0x08)
702*53ee8cc1Swenshuai.xi #define GOP_1GS1_HWSTATE                      GOP_REG(GOP_1GS1_OFST, 0x09)
703*53ee8cc1Swenshuai.xi #define GOP_1GS1_RDMA_HT                      GOP_REG(GOP_1GS1_OFST, 0x0e)
704*53ee8cc1Swenshuai.xi #define GOP_1GS1_HS_PIPE                      GOP_REG(GOP_1GS1_OFST, 0x0f)
705*53ee8cc1Swenshuai.xi #define GOP_1GS1_BRI                          GOP_REG(GOP_1GS1_OFST, 0x11)
706*53ee8cc1Swenshuai.xi #define GOP_1GS1_CON                          GOP_REG(GOP_1GS1_OFST, 0x12)
707*53ee8cc1Swenshuai.xi #define GOP_1GS1_BW                           GOP_REG(GOP_1GS1_OFST, 0x19)
708*53ee8cc1Swenshuai.xi #define GOP_1GS1_TRSCLR_L                     GOP_REG(GOP_1GS1_OFST, 0x24)
709*53ee8cc1Swenshuai.xi #define GOP_1GS1_TRSCLR_H                     GOP_REG(GOP_1GS1_OFST, 0x25)
710*53ee8cc1Swenshuai.xi #define GOP_1GS1_STRCH_HSZ                    GOP_REG(GOP_1GS1_OFST, 0x30)
711*53ee8cc1Swenshuai.xi #define GOP_1GS1_STRCH_VSZ                    GOP_REG(GOP_1GS1_OFST, 0x31)
712*53ee8cc1Swenshuai.xi #define GOP_1GS1_STRCH_HSTR                   GOP_REG(GOP_1GS1_OFST, 0x32)
713*53ee8cc1Swenshuai.xi #define GOP_1GS1_STRCH_VSTR                   GOP_REG(GOP_1GS1_OFST, 0x34)
714*53ee8cc1Swenshuai.xi #define GOP_1GS1_HSTRCH                       GOP_REG(GOP_1GS1_OFST, 0x35)
715*53ee8cc1Swenshuai.xi #define GOP_1GS1_HSTRCH_INI                   GOP_REG(GOP_1GS1_OFST, 0x38)
716*53ee8cc1Swenshuai.xi #define GOP_1GS1_VSTRCH_INI                   GOP_REG(GOP_1GS1_OFST, 0x39)
717*53ee8cc1Swenshuai.xi #define GOP_1GS1_HVStrch_MD                    GOP_REG(GOP_1GS1_OFST, 0x3a)
718*53ee8cc1Swenshuai.xi #define GOP_1GS1_OLDADDR                      GOP_REG(GOP_1GS1_OFST, 0x3b)
719*53ee8cc1Swenshuai.xi #define GOP_1GS1_MULTI_ALPHA                  GOP_REG(GOP_1GS1_OFST, 0x3c)
720*53ee8cc1Swenshuai.xi 
721*53ee8cc1Swenshuai.xi #define GOP_1GS1_GWIN0_CTRL                   GOP_REG(GOP_1GS1_OFST+1, 0x00)
722*53ee8cc1Swenshuai.xi #define GOP_1GS1_DRAM_RBLK_L                  GOP_REG(GOP_1GS1_OFST+1, 0x01)
723*53ee8cc1Swenshuai.xi #define GOP_1GS1_DRAM_RBLK_H                  GOP_REG(GOP_1GS1_OFST+1, 0x02)
724*53ee8cc1Swenshuai.xi #define GOP_1GS1_DEL_PIXEL                    GOP_REG(GOP_1GS1_OFST+1, 0x03)
725*53ee8cc1Swenshuai.xi #define GOP_1GS1_HSTR                         GOP_REG(GOP_1GS1_OFST+1, 0x04)
726*53ee8cc1Swenshuai.xi #define GOP_1GS1_HEND                         GOP_REG(GOP_1GS1_OFST+1, 0x05)
727*53ee8cc1Swenshuai.xi #define GOP_1GS1_VSTR                         GOP_REG(GOP_1GS1_OFST+1, 0x06)
728*53ee8cc1Swenshuai.xi #define GOP_1GS1_VEND                         GOP_REG(GOP_1GS1_OFST+1, 0x08)
729*53ee8cc1Swenshuai.xi #define GOP_1GS1_DRAM_RBLK_HSIZE              GOP_REG(GOP_1GS1_OFST+1, 0x09)
730*53ee8cc1Swenshuai.xi #define GOP_1GS1_GWIN_ALPHA01                 GOP_REG(GOP_1GS1_OFST+1, 0x0A)
731*53ee8cc1Swenshuai.xi #define GOP_1GS1_DRAM_VSTR_L                  GOP_REG(GOP_1GS1_OFST+1, 0x0C)
732*53ee8cc1Swenshuai.xi #define GOP_1GS1_DRAM_VSTR_H                  GOP_REG(GOP_1GS1_OFST+1, 0x0D)
733*53ee8cc1Swenshuai.xi #define GOP_1GS1_DRAM_FADE                    GOP_REG(GOP_1GS1_OFST+1, 0x16)
734*53ee8cc1Swenshuai.xi #define GOP_1GS1_3DOSD_SUB_RBLK_L             GOP_REG(GOP_1GS1_OFST+1, 0x1E)
735*53ee8cc1Swenshuai.xi #define GOP_1GS1_3DOSD_SUB_RBLK_H             GOP_REG(GOP_1GS1_OFST+1, 0x1F)
736*53ee8cc1Swenshuai.xi //-------------------------------------------------------------------------------------------------
737*53ee8cc1Swenshuai.xi //  Type and Structure
738*53ee8cc1Swenshuai.xi //-------------------------------------------------------------------------------------------------
739*53ee8cc1Swenshuai.xi 
740*53ee8cc1Swenshuai.xi //----------------------------------------------------------------------------
741*53ee8cc1Swenshuai.xi // GOP Test Pattern Reg
742*53ee8cc1Swenshuai.xi //----------------------------------------------------------------------------
743*53ee8cc1Swenshuai.xi #define REG_TSTCLR_EN                       GOP_REG(GOP_4G_OFST, 0x00)
744*53ee8cc1Swenshuai.xi #define REG_TSTCLR_ALPHA_EN                 GOP_REG(GOP_4G_OFST+2, 0x00)
745*53ee8cc1Swenshuai.xi #define REG_TLB_TAG_ADDR_L                  GOP_REG(GOP_4G_OFST+2, 0x2C)
746*53ee8cc1Swenshuai.xi #define REG_TLB_TAG_ADDR_H                  GOP_REG(GOP_4G_OFST+2, 0x2D)
747*53ee8cc1Swenshuai.xi #define REG_TLB_TAG_ADDR_RVIEW_L            GOP_REG(GOP_4G_OFST+2, 0x2E)
748*53ee8cc1Swenshuai.xi #define REG_TLB_TAG_ADDR_RVIEW_H            GOP_REG(GOP_4G_OFST+2, 0x2F)
749*53ee8cc1Swenshuai.xi #define REG_TSTCLR_ALPHA                    GOP_REG(GOP_4G_OFST+2, 0x40)
750*53ee8cc1Swenshuai.xi #define REG_R_STC                           GOP_REG(GOP_4G_OFST+2, 0x41)
751*53ee8cc1Swenshuai.xi #define REG_G_STC                           GOP_REG(GOP_4G_OFST+2, 0x48)
752*53ee8cc1Swenshuai.xi #define REG_B_STC                           GOP_REG(GOP_4G_OFST+2, 0x49)
753*53ee8cc1Swenshuai.xi #define REG_TSTCLR_HDUP                     GOP_REG(GOP_4G_OFST+2, 0x01)
754*53ee8cc1Swenshuai.xi #define REG_TSTCLR_VDUP                     GOP_REG(GOP_4G_OFST+2, 0x01)
755*53ee8cc1Swenshuai.xi #define REG_HR_INC                          GOP_REG(GOP_4G_OFST+2, 0x42)
756*53ee8cc1Swenshuai.xi #define REG_HR_INC_SIGNZ                    GOP_REG(GOP_4G_OFST+2, 0x42)
757*53ee8cc1Swenshuai.xi #define REG_HG_INC                          GOP_REG(GOP_4G_OFST+2, 0x43)
758*53ee8cc1Swenshuai.xi #define REG_HG_INC_SIGNZ                    GOP_REG(GOP_4G_OFST+2, 0x43)
759*53ee8cc1Swenshuai.xi #define REG_HB_INC                          GOP_REG(GOP_4G_OFST+2, 0x44)
760*53ee8cc1Swenshuai.xi #define REG_HB_INC_SIGNZ                    GOP_REG(GOP_4G_OFST+2, 0x44)
761*53ee8cc1Swenshuai.xi #define REG_HR_STEP                         GOP_REG(GOP_4G_OFST+2, 0x4A)
762*53ee8cc1Swenshuai.xi #define REG_HG_STEP                         GOP_REG(GOP_4G_OFST+2, 0x4B)
763*53ee8cc1Swenshuai.xi #define REG_HB_STEP                         GOP_REG(GOP_4G_OFST+2, 0x4C)
764*53ee8cc1Swenshuai.xi #define REG_VR_INC                          GOP_REG(GOP_4G_OFST+2, 0x45)
765*53ee8cc1Swenshuai.xi #define REG_VR_INC_SIGNZ                    GOP_REG(GOP_4G_OFST+2, 0x45)
766*53ee8cc1Swenshuai.xi #define REG_VG_INC                          GOP_REG(GOP_4G_OFST+2, 0x46)
767*53ee8cc1Swenshuai.xi #define REG_VG_INC_SIGNZ                    GOP_REG(GOP_4G_OFST+2, 0x46)
768*53ee8cc1Swenshuai.xi #define REG_VB_INC                          GOP_REG(GOP_4G_OFST+2, 0x47)
769*53ee8cc1Swenshuai.xi #define REG_VB_INC_SIGNZ                    GOP_REG(GOP_4G_OFST+2, 0x47)
770*53ee8cc1Swenshuai.xi #define REG_VR_STEP                         GOP_REG(GOP_4G_OFST+2, 0x4D)
771*53ee8cc1Swenshuai.xi #define REG_VG_STEP                         GOP_REG(GOP_4G_OFST+2, 0x4E)
772*53ee8cc1Swenshuai.xi #define REG_VB_STEP                         GOP_REG(GOP_4G_OFST+2, 0x4F)
773*53ee8cc1Swenshuai.xi #define REG_TLB_BASE_ADDR_L                 GOP_REG(GOP_4G_OFST+2, 0x58)
774*53ee8cc1Swenshuai.xi #define REG_TLB_BASE_ADDR_H                 GOP_REG(GOP_4G_OFST+2, 0x59)
775*53ee8cc1Swenshuai.xi #define REG_TLB_BASE_ADDR_RVIEW_L           GOP_REG(GOP_4G_OFST+2, 0x5A)
776*53ee8cc1Swenshuai.xi #define REG_TLB_BASE_ADDR_RVIEW_H           GOP_REG(GOP_4G_OFST+2, 0x5B)
777*53ee8cc1Swenshuai.xi 
778*53ee8cc1Swenshuai.xi #define MASK_TSTCLR_EN                      GOP_BIT6
779*53ee8cc1Swenshuai.xi #define MASK_TSTCLR_ALPHA_EN                GOP_BIT1
780*53ee8cc1Swenshuai.xi #define MASK_TSTCLR_ALPHA                   BMASK(11:8)|BMASK(3:0)
781*53ee8cc1Swenshuai.xi #define MASK_RGB_STC_VALID                  BMASK(7:0)
782*53ee8cc1Swenshuai.xi #define MASK_R_STC                          BMASK(11:8)|BMASK(3:0)
783*53ee8cc1Swenshuai.xi #define MASK_G_STC                          BMASK(11:8)|BMASK(3:0)
784*53ee8cc1Swenshuai.xi #define MASK_B_STC                          BMASK(11:8)|BMASK(3:0)
785*53ee8cc1Swenshuai.xi #define MASK_INI_TSTCLR_EN                  GOP_BIT0
786*53ee8cc1Swenshuai.xi #define MASK_TSTCLR_HDUP                    BMASK(3:2)
787*53ee8cc1Swenshuai.xi #define MASK_TSTCLR_VDUP                    BMASK(1:0)
788*53ee8cc1Swenshuai.xi #define MASK_HR_INC                         BMASK(10:8)|BMASK(3:0)
789*53ee8cc1Swenshuai.xi #define MASK_HR_INC_SIGNZ                   GOP_BIT11
790*53ee8cc1Swenshuai.xi #define MASK_HG_INC                         BMASK(10:8)|BMASK(3:0)
791*53ee8cc1Swenshuai.xi #define MASK_HG_INC_SIGNZ                   GOP_BIT11
792*53ee8cc1Swenshuai.xi #define MASK_HB_INC                         BMASK(10:8)|BMASK(3:0)
793*53ee8cc1Swenshuai.xi #define MASK_HB_INC_SIGNZ                   GOP_BIT11
794*53ee8cc1Swenshuai.xi #define MASK_HR_STEP                        BMASK(11:8)|BMASK(3:0)
795*53ee8cc1Swenshuai.xi #define MASK_HG_STEP                        BMASK(11:8)|BMASK(3:0)
796*53ee8cc1Swenshuai.xi #define MASK_HB_STEP                        BMASK(11:8)|BMASK(3:0)
797*53ee8cc1Swenshuai.xi #define MASK_VR_INC                         BMASK(10:8)|BMASK(3:0)
798*53ee8cc1Swenshuai.xi #define MASK_VR_INC_SIGNZ                   GOP_BIT11
799*53ee8cc1Swenshuai.xi #define MASK_VG_INC                         BMASK(10:8)|BMASK(3:0)
800*53ee8cc1Swenshuai.xi #define MASK_VG_INC_SIGNZ                   GOP_BIT11
801*53ee8cc1Swenshuai.xi #define MASK_VB_INC                         BMASK(10:8)|BMASK(3:0)
802*53ee8cc1Swenshuai.xi #define MASK_VB_INC_SIGNZ                   GOP_BIT11
803*53ee8cc1Swenshuai.xi #define MASK_VR_STEP                        BMASK(11:8)|BMASK(3:0)
804*53ee8cc1Swenshuai.xi #define MASK_VG_STEP                        BMASK(11:8)|BMASK(3:0)
805*53ee8cc1Swenshuai.xi #define MASK_VB_STEP                        BMASK(11:8)|BMASK(3:0)
806*53ee8cc1Swenshuai.xi 
807*53ee8cc1Swenshuai.xi #define SHIFT_TSTCLR_EN                     6
808*53ee8cc1Swenshuai.xi #define SHIFT_TSTCLR_ALPHA_EN               1
809*53ee8cc1Swenshuai.xi #define SHIFT_TSTCLR_ALPHA                  8
810*53ee8cc1Swenshuai.xi #define SHIFT_R_STC                         0
811*53ee8cc1Swenshuai.xi #define SHIFT_G_STC                         0
812*53ee8cc1Swenshuai.xi #define SHIFT_B_STC                         0
813*53ee8cc1Swenshuai.xi #define SHIFT_INI_TSTCLR_EN                 0
814*53ee8cc1Swenshuai.xi #define SHIFT_TSTCLR_HDUP                   2
815*53ee8cc1Swenshuai.xi #define SHIFT_TSTCLR_VDUP                   0
816*53ee8cc1Swenshuai.xi #define SHIFT_HR_INC                        0
817*53ee8cc1Swenshuai.xi #define SHIFT_HR_INC_SIGNZ                  11
818*53ee8cc1Swenshuai.xi #define SHIFT_HG_INC                        0
819*53ee8cc1Swenshuai.xi #define SHIFT_HG_INC_SIGNZ                  11
820*53ee8cc1Swenshuai.xi #define SHIFT_HB_INC                        0
821*53ee8cc1Swenshuai.xi #define SHIFT_HB_INC_SIGNZ                  11
822*53ee8cc1Swenshuai.xi #define SHIFT_HR_STEP                       0
823*53ee8cc1Swenshuai.xi #define SHIFT_HG_STEP                       0
824*53ee8cc1Swenshuai.xi #define SHIFT_HB_STEP                       0
825*53ee8cc1Swenshuai.xi #define SHIFT_VR_INC                        0
826*53ee8cc1Swenshuai.xi #define SHIFT_VR_INC_SIGNZ                  11
827*53ee8cc1Swenshuai.xi #define SHIFT_VG_INC                        0
828*53ee8cc1Swenshuai.xi #define SHIFT_VG_INC_SIGNZ                  11
829*53ee8cc1Swenshuai.xi #define SHIFT_VB_INC                        0
830*53ee8cc1Swenshuai.xi #define SHIFT_VB_INC_SIGNZ                  11
831*53ee8cc1Swenshuai.xi #define SHIFT_VR_STEP                       0
832*53ee8cc1Swenshuai.xi #define SHIFT_VG_STEP                       0
833*53ee8cc1Swenshuai.xi #define SHIFT_VB_STEP                       0
834*53ee8cc1Swenshuai.xi #endif // _REG_GOP_H_
835