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MStar hereby reserves the 91 // rights to any and all damages, losses, costs and expenses resulting therefrom. 92 // 93 //////////////////////////////////////////////////////////////////////////////// 94 95 #ifndef _REG_GOP_H_ 96 #define _REG_GOP_H_ 97 98 //------------------------------------------------------------------------------------------------- 99 // Hardware Capability 100 //------------------------------------------------------------------------------------------------- 101 102 103 //------------------------------------------------------------------------------------------------- 104 // Macro and Define 105 //------------------------------------------------------------------------------------------------- 106 //---------------------------------------------------------------------------- 107 // HW IP Reg Base Adr 108 //---------------------------------------------------------------------------- 109 #define GOP_REG_BASE 0x1F00 110 #define GE_REG_BASE 0x2800 111 #define SC1_REG_BASE 0x2F00 112 #define CKG_REG_BASE 0x0B00 113 #define MIU_REG_BASE 0x1200 114 #define MVOP_REG_BASE 0x1400 115 #define SC1_DIRREG_BASE 0x130000 116 //---------------------------------------------------------------------------- 117 // Scaler Reg 118 //---------------------------------------------------------------------------- 119 #define XC_REG(bk, reg) (SC1_REG_BASE+((MS_U32)(bk)<<16) + (reg) * 2) 120 121 #define REG_SC_BK00_00_L XC_REG(0x00, 0x00) 122 #define REG_SC_BK00_05_L XC_REG(0x00, 0x05) 123 #define REG_SC_BK00_06_L XC_REG(0x00, 0x06) 124 #define REG_SC_BK01_02_L XC_REG(0x01, 0x02) 125 #define REG_SC_BK02_5F_L XC_REG(0x02, 0x5F) 126 #define REG_SC_BK10_23_L XC_REG(0x10, 0x23) 127 #define REG_SC_BK10_50_L XC_REG(0x10, 0x50) 128 #define REG_SC_BK10_5B_L XC_REG(0x10, 0x5B) 129 #define REG_SC_BK12_03_L XC_REG(0x12, 0x03) 130 #define REG_SC_BK20_10_L XC_REG(0x20, 0x10) 131 #define REG_SC_BK0F_2B_L XC_REG(0x0F, 0x2B) 132 #define REG_SC_BK3E_28_L XC_REG(0x3E, 0x28) 133 #define REG_SC_BK37_22_L XC_REG(0x37, 0x22) 134 #define REG_SC_BK37_24_L XC_REG(0x37, 0x24) 135 #define REG_SC_BK3D_0D_L XC_REG(0x3D, 0x0D) 136 #define REG_SC_BK7F_10_L XC_REG(0x7F, 0x10) 137 138 #define GOP_SC_BANKSEL REG_SC_BK00_00_L 139 #define GOP_SC_CHANNELSYNC REG_SC_BK00_05_L 140 #define IPMUX0_BLENDING_ENABLE GOP_BIT13 141 #define IPMUX1_BLENDING_ENABLE GOP_BIT12 142 #define GOP_SC_GOPEN REG_SC_BK00_06_L 143 #define GOP_SC_IP_SYNC REG_SC_BK01_02_L 144 #define GOP_SC_IP2GOP_SRCSEL REG_SC_BK02_5F_L 145 #define GOP_SC_VOPNBL REG_SC_BK10_23_L 146 #define GOP_SC_GOPEN_DWIN REG_SC_BK10_50_L 147 #define GOP_SC_GOPENMODE1 REG_SC_BK10_5B_L 148 #define GOP_SC_MIRRORCFG REG_SC_BK12_03_L 149 #define GOP_SC_OSD_CHECK_ALPHA REG_SC_BK0F_2B_L 150 #define GOP_SC_GOPEN_BYPASS REG_SC_BK3E_28_L 151 #define GOP_SC_OCMIXER REG_SC_BK37_22_L 152 #define GOP_SC_OCMISC REG_SC_BK37_24_L 153 #define GOP_SC_GOPSC_SRAM_CTRL REG_SC_BK3D_0D_L 154 155 //---------------------------------------------------------------------------- 156 // MVOP Reg 157 //---------------------------------------------------------------------------- 158 #define GOP_MVOP_MIRRORCFG (MVOP_REG_BASE+0x76) 159 160 161 162 //---------------------------------------------------------------------------- 163 // GE Reg 164 //---------------------------------------------------------------------------- 165 #define GOP_GE_FMT_BLT (GE_REG_BASE+(0x01*2)) 166 #define GOP_GE_EN_CMDQ BIT(0) 167 #define GOP_GE_EN_VCMDQ BIT(1) 168 169 #define GOP_GE_VQ_FIFO_STATUS_L (GE_REG_BASE+(0x04*2)) 170 #define GOP_GE_VQ_FIFO_STATUS_H (GE_REG_BASE+(0x05*2)) 171 172 #define GOP_GE_STATUS (GE_REG_BASE+(0x07*2)) 173 #define GOP_GE_BUSY BIT(0) 174 #define GOP_GE_CMDQ1_STATUS BMASK(7:3) 175 #define GOP_GE_CMDQ2_STATUS BMASK(15:11) 176 177 #define GOP_GE_TAG (GE_REG_BASE+(0x2C*2)) 178 179 #define GOP_GE_DBBASE0 (GE_REG_BASE+(0x26*2)) 180 #define GOP_GE_DBBASE1 (GE_REG_BASE+(0x27*2)) 181 #define GOP_GE_DBPIT (GE_REG_BASE+(0x33*2)) 182 #define GOP_GE_FBFMT (GE_REG_BASE+(0x34*2)) 183 #define GOP_GE_SRCW (GE_REG_BASE+(0x6e*2)) 184 #define GOP_GE_SRCH (GE_REG_BASE+(0x6f*2)) 185 186 187 //---------------------------------------------------------------------------- 188 // ChipTop Reg 189 //---------------------------------------------------------------------------- 190 /* GOP0 and GOP1 CLK */ 191 #define GOP_GOPCLK (CKG_REG_BASE+0x80) 192 #define CKG_GOPG0_DISABLE_CLK ~(GOP_BIT0) 193 #define CKG_GOPG0_ODCLK (0<<2) 194 #define CKG_GOPG0_IDCLK2 (1 << 2) 195 #define CKG_GOPG0_IDCLK1 (3 << 2) 196 #define CKG_GOPG0_MASK (GOP_BIT4 | GOP_BIT3 | GOP_BIT2) 197 #define CKG_GOPG1_MASK (GOP_BIT12 | GOP_BIT11 | GOP_BIT10) 198 #define CKG_GOPG1_DISABLE_CLK ~(GOP_BIT8) 199 #define CKG_GOPG1_ODCLK (0 << 10) 200 #define CKG_GOPG1_IDCLK2 (1 << 10) 201 #define CKG_GOPG1_IDCLK1 (3 << 10) 202 203 #define CKG_GOPG0_SCALING (CKG_REG_BASE+0x88) 204 #define CKG_GOPG0_MG (CKG_REG_BASE+0xFE) 205 #define CKG_GOPG0_MG_MASK (GOP_BIT3 | GOP_BIT2) 206 #define CKG_GOPG2_MG_MASK (GOP_BIT7 | GOP_BIT6) 207 208 /* GOP2 and GOPDWIN CLK */ 209 #define GOP_GOP2CLK (CKG_REG_BASE+0x82) 210 #define CKG_GOPG2_DISABLE_CLK ~(GOP_BIT0) 211 #define CKG_GOPG2_ODCLK (0<<2) 212 #define CKG_GOPG2_IDCLK2 (1 << 2) 213 #define CKG_GOPG2_IDCLK1 (3 << 2) 214 #define CKG_GOPG2_MASK (GOP_BIT4 | GOP_BIT3 | GOP_BIT2) 215 #define CKG_GOPD_MASK (GOP_BIT12 | GOP_BIT11 | GOP_BIT10) 216 #define CKG_GOPD_CLK_IDCLK2 (0 << 10) 217 #define CKG_GOPD_CLK_ODCLK (1 << 10) 218 #define CKG_GOPD_CLK_DC0CLK (2 << 10) 219 #define CKG_GOPD_CLK_SUBDC0CLK (3 << 10) 220 221 222 /* GOP3 CLK*/ 223 #define GOP_GOP3CLK (CKG_REG_BASE+0x84) 224 #define CKG_GOPG3_ODCLK (0<<2) 225 #define CKG_GOPG3_IDCLK2 (1 << 2) 226 #define CKG_GOPG3_IDCLK1 (3 << 2) 227 #define CKG_GOPG3_MASK (GOP_BIT4 | GOP_BIT3 | GOP_BIT2) 228 #define CKG_GOPD_DISABLE_CLK ~(GOP_BIT8) 229 230 /* GOP4 CLK*/ 231 #define GOP_GOP4CLK (CKG_REG_BASE+(0x7E<<1)) 232 #define CKG_GOPG4_ODCLK (0 << 10) 233 #define CKG_GOPG4_IDCLK2 (1 << 10) 234 #define CKG_GOPG4_IDCLK1 (2 << 10) 235 #define CKG_GOPG4_OCC_FRCCLK (3 << 10) 236 #define CKG_GOPG4_MIXERCLK_VE (4 << 10) 237 #define CKG_GOPG4_MASK (GOP_BIT12 | GOP_BIT11 | GOP_BIT10) 238 239 240 /* SRAM CLK */ 241 #define GOP_SRAMCLK (CKG_REG_BASE+0x84) 242 #define CKG_SRAM0_DISABLE_CLK (GOP_BIT0) 243 #define CKG_SRAM1_DISABLE_CLK (GOP_BIT8) 244 #define CKG_SRAM0_MASK (GOP_BIT0|GOP_BIT1) 245 #define CKG_SRAM1_MASK (GOP_BIT8|GOP_BIT9) 246 247 248 //---------------------------------------------------------------------------- 249 // MIU Reg 250 //---------------------------------------------------------------------------- 251 #define GOP_CLIENT_REG 0x7D 252 #define GOP_MIU_GROUP1 REG_SC_BK7F_10_L 253 254 /*Define each gop miu clint bit*/ 255 #define GOP_MIU_CLIENT_DWIN 0xff 256 #define GOP_MIU_CLIENT_GOP0 0x5 257 #define GOP_MIU_CLIENT_GOP1 0x6 258 #define GOP_MIU_CLIENT_GOP2 0x7 259 #define GOP_MIU_CLIENT_GOP3 0xF 260 #define GOP_MIU_CLIENT_GOP4 0xff 261 #define GOP_MIU_CLIENT_GOP5 0xff 262 //---------------------------------------------------------------------------- 263 // GOP Reg 264 //---------------------------------------------------------------------------- 265 #define GOP_REG(bk, reg) (GOP_REG_BASE+((MS_U32)(bk)<<16) + (reg) * 2) 266 #define __GOP_REG(reg) (GOP_REG_BASE+(reg) * 2) 267 #define GOP_REG_DIRECT_BASE (0x120200) 268 #define GOP_REG_VAL(x) (1<<x) 269 270 //MUX Setting 271 #define GOP_MUX_SHIFT 0x2 272 #define GOP_REGMUX_MASK BMASK((GOP_MUX_SHIFT-1):0) 273 #define GOP_MUX0_MASK (GOP_REGMUX_MASK<<(GOP_MUX_SHIFT*0)) 274 #define GOP_MUX1_MASK (GOP_REGMUX_MASK<<(GOP_MUX_SHIFT*1)) 275 #define GOP_MUX2_MASK (GOP_REGMUX_MASK<<(GOP_MUX_SHIFT*2)) 276 #define GOP_MUX3_MASK (GOP_REGMUX_MASK<<(GOP_MUX_SHIFT*3)) 277 278 //IP and VOP MUX Setting 279 #define GOP_IP_MAIN_MUX_SHIFT 0 280 #define GOP_IP_MAIN_MUX_MASK (BMASK((GOP_MUX_SHIFT-1):0))<<GOP_IP_MAIN_MUX_SHIFT 281 #define GOP_IP_SUB_MUX_SHIFT 3 282 #define GOP_IP_SUB_MUX_MASK (BMASK((GOP_MUX_SHIFT-1):0))<<GOP_IP_SUB_MUX_SHIFT 283 #define GOP_IP_VOP0_MUX_SHIFT 6 284 #define GOP_IP_VOP0_MUX_MASK (BMASK((GOP_MUX_SHIFT-1):0))<<GOP_IP_VOP0_MUX_SHIFT 285 #define GOP_IP_VOP1_MUX_SHIFT 9 286 #define GOP_IP_VOP1_MUX_MASK (BMASK((GOP_MUX_SHIFT-1):0))<<GOP_IP_VOP1_MUX_SHIFT 287 288 // for gwin color format mask 289 #define GOP_REG_COLORTYPE_MASK BMASK(3:0) 290 #define GOP_REG_COLORTYPE_SHIFT 4 291 292 #define GOP_BANK_OFFSET 0x3 293 #define GOP_4G_OFST 0x0 294 #define GOP_2G_OFST 0x3 295 #define GOP_1G_OFST 0x8 296 #define GOP_1GX_OFST 0xB 297 #define GOP_DW_OFST 0x6 298 #define GOP_1GS0_OFST 0xe 299 #define GOP_1GS1_OFST 0x11 300 301 #define GOP_OFFSET_WR 8 302 #define GOP_VAL_WR GOP_REG_VAL(GOP_OFFSET_WR) 303 #define GOP_OFFSET_FWR 9 304 #define GOP_VAL_FWR GOP_REG_VAL(GOP_OFFSET_FWR) 305 #define GOP_OFFSET_FCLR 11 306 #define GOP_VAL_FCL GOP_REG_VAL(GOP_OFFSET_FCLR) 307 #define GOP4G_OFFSET_WR_ACK 12 308 #define GOP4G_VAL_WR_ACK GOP_REG_VAL(GOP4G_OFFSET_WR_ACK) 309 #define GOP2G_OFFSET_WR_ACK 13 310 #define GOP2G_VAL_WR_ACK GOP_REG_VAL(GOP2G_OFFSET_WR_ACK) 311 #define GOPD_OFFSET_WR_ACK 14 312 #define GOPD_VAL_WR_ACK GOP_REG_VAL(GOPD_OFFSET_WR_ACK) 313 #define GOP1G_OFFSET_WR_ACK 15 314 #define GOP1G_VAL_WR_ACK GOP_REG_VAL(GOPD_OFFSET_WR_ACK) 315 #define GOP_VAL_ACK(x) GOP_REG_VAL(GOP4G_OFFSET_WR_ACK+x) 316 317 #define GOP_4G_CTRL0 GOP_REG(GOP_4G_OFST, 0x00) 318 #define GOP_4G_CTRL1 GOP_REG(GOP_4G_OFST, 0x01) 319 #define GOP_4G_RATE GOP_REG(GOP_4G_OFST, 0x02) 320 #define GOP_4G_PALDATA_L GOP_REG(GOP_4G_OFST, 0x03) 321 #define GOP_4G_PALDATA_H GOP_REG(GOP_4G_OFST, 0x04) 322 #define GOP_4G_PALCTRL GOP_REG(GOP_4G_OFST, 0x05) 323 #define GOP_4G_REGDMA_END GOP_REG(GOP_4G_OFST, 0x06) 324 #define GOP_4G_REGDMA_STR GOP_REG(GOP_4G_OFST, 0x07) 325 #define GOP_4G_INT GOP_REG(GOP_4G_OFST, 0x08) 326 #define GOP_4G_HWSTATE GOP_REG(GOP_4G_OFST, 0x09) 327 #define GOP_4G_SVM_HSTR GOP_REG(GOP_4G_OFST, 0x0a) 328 #define GOP_4G_SVM_HEND GOP_REG(GOP_4G_OFST, 0x0b) 329 #define GOP_4G_SVM_VSTR GOP_REG(GOP_4G_OFST, 0x0c) 330 #define GOP_4G_SVM_VEND GOP_REG(GOP_4G_OFST, 0x0d) 331 #define GOP_4G_RDMA_HT GOP_REG(GOP_4G_OFST, 0x0e) 332 #define GOP_4G_HS_PIPE GOP_REG(GOP_4G_OFST, 0x0f) 333 #define GOP_4G_SLOW GOP_REG(GOP_4G_OFST, 0x10) 334 #define GOP_4G_BRI GOP_REG(GOP_4G_OFST, 0x11) 335 #define GOP_4G_CON GOP_REG(GOP_4G_OFST, 0x12) 336 #define GOP_4G_BW GOP_REG(GOP_4G_OFST, 0x19) 337 #define GOP_4G_NEW_BW GOP_REG(GOP_4G_OFST, 0x1C) 338 #define GOP_4G_SRAM_BORROW GOP_REG(GOP_4G_OFST, 0x1D) 339 #define GOP_4G_3D_MIDDLE GOP_REG(GOP_4G_OFST, 0x1E) 340 #define GOP_4G_PRI0 GOP_REG(GOP_4G_OFST, 0x20) 341 #define GOP_4G_DUMMY_22 GOP_REG(GOP_4G_OFST, 0x22) 342 #define GOP_4G_BOT_HS GOP_REG(GOP_4G_OFST, 0x23) 343 #define GOP_4G_TRSCLR_L GOP_REG(GOP_4G_OFST, 0x24) 344 #define GOP_4G_TRSCLR_H GOP_REG(GOP_4G_OFST, 0x25) 345 #define GOP_4G_YUV_SWAP GOP_REG(GOP_4G_OFST, 0x28) 346 #define GOP_4G_STRCH_HSZ GOP_REG(GOP_4G_OFST, 0x30) 347 #define GOP_4G_STRCH_VSZ GOP_REG(GOP_4G_OFST, 0x31) 348 #define GOP_4G_STRCH_HSTR GOP_REG(GOP_4G_OFST, 0x32) 349 #define GOP_4G_STRCH_VSTR GOP_REG(GOP_4G_OFST, 0x34) 350 #define GOP_4G_HSTRCH GOP_REG(GOP_4G_OFST, 0x35) 351 #define GOP_4G_VSTRCH GOP_REG(GOP_4G_OFST, 0x36) 352 #define GOP_4G_HSTRCH_INI GOP_REG(GOP_4G_OFST, 0x38) 353 #define GOP_4G_VSTRCH_INI GOP_REG(GOP_4G_OFST, 0x39) 354 #define GOP_4G_HVSTRCHMD GOP_REG(GOP_4G_OFST, 0x3a) 355 #define GOP_4G_OLDADDR GOP_REG(GOP_4G_OFST, 0x3b) 356 #define GOP_4G_MULTI_ALPHA GOP_REG(GOP_4G_OFST, 0x3c) 357 #define GOP_4G_BANK_FWR GOP_REG(GOP_4G_OFST, 0x50) 358 #define GOP_4G_BANK_HVAILDSIZE GOP_REG(GOP_4G_OFST, 0x52) 359 #define GOP_4G_BANK_VVAILDSIZE GOP_REG(GOP_4G_OFST, 0x53) 360 #define GOP_4G_SCALING_H_OUTPUTSIZE GOP_REG(GOP_4G_OFST, 0x56) 361 #define GOP_4G_SCALING_HRATIO_L GOP_REG(GOP_4G_OFST, 0x59) //GOP scaling down ratio dst / out * 2^20 362 #define GOP_4G_SCALING_HRATIO_H GOP_REG(GOP_4G_OFST, 0x5A) 363 #define GOP_4G_SCALING_CFG GOP_REG(GOP_4G_OFST, 0x5B) 364 #define GOP_4G_SCALING_VRATIO_L GOP_REG(GOP_4G_OFST, 0x5C) //GOP scaling down ratio dst / out * 2^20 365 #define GOP_4G_SCALING_VRATIO_H GOP_REG(GOP_4G_OFST, 0x5D) 366 367 368 #define GOP_4G_RBLK0_VOFFL GOP_REG(GOP_4G_OFST, 0x60) 369 #define GOP_4G_RBLK0_VOFFH GOP_REG(GOP_4G_OFST, 0x61) 370 #define GOP_4G_RBLK1_VOFFL GOP_REG(GOP_4G_OFST, 0x62) 371 #define GOP_4G_RBLK1_VOFFH GOP_REG(GOP_4G_OFST, 0x63) 372 #define GOP_4G_RBLK2_VOFFL GOP_REG(GOP_4G_OFST, 0x64) 373 #define GOP_4G_RBLK2_VOFFH GOP_REG(GOP_4G_OFST, 0x65) 374 #define GOP_4G_RBLK3_VOFFL GOP_REG(GOP_4G_OFST, 0x66) 375 #define GOP_4G_RBLK3_VOFFH GOP_REG(GOP_4G_OFST, 0x67) 376 #define GOP_4G_RBLK0_HOFF GOP_REG(GOP_4G_OFST, 0x70) 377 #define GOP_4G_RBLK1_HOFF GOP_REG(GOP_4G_OFST, 0x71) 378 #define GOP_4G_RBLK2_HOFF GOP_REG(GOP_4G_OFST, 0x72) 379 #define GOP_4G_RBLK3_HOFF GOP_REG(GOP_4G_OFST, 0x73) 380 #define GOP_4G_REGDMA_EN GOP_REG(GOP_4G_OFST, 0x78) 381 #define GOP_MUX_IPVOP __GOP_REG(0x77) 382 #define GOP_MUX_BYPASS __GOP_REG(0x7B) 383 #define GOP_MUX __GOP_REG(0x7E) 384 #define GOP_BAK_SEL __GOP_REG(0x7F) 385 386 #define GOP_4G_GWIN0_CTRL(id) GOP_REG(GOP_4G_OFST+1, 0x00 + (0x20*((id)%MAX_GOP0_GWIN))) 387 #define GOP_4G_DRAM_RBLK_L(id) GOP_REG(GOP_4G_OFST+1, 0x01 + (0x20*((id)%MAX_GOP0_GWIN))) 388 #define GOP_4G_DRAM_RBLK_H(id) GOP_REG(GOP_4G_OFST+1, 0x02 + (0x20*((id)%MAX_GOP0_GWIN))) 389 #define GOP_4G_DEL_PIXEL(id) GOP_REG(GOP_4G_OFST+1, 0x03 + (0x20*((id)%MAX_GOP1_GWIN))) 390 #define GOP_4G_HSTR(id) GOP_REG(GOP_4G_OFST+1, 0x04 + (0x20*((id)%MAX_GOP0_GWIN))) 391 #define GOP_4G_HEND(id) GOP_REG(GOP_4G_OFST+1, 0x05 + (0x20*((id)%MAX_GOP0_GWIN))) 392 #define GOP_4G_VSTR(id) GOP_REG(GOP_4G_OFST+1, 0x06 + (0x20*((id)%MAX_GOP0_GWIN))) 393 #define GOP_4G_GWIN_MIDDLE(id) GOP_REG(GOP_4G_OFST+1, 0x07 + (0x20*((id)%MAX_GOP0_GWIN))) 394 #define GOP_4G_VEND(id) GOP_REG(GOP_4G_OFST+1, 0x08 + (0x20*((id)%MAX_GOP0_GWIN))) 395 #define GOP_4G_DRAM_RBLK_HSIZE(id) GOP_REG(GOP_4G_OFST+1, 0x09 + (0x20*((id)%MAX_GOP0_GWIN))) 396 #define GOP_4G_GWIN_ALPHA01(id) GOP_REG(GOP_4G_OFST+1, 0x0A + (0x20*((id)%MAX_GOP0_GWIN))) 397 #define GOP_4G_DRAM_VSTR_L(id) GOP_REG(GOP_4G_OFST+1, 0x0C + (0x20*((id)%MAX_GOP0_GWIN))) 398 #define GOP_4G_DRAM_VSTR_H(id) GOP_REG(GOP_4G_OFST+1, 0x0D + (0x20*((id)%MAX_GOP0_GWIN))) 399 #define GOP_4G_DRAM_HSTR(id) GOP_REG(GOP_4G_OFST+1, 0x0E + (0x20*((id)%MAX_GOP0_GWIN))) 400 #define GOP_4G_DRAM_RBLK_SIZE_L(id) GOP_REG(GOP_4G_OFST+1, 0x10 + (0x20*((id)%MAX_GOP0_GWIN))) 401 #define GOP_4G_DRAM_RBLK_SIZE_H(id) GOP_REG(GOP_4G_OFST+1, 0x11 + (0x20*((id)%MAX_GOP0_GWIN))) 402 #define GOP_4G_DRAM_RLEN_L(id) GOP_REG(GOP_4G_OFST+1, 0x12 + (0x20*((id)%MAX_GOP0_GWIN))) 403 #define GOP_4G_DRAM_RLEN_H(id) GOP_REG(GOP_4G_OFST+1, 0x13 + (0x20*((id)%MAX_GOP0_GWIN))) 404 #define GOP_4G_DRAM_HVSTOP_L(id) GOP_REG(GOP_4G_OFST+1, 0x14 + (0x20*((id)%MAX_GOP0_GWIN))) 405 #define GOP_4G_DRAM_HVSTOP_H(id) GOP_REG(GOP_4G_OFST+1, 0x15 + (0x20*((id)%MAX_GOP0_GWIN))) 406 #define GOP_4G_DRAM_FADE(id) GOP_REG(GOP_4G_OFST+1, 0x16 + (0x20*((id)%MAX_GOP0_GWIN))) 407 #define GOP_4G_BG_CLR(id) GOP_REG(GOP_4G_OFST+1, 0x18 + (0x20*((id)%MAX_GOP0_GWIN))) 408 #define GOP_4G_BG_HSTR(id) GOP_REG(GOP_4G_OFST+1, 0x19 + (0x20*((id)%MAX_GOP0_GWIN))) 409 #define GOP_4G_BG_HEND(id) GOP_REG(GOP_4G_OFST+1, 0x1a + (0x20*((id)%MAX_GOP0_GWIN))) 410 #define GOP_4G_BG_VSTR(id) GOP_REG(GOP_4G_OFST+1, 0x1C + (0x20*((id)%MAX_GOP0_GWIN))) 411 #define GOP_4G_BG_VEND(id) GOP_REG(GOP_4G_OFST+1, 0x1D + (0x20*((id)%MAX_GOP0_GWIN))) 412 #define GOP_4G_3DOSD_SUB_RBLK_L(id) GOP_REG(GOP_4G_OFST+1, 0x1E + (0x20*((id)%MAX_GOP0_GWIN))) 413 #define GOP_4G_3DOSD_SUB_RBLK_H(id) GOP_REG(GOP_4G_OFST+1, 0x1F + (0x20*((id)%MAX_GOP0_GWIN))) 414 415 416 #define GOP_2G_CTRL0 GOP_REG(GOP_2G_OFST, 0x00) 417 #define GOP_2G_CTRL1 GOP_REG(GOP_2G_OFST, 0x01) 418 #define GOP_2G_RATE GOP_REG(GOP_2G_OFST, 0x02) 419 #define GOP_2G_PALDATA_L GOP_REG(GOP_2G_OFST, 0x03) 420 #define GOP_2G_PALDATA_H GOP_REG(GOP_2G_OFST, 0x04) 421 #define GOP_2G_PALCTRL GOP_REG(GOP_2G_OFST, 0x05) 422 #define GOP_2G_REGDMA_END GOP_REG(GOP_2G_OFST, 0x06) 423 #define GOP_2G_REGDMA_STR GOP_REG(GOP_2G_OFST, 0x07) 424 #define GOP_2G_INT GOP_REG(GOP_2G_OFST, 0x08) 425 #define GOP_2G_HWSTATE GOP_REG(GOP_2G_OFST, 0x09) 426 #define GOP_2G_RDMA_HT GOP_REG(GOP_2G_OFST, 0x0e) 427 #define GOP_2G_HS_PIPE GOP_REG(GOP_2G_OFST, 0x0f) 428 #define GOP_2G_SLOW GOP_REG(GOP_2G_OFST, 0x10) 429 #define GOP_2G_BRI GOP_REG(GOP_2G_OFST, 0x11) 430 #define GOP_2G_CON GOP_REG(GOP_2G_OFST, 0x12) 431 #define GOP_2G_BW GOP_REG(GOP_2G_OFST, 0x19) 432 #define GOP_2G_3D_MIDDLE GOP_REG(GOP_2G_OFST, 0x1E) 433 #define GOP_2G_PRI0 GOP_REG(GOP_2G_OFST, 0x20) 434 #define GOP_2G_TRSCLR_L GOP_REG(GOP_2G_OFST, 0x24) 435 #define GOP_2G_TRSCLR_H GOP_REG(GOP_2G_OFST, 0x25) 436 #define GOP_2G_STRCH_HSZ GOP_REG(GOP_2G_OFST, 0x30) 437 #define GOP_2G_STRCH_VSZ GOP_REG(GOP_2G_OFST, 0x31) 438 #define GOP_2G_STRCH_HSTR GOP_REG(GOP_2G_OFST, 0x32) 439 #define GOP_2G_STRCH_VSTR GOP_REG(GOP_2G_OFST, 0x34) 440 #define GOP_2G_HSTRCH GOP_REG(GOP_2G_OFST, 0x35) 441 #define GOP_2G_VSTRCH GOP_REG(GOP_2G_OFST, 0x36) 442 #define GOP_2G_HSTRCH_INI GOP_REG(GOP_2G_OFST, 0x38) 443 #define GOP_2G_VSTRCH_INI GOP_REG(GOP_2G_OFST, 0x39) 444 #define GOP_2G_HVStrch_MD GOP_REG(GOP_2G_OFST, 0x3a) 445 #define GOP_2G_OLDADDR GOP_REG(GOP_2G_OFST, 0x3b) 446 #define GOP_2G_MULTI_ALPHA GOP_REG(GOP_2G_OFST, 0x3c) 447 #define GOP_2G_REGDMA_EN GOP_REG(GOP_2G_OFST, 0x78) 448 449 450 #define GOP_2G_GWIN0_CTRL(id) GOP_REG(GOP_2G_OFST+1, 0x00 + (0x20*((id)%MAX_GOP1_GWIN))) 451 #define GOP_2G_GWIN_CTRL(id) GOP_REG(GOP_2G_OFST+1, 0x00 + (0x20*((id)%MAX_GOP1_GWIN))) 452 #define GOP_2G_DRAM_RBLK_L(id) GOP_REG(GOP_2G_OFST+1, 0x01 + (0x20*((id)%MAX_GOP1_GWIN))) 453 #define GOP_2G_DRAM_RBLK_H(id) GOP_REG(GOP_2G_OFST+1, 0x02 + (0x20*((id)%MAX_GOP1_GWIN))) 454 #define GOP_2G_DEL_PIXEL(id) GOP_REG(GOP_2G_OFST+1, 0x03 + (0x20*((id)%MAX_GOP1_GWIN))) 455 #define GOP_2G_HSTR(id) GOP_REG(GOP_2G_OFST+1, 0x04 + (0x20*((id)%MAX_GOP1_GWIN))) 456 #define GOP_2G_HEND(id) GOP_REG(GOP_2G_OFST+1, 0x05 + (0x20*((id)%MAX_GOP1_GWIN))) 457 #define GOP_2G_VSTR(id) GOP_REG(GOP_2G_OFST+1, 0x06 + (0x20*((id)%MAX_GOP1_GWIN))) 458 #define GOP_2G_VEND(id) GOP_REG(GOP_2G_OFST+1, 0x08 + (0x20*((id)%MAX_GOP1_GWIN))) 459 #define GOP_2G_DRAM_RBLK_HSIZE(id) GOP_REG(GOP_2G_OFST+1, 0x09 + (0x20*((id)%MAX_GOP1_GWIN))) 460 #define GOP_2G_GWIN_ALPHA01(id) GOP_REG(GOP_2G_OFST+1, 0x0A + (0x20*((id)%MAX_GOP1_GWIN))) 461 #define GOP_2G_DRAM_VSTR_L(id) GOP_REG(GOP_2G_OFST+1, 0x0C + (0x20*((id)%MAX_GOP1_GWIN))) 462 #define GOP_2G_DRAM_VSTR_H(id) GOP_REG(GOP_2G_OFST+1, 0x0D + (0x20*((id)%MAX_GOP1_GWIN))) 463 #define GOP_2G_DRAM_FADE(id) GOP_REG(GOP_2G_OFST+1, 0x16 + (0x20*((id)%MAX_GOP1_GWIN))) 464 #define GOP_2G_3DOSD_SUB_RBLK_L(id) GOP_REG(GOP_2G_OFST+1, 0x1E + (0x20*((id)%MAX_GOP1_GWIN))) 465 #define GOP_2G_3DOSD_SUB_RBLK_H(id) GOP_REG(GOP_2G_OFST+1, 0x1F + (0x20*((id)%MAX_GOP1_GWIN))) 466 467 // DWIN reg 468 #define GOP_DW_CTL0_EN GOP_REG(GOP_DW_OFST, 0x00) 469 #define GOP_DWIN_EN (0x00) 470 #define GOP_DWIN_EN_VAL GOP_REG_VAL(GOP_DWIN_EN) 471 #define GOP_DWIN_SHOT (0x07) 472 #define GOP_DWIN_SHOT_VAL GOP_REG_VAL(GOP_DWIN_SHOT) 473 474 #define GOP_DW_LSTR_WBE GOP_REG(GOP_DW_OFST, 0x01) 475 #define GOP_DW_INT_MASK GOP_REG(GOP_DW_OFST, 0x02) 476 #define GOP_DW_DEBUG GOP_REG(GOP_DW_OFST, 0x03) 477 #define GOP_DW_ALPHA GOP_REG(GOP_DW_OFST, 0x04) 478 #define GOP_DW_BW GOP_REG(GOP_DW_OFST, 0x05) 479 #define GOP_DW_VSTR GOP_REG(GOP_DW_OFST, 0x10) 480 #define GOP_DW_HSTR GOP_REG(GOP_DW_OFST, 0x11) 481 #define GOP_DW_VEND GOP_REG(GOP_DW_OFST, 0x12) 482 #define GOP_DW_HEND GOP_REG(GOP_DW_OFST, 0x13) 483 #define GOP_DW_HSIZE GOP_REG(GOP_DW_OFST, 0x14) 484 #define GOP_DW_JMPLEN GOP_REG(GOP_DW_OFST, 0x15) 485 #define GOP_DW_DSTR_L GOP_REG(GOP_DW_OFST, 0x16) 486 #define GOP_DW_DSTR_H GOP_REG(GOP_DW_OFST, 0x17) 487 #define GOP_DW_UB_L GOP_REG(GOP_DW_OFST, 0x18) 488 #define GOP_DW_UB_H GOP_REG(GOP_DW_OFST, 0x19) 489 490 #define GOP_DW_PON_DSTR_L GOP_REG(GOP_DW_OFST, 0x1a) 491 #define GOP_DW_PON_DSTR_H GOP_REG(GOP_DW_OFST, 0x1b) 492 #define GOP_DW_PON_UB_L GOP_REG(GOP_DW_OFST, 0x1c) 493 #define GOP_DW_PON_UB_H GOP_REG(GOP_DW_OFST, 0x1d) 494 #define GOP_DW_FRAME_OFT_L GOP_REG(GOP_DW_OFST, 0x28) 495 #define GOP_DW_FRAME_OFT_H GOP_REG(GOP_DW_OFST, 0x29) 496 #define GOP_DW_FRAME_CTRL GOP_REG(GOP_DW_OFST, 0x30) 497 498 #define GOP_1G_CTRL0 GOP_REG(GOP_1G_OFST, 0x00) 499 #define GOP_1G_CTRL1 GOP_REG(GOP_1G_OFST, 0x01) 500 #define GOP_1G_RATE GOP_REG(GOP_1G_OFST, 0x02) 501 #define GOP_1G_PALDATA_L GOP_REG(GOP_1G_OFST, 0x03) 502 #define GOP_1G_PALDATA_H GOP_REG(GOP_1G_OFST, 0x04) 503 #define GOP_1G_PALCTRL GOP_REG(GOP_1G_OFST, 0x05) 504 #define GOP_1G_REGDMA_END GOP_REG(GOP_1G_OFST, 0x06) 505 #define GOP_1G_REGDMA_STR GOP_REG(GOP_1G_OFST, 0x07) 506 #define GOP_1G_INT GOP_REG(GOP_1G_OFST, 0x08) 507 #define GOP_1G_HWSTATE GOP_REG(GOP_1G_OFST, 0x09) 508 #define GOP_1G_RDMA_HT GOP_REG(GOP_1G_OFST, 0x0e) 509 #define GOP_1G_HS_PIPE GOP_REG(GOP_1G_OFST, 0x0f) 510 #define GOP_1G_BRI GOP_REG(GOP_1G_OFST, 0x11) 511 #define GOP_1G_CON GOP_REG(GOP_1G_OFST, 0x12) 512 #define GOP_1G_BW GOP_REG(GOP_1G_OFST, 0x19) 513 #define GOP_1G_3D_MIDDLE GOP_REG(GOP_1G_OFST, 0x1E) 514 #define GOP_1G_TRSCLR_L GOP_REG(GOP_1G_OFST, 0x24) 515 #define GOP_1G_TRSCLR_H GOP_REG(GOP_1G_OFST, 0x25) 516 #define GOP_1G_STRCH_HSZ GOP_REG(GOP_1G_OFST, 0x30) 517 #define GOP_1G_STRCH_VSZ GOP_REG(GOP_1G_OFST, 0x31) 518 #define GOP_1G_STRCH_HSTR GOP_REG(GOP_1G_OFST, 0x32) 519 #define GOP_1G_STRCH_VSTR GOP_REG(GOP_1G_OFST, 0x34) 520 #define GOP_1G_HSTRCH GOP_REG(GOP_1G_OFST, 0x35) 521 #define GOP_1G_HSTRCH_INI GOP_REG(GOP_1G_OFST, 0x38) 522 #define GOP_1G_VSTRCH_INI GOP_REG(GOP_1G_OFST, 0x39) 523 #define GOP_1G_HStrch_MD GOP_REG(GOP_1G_OFST, 0x3a) 524 #define GOP_1G_OLDADDR GOP_REG(GOP_1G_OFST, 0x3b) 525 #define GOP_1G_MULTI_ALPHA GOP_REG(GOP_1G_OFST, 0x3c) 526 527 #define GOP_1G_GWIN0_CTRL GOP_REG(GOP_1G_OFST+1, 0x0) 528 #define GOP_1G_DRAM_RBLK_L GOP_REG(GOP_1G_OFST+1, 0x1) 529 #define GOP_1G_DRAM_RBLK_H GOP_REG(GOP_1G_OFST+1, 0x2) 530 #define GOP_1G_DEL_PIXEL GOP_REG(GOP_1G_OFST+1, 0x3) 531 #define GOP_1G_HSTR GOP_REG(GOP_1G_OFST+1, 0x4) 532 #define GOP_1G_HEND GOP_REG(GOP_1G_OFST+1, 0x5) 533 #define GOP_1G_VSTR GOP_REG(GOP_1G_OFST+1, 0x6) 534 #define GOP_1G_VEND GOP_REG(GOP_1G_OFST+1, 0x8) 535 #define GOP_1G_DRAM_RBLK_HSIZE GOP_REG(GOP_1G_OFST+1, 0x9) 536 #define GOP_1G_GWIN_ALPHA01 GOP_REG(GOP_1G_OFST+1, 0xA) 537 #define GOP_1G_DRAM_VSTR_L GOP_REG(GOP_1G_OFST+1, 0x0C) 538 #define GOP_1G_DRAM_VSTR_H GOP_REG(GOP_1G_OFST+1, 0x0D) 539 #define GOP_1G_DRAM_FADE GOP_REG(GOP_1G_OFST+1, 0x16) 540 #define GOP_1G_3DOSD_SUB_RBLK_L GOP_REG(GOP_1G_OFST+1, 0x1E) 541 #define GOP_1G_3DOSD_SUB_RBLK_H GOP_REG(GOP_1G_OFST+1, 0x1F) 542 543 #define GOP_1GX_CTRL0 GOP_REG(GOP_1GX_OFST, 0x00) 544 #define GOP_1GX_CTRL1 GOP_REG(GOP_1GX_OFST, 0x01) 545 #define GOP_1GX_RATE GOP_REG(GOP_1GX_OFST, 0x02) 546 #define GOP_1GX_PALDATA_L GOP_REG(GOP_1GX_OFST, 0x03) 547 #define GOP_1GX_PALDATA_H GOP_REG(GOP_1GX_OFST, 0x04) 548 #define GOP_1GX_PALCTRL GOP_REG(GOP_1GX_OFST, 0x05) 549 #define GOP_1GX_REGDMA_END GOP_REG(GOP_1GX_OFST, 0x06) 550 #define GOP_1GX_REGDMA_STR GOP_REG(GOP_1GX_OFST, 0x07) 551 #define GOP_1GX_INT GOP_REG(GOP_1GX_OFST, 0x08) 552 #define GOP_1GX_HWSTATE GOP_REG(GOP_1GX_OFST, 0x09) 553 #define GOP_1GX_RDMA_HT GOP_REG(GOP_1GX_OFST, 0x0e) 554 #define GOP_1GX_HS_PIPE GOP_REG(GOP_1GX_OFST, 0x0f) 555 #define GOP_1GX_BRI GOP_REG(GOP_1GX_OFST, 0x11) 556 #define GOP_1GX_CON GOP_REG(GOP_1GX_OFST, 0x12) 557 #define GOP_1GX_BW GOP_REG(GOP_1GX_OFST, 0x19) 558 #define GOP_1GX_3D_MIDDLE GOP_REG(GOP_1GX_OFST, 0x1E) 559 #define GOP_1GX_TRSCLR_L GOP_REG(GOP_1GX_OFST, 0x24) 560 #define GOP_1GX_TRSCLR_H GOP_REG(GOP_1GX_OFST, 0x25) 561 #define GOP_1GX_STRCH_HSZ GOP_REG(GOP_1GX_OFST, 0x30) 562 #define GOP_1GX_STRCH_VSZ GOP_REG(GOP_1GX_OFST, 0x31) 563 #define GOP_1GX_STRCH_HSTR GOP_REG(GOP_1GX_OFST, 0x32) 564 #define GOP_1GX_STRCH_VSTR GOP_REG(GOP_1GX_OFST, 0x34) 565 #define GOP_1GX_HSTRCH GOP_REG(GOP_1GX_OFST, 0x35) 566 #define GOP_1GX_HSTRCH_INI GOP_REG(GOP_1GX_OFST, 0x38) 567 #define GOP_1GX_VSTRCH_INI GOP_REG(GOP_1GX_OFST, 0x39) 568 #define GOP_1GX_HStrch_MD GOP_REG(GOP_1GX_OFST, 0x3a) 569 #define GOP_1GX_OLDADDR GOP_REG(GOP_1GX_OFST, 0x3b) 570 #define GOP_1GX_MULTI_ALPHA GOP_REG(GOP_1GX_OFST, 0x3c) 571 572 #define GOP_1GX_GWIN0_CTRL GOP_REG(GOP_1GX_OFST+1, 0x00) 573 #define GOP_1GX_DRAM_RBLK_L GOP_REG(GOP_1GX_OFST+1, 0x01) 574 #define GOP_1GX_DRAM_RBLK_H GOP_REG(GOP_1GX_OFST+1, 0x02) 575 #define GOP_1GX_DEL_PIXEL GOP_REG(GOP_1GX_OFST+1, 0x03) 576 #define GOP_1GX_HSTR GOP_REG(GOP_1GX_OFST+1, 0x04) 577 #define GOP_1GX_HEND GOP_REG(GOP_1GX_OFST+1, 0x05) 578 #define GOP_1GX_VSTR GOP_REG(GOP_1GX_OFST+1, 0x06) 579 #define GOP_1GX_VEND GOP_REG(GOP_1GX_OFST+1, 0x08) 580 #define GOP_1GX_DRAM_RBLK_HSIZE GOP_REG(GOP_1GX_OFST+1, 0x09) 581 #define GOP_1GX_GWIN_ALPHA01 GOP_REG(GOP_1GX_OFST+1, 0x0A) 582 #define GOP_1GX_DRAM_VSTR_L GOP_REG(GOP_1GX_OFST+1, 0x0C) 583 #define GOP_1GX_DRAM_VSTR_H GOP_REG(GOP_1GX_OFST+1, 0x0D) 584 #define GOP_1GX_DRAM_FADE GOP_REG(GOP_1GX_OFST+1, 0x16) 585 #define GOP_1GX_3DOSD_SUB_RBLK_L GOP_REG(GOP_1GX_OFST+1, 0x1E) 586 #define GOP_1GX_3DOSD_SUB_RBLK_H GOP_REG(GOP_1GX_OFST+1, 0x1F) 587 588 #define GOP_1GS0_CTRL0 GOP_REG(GOP_1GS0_OFST, 0x00) 589 #define GOP_1GS0_CTRL1 GOP_REG(GOP_1GS0_OFST, 0x01) 590 #define GOP_1GS0_RATE GOP_REG(GOP_1GS0_OFST, 0x02) 591 #define GOP_1GS0_PALDATA_L GOP_REG(GOP_1GS0_OFST, 0x03) 592 #define GOP_1GS0_PALDATA_H GOP_REG(GOP_1GS0_OFST, 0x04) 593 #define GOP_1GS0_PALCTRL GOP_REG(GOP_1GS0_OFST, 0x05) 594 #define GOP_1GS0_REGDMA_END GOP_REG(GOP_1GS0_OFST, 0x06) 595 #define GOP_1GS0_REGDMA_STR GOP_REG(GOP_1GS0_OFST, 0x07) 596 #define GOP_1GS0_INT GOP_REG(GOP_1GS0_OFST, 0x08) 597 #define GOP_1GS0_HWSTATE GOP_REG(GOP_1GS0_OFST, 0x09) 598 #define GOP_1GS0_RDMA_HT GOP_REG(GOP_1GS0_OFST, 0x0e) 599 #define GOP_1GS0_HS_PIPE GOP_REG(GOP_1GS0_OFST, 0x0f) 600 #define GOP_1GS0_BRI GOP_REG(GOP_1GS0_OFST, 0x11) 601 #define GOP_1GS0_CON GOP_REG(GOP_1GS0_OFST, 0x12) 602 #define GOP_1GS0_BW GOP_REG(GOP_1GS0_OFST, 0x19) 603 #define GOP_1GS0_TRSCLR_L GOP_REG(GOP_1GS0_OFST, 0x24) 604 #define GOP_1GS0_TRSCLR_H GOP_REG(GOP_1GS0_OFST, 0x25) 605 #define GOP_1GS0_STRCH_HSZ GOP_REG(GOP_1GS0_OFST, 0x30) 606 #define GOP_1GS0_STRCH_VSZ GOP_REG(GOP_1GS0_OFST, 0x31) 607 #define GOP_1GS0_STRCH_HSTR GOP_REG(GOP_1GS0_OFST, 0x32) 608 #define GOP_1GS0_STRCH_VSTR GOP_REG(GOP_1GS0_OFST, 0x34) 609 #define GOP_1GS0_HSTRCH GOP_REG(GOP_1GS0_OFST, 0x35) 610 #define GOP_1GS0_HSTRCH_INI GOP_REG(GOP_1GS0_OFST, 0x38) 611 #define GOP_1GS0_VSTRCH_INI GOP_REG(GOP_1GS0_OFST, 0x39) 612 #define GOP_1GS0_HVStrch_MD GOP_REG(GOP_1GS0_OFST, 0x3a) 613 #define GOP_1GS0_OLDADDR GOP_REG(GOP_1GS0_OFST, 0x3b) 614 #define GOP_1GS0_MULTI_ALPHA GOP_REG(GOP_1GS0_OFST, 0x3c) 615 616 #define GOP_1GS0_GWIN0_CTRL GOP_REG(GOP_1GS0_OFST+1, 0x00) 617 #define GOP_1GS0_DRAM_RBLK_L GOP_REG(GOP_1GS0_OFST+1, 0x01) 618 #define GOP_1GS0_DRAM_RBLK_H GOP_REG(GOP_1GS0_OFST+1, 0x02) 619 #define GOP_1GS0_DEL_PIXEL GOP_REG(GOP_1GS0_OFST+1, 0x03) 620 #define GOP_1GS0_HSTR GOP_REG(GOP_1GS0_OFST+1, 0x04) 621 #define GOP_1GS0_HEND GOP_REG(GOP_1GS0_OFST+1, 0x05) 622 #define GOP_1GS0_VSTR GOP_REG(GOP_1GS0_OFST+1, 0x06) 623 #define GOP_1GS0_VEND GOP_REG(GOP_1GS0_OFST+1, 0x08) 624 #define GOP_1GS0_DRAM_RBLK_HSIZE GOP_REG(GOP_1GS0_OFST+1, 0x09) 625 #define GOP_1GS0_GWIN_ALPHA01 GOP_REG(GOP_1GS0_OFST+1, 0x0A) 626 #define GOP_1GS0_DRAM_VSTR_L GOP_REG(GOP_1GS0_OFST+1, 0x0C) 627 #define GOP_1GS0_DRAM_VSTR_H GOP_REG(GOP_1GS0_OFST+1, 0x0D) 628 #define GOP_1GS0_DRAM_FADE GOP_REG(GOP_1GS0_OFST+1, 0x16) 629 #define GOP_1GS0_3DOSD_SUB_RBLK_L GOP_REG(GOP_1GS0_OFST+1, 0x1E) 630 #define GOP_1GS0_3DOSD_SUB_RBLK_H GOP_REG(GOP_1GS0_OFST+1, 0x1F) 631 632 #define GOP_1GS1_CTRL0 GOP_REG(GOP_1GS1_OFST, 0x00) 633 #define GOP_1GS1_CTRL1 GOP_REG(GOP_1GS1_OFST, 0x01) 634 #define GOP_1GS1_RATE GOP_REG(GOP_1GS1_OFST, 0x02) 635 #define GOP_1GS1_PALDATA_L GOP_REG(GOP_1GS1_OFST, 0x03) 636 #define GOP_1GS1_PALDATA_H GOP_REG(GOP_1GS1_OFST, 0x04) 637 #define GOP_1GS1_PALCTRL GOP_REG(GOP_1GS1_OFST, 0x05) 638 #define GOP_1GS1_REGDMA_END GOP_REG(GOP_1GS1_OFST, 0x06) 639 #define GOP_1GS1_REGDMA_STR GOP_REG(GOP_1GS1_OFST, 0x07) 640 #define GOP_1GS1_INT GOP_REG(GOP_1GS1_OFST, 0x08) 641 #define GOP_1GS1_HWSTATE GOP_REG(GOP_1GS1_OFST, 0x09) 642 #define GOP_1GS1_RDMA_HT GOP_REG(GOP_1GS1_OFST, 0x0e) 643 #define GOP_1GS1_HS_PIPE GOP_REG(GOP_1GS1_OFST, 0x0f) 644 #define GOP_1GS1_BRI GOP_REG(GOP_1GS1_OFST, 0x11) 645 #define GOP_1GS1_CON GOP_REG(GOP_1GS1_OFST, 0x12) 646 #define GOP_1GS1_BW GOP_REG(GOP_1GS1_OFST, 0x19) 647 #define GOP_1GS1_TRSCLR_L GOP_REG(GOP_1GS1_OFST, 0x24) 648 #define GOP_1GS1_TRSCLR_H GOP_REG(GOP_1GS1_OFST, 0x25) 649 #define GOP_1GS1_STRCH_HSZ GOP_REG(GOP_1GS1_OFST, 0x30) 650 #define GOP_1GS1_STRCH_VSZ GOP_REG(GOP_1GS1_OFST, 0x31) 651 #define GOP_1GS1_STRCH_HSTR GOP_REG(GOP_1GS1_OFST, 0x32) 652 #define GOP_1GS1_STRCH_VSTR GOP_REG(GOP_1GS1_OFST, 0x34) 653 #define GOP_1GS1_HSTRCH GOP_REG(GOP_1GS1_OFST, 0x35) 654 #define GOP_1GS1_HSTRCH_INI GOP_REG(GOP_1GS1_OFST, 0x38) 655 #define GOP_1GS1_VSTRCH_INI GOP_REG(GOP_1GS1_OFST, 0x39) 656 #define GOP_1GS1_HVStrch_MD GOP_REG(GOP_1GS1_OFST, 0x3a) 657 #define GOP_1GS1_OLDADDR GOP_REG(GOP_1GS1_OFST, 0x3b) 658 #define GOP_1GS1_MULTI_ALPHA GOP_REG(GOP_1GS1_OFST, 0x3c) 659 660 #define GOP_1GS1_GWIN0_CTRL GOP_REG(GOP_1GS1_OFST+1, 0x00) 661 #define GOP_1GS1_DRAM_RBLK_L GOP_REG(GOP_1GS1_OFST+1, 0x01) 662 #define GOP_1GS1_DRAM_RBLK_H GOP_REG(GOP_1GS1_OFST+1, 0x02) 663 #define GOP_1GS1_DEL_PIXEL GOP_REG(GOP_1GS1_OFST+1, 0x03) 664 #define GOP_1GS1_HSTR GOP_REG(GOP_1GS1_OFST+1, 0x04) 665 #define GOP_1GS1_HEND GOP_REG(GOP_1GS1_OFST+1, 0x05) 666 #define GOP_1GS1_VSTR GOP_REG(GOP_1GS1_OFST+1, 0x06) 667 #define GOP_1GS1_VEND GOP_REG(GOP_1GS1_OFST+1, 0x08) 668 #define GOP_1GS1_DRAM_RBLK_HSIZE GOP_REG(GOP_1GS1_OFST+1, 0x09) 669 #define GOP_1GS1_GWIN_ALPHA01 GOP_REG(GOP_1GS1_OFST+1, 0x0A) 670 #define GOP_1GS1_DRAM_VSTR_L GOP_REG(GOP_1GS1_OFST+1, 0x0C) 671 #define GOP_1GS1_DRAM_VSTR_H GOP_REG(GOP_1GS1_OFST+1, 0x0D) 672 #define GOP_1GS1_DRAM_FADE GOP_REG(GOP_1GS1_OFST+1, 0x16) 673 #define GOP_1GS1_3DOSD_SUB_RBLK_L GOP_REG(GOP_1GS1_OFST+1, 0x1E) 674 #define GOP_1GS1_3DOSD_SUB_RBLK_H GOP_REG(GOP_1GS1_OFST+1, 0x1F) 675 //------------------------------------------------------------------------------------------------- 676 // Type and Structure 677 //------------------------------------------------------------------------------------------------- 678 679 //---------------------------------------------------------------------------- 680 // GOP Test Pattern Reg 681 //---------------------------------------------------------------------------- 682 #define REG_TSTCLR_EN GOP_REG(GOP_4G_OFST, 0x00) 683 #define REG_TSTCLR_ALPHA_EN GOP_REG(GOP_4G_OFST+2, 0x00) 684 #define REG_TLB_TAG_ADDR_L GOP_REG(GOP_4G_OFST+2, 0x2C) 685 #define REG_TLB_TAG_ADDR_H GOP_REG(GOP_4G_OFST+2, 0x2D) 686 #define REG_TLB_TAG_ADDR_RVIEW_L GOP_REG(GOP_4G_OFST+2, 0x2E) 687 #define REG_TLB_TAG_ADDR_RVIEW_H GOP_REG(GOP_4G_OFST+2, 0x2F) 688 #define REG_TSTCLR_ALPHA GOP_REG(GOP_4G_OFST+2, 0x40) 689 #define REG_R_STC GOP_REG(GOP_4G_OFST+2, 0x41) 690 #define REG_G_STC GOP_REG(GOP_4G_OFST+2, 0x48) 691 #define REG_B_STC GOP_REG(GOP_4G_OFST+2, 0x49) 692 #define REG_TSTCLR_HDUP GOP_REG(GOP_4G_OFST+2, 0x01) 693 #define REG_TSTCLR_VDUP GOP_REG(GOP_4G_OFST+2, 0x01) 694 #define REG_HR_INC GOP_REG(GOP_4G_OFST+2, 0x42) 695 #define REG_HR_INC_SIGNZ GOP_REG(GOP_4G_OFST+2, 0x42) 696 #define REG_HG_INC GOP_REG(GOP_4G_OFST+2, 0x43) 697 #define REG_HG_INC_SIGNZ GOP_REG(GOP_4G_OFST+2, 0x43) 698 #define REG_HB_INC GOP_REG(GOP_4G_OFST+2, 0x44) 699 #define REG_HB_INC_SIGNZ GOP_REG(GOP_4G_OFST+2, 0x44) 700 #define REG_HR_STEP GOP_REG(GOP_4G_OFST+2, 0x4A) 701 #define REG_HG_STEP GOP_REG(GOP_4G_OFST+2, 0x4B) 702 #define REG_HB_STEP GOP_REG(GOP_4G_OFST+2, 0x4C) 703 #define REG_VR_INC GOP_REG(GOP_4G_OFST+2, 0x45) 704 #define REG_VR_INC_SIGNZ GOP_REG(GOP_4G_OFST+2, 0x45) 705 #define REG_VG_INC GOP_REG(GOP_4G_OFST+2, 0x46) 706 #define REG_VG_INC_SIGNZ GOP_REG(GOP_4G_OFST+2, 0x46) 707 #define REG_VB_INC GOP_REG(GOP_4G_OFST+2, 0x47) 708 #define REG_VB_INC_SIGNZ GOP_REG(GOP_4G_OFST+2, 0x47) 709 #define REG_VR_STEP GOP_REG(GOP_4G_OFST+2, 0x4D) 710 #define REG_VG_STEP GOP_REG(GOP_4G_OFST+2, 0x4E) 711 #define REG_VB_STEP GOP_REG(GOP_4G_OFST+2, 0x4F) 712 #define REG_TLB_BASE_ADDR_L GOP_REG(GOP_4G_OFST+2, 0x58) 713 #define REG_TLB_BASE_ADDR_H GOP_REG(GOP_4G_OFST+2, 0x59) 714 #define REG_TLB_BASE_ADDR_RVIEW_L GOP_REG(GOP_4G_OFST+2, 0x5A) 715 #define REG_TLB_BASE_ADDR_RVIEW_H GOP_REG(GOP_4G_OFST+2, 0x5B) 716 717 #define MASK_TSTCLR_EN GOP_BIT6 718 #define MASK_TSTCLR_ALPHA_EN 0 719 #define MASK_TSTCLR_ALPHA 0 720 #define MASK_RGB_STC_VALID BMASK(1:0) 721 #define MASK_R_STC BMASK(9:8) 722 #define MASK_G_STC BMASK(11:10) 723 #define MASK_B_STC BMASK(1:0) 724 #define MASK_INI_TSTCLR_EN GOP_BIT15 725 #define MASK_TSTCLR_HDUP BMASK(9:8) 726 #define MASK_TSTCLR_VDUP BMASK(3:2) 727 #define MASK_HR_INC BMASK(14:8) 728 #define MASK_HR_INC_SIGNZ GOP_BIT15 729 #define MASK_HG_INC BMASK(6:0) 730 #define MASK_HG_INC_SIGNZ GOP_BIT7 731 #define MASK_HB_INC BMASK(6:0) 732 #define MASK_HB_INC_SIGNZ GOP_BIT7 733 #define MASK_HR_STEP BMASK(7:0) 734 #define MASK_HG_STEP BMASK(15:8) 735 #define MASK_HB_STEP BMASK(7:0) 736 #define MASK_VR_INC BMASK(14:8) 737 #define MASK_VR_INC_SIGNZ GOP_BIT4 738 #define MASK_VG_INC BMASK(6:0) 739 #define MASK_VG_INC_SIGNZ GOP_BIT7 740 #define MASK_VB_INC BMASK(14:8) 741 #define MASK_VB_INC_SIGNZ GOP_BIT15 742 #define MASK_VR_STEP BMASK(7:0) 743 #define MASK_VG_STEP BMASK(7:0) 744 #define MASK_VB_STEP BMASK(7:0) 745 746 #define SHIFT_TSTCLR_EN 6 747 #define SHIFT_TSTCLR_ALPHA_EN 0 748 #define SHIFT_TSTCLR_ALPHA 0 749 #define SHIFT_R_STC 8 750 #define SHIFT_G_STC 10 751 #define SHIFT_B_STC 0 752 #define SHIFT_INI_TSTCLR_EN 15 753 #define SHIFT_TSTCLR_HDUP 8 754 #define SHIFT_TSTCLR_VDUP 2 755 #define SHIFT_HR_INC 8 756 #define SHIFT_HR_INC_SIGNZ 15 757 #define SHIFT_HG_INC 0 758 #define SHIFT_HG_INC_SIGNZ 7 759 #define SHIFT_HB_INC 0 760 #define SHIFT_HB_INC_SIGNZ 7 761 #define SHIFT_HR_STEP 0 762 #define SHIFT_HG_STEP 8 763 #define SHIFT_HB_STEP 0 764 #define SHIFT_VR_INC 8 765 #define SHIFT_VR_INC_SIGNZ 4 766 #define SHIFT_VG_INC 0 767 #define SHIFT_VG_INC_SIGNZ 7 768 #define SHIFT_VB_INC 8 769 #define SHIFT_VB_INC_SIGNZ 15 770 #define SHIFT_VR_STEP 0 771 #define SHIFT_VG_STEP 0 772 #define SHIFT_VB_STEP 0 773 #endif // _REG_GOP_H_ 774 775