Searched refs:E_PNL_DEVICE_ID_1 (Results 1 – 18 of 18) sorted by relevance
101 E_PNL_DEVICE_ID_1 = 1, enumerator108 ((u32Id == E_PNL_DEVICE_ID_1) ? E_PNL_POOL_ID_INTERNAL1 : E_PNL_POOL_ID_INTERNAL)
102 E_PNL_DEVICE_ID_1 = 1, enumerator109 ((u32Id == E_PNL_DEVICE_ID_1) ? E_PNL_POOL_ID_INTERNAL1 : E_PNL_POOL_ID_INTERNAL)
1060 …u32PNL_XCDeviceBankOffset[E_PNL_DEVICE_ID_1] = E_HALPNL_DEVICE1_XC_BANK_OFFSET; // Set SC1 reg ban… in MHal_PNL_Set_Device_Bank_Offset()
1942 …u32PNL_XCDeviceBankOffset[E_PNL_DEVICE_ID_1] = E_HALPNL_DEVICE1_XC_BANK_OFFSET; // Set SC2 reg ban… in MHal_PNL_Set_Device_Bank_Offset()
2787 …u32PNL_XCDeviceBankOffset[E_PNL_DEVICE_ID_1] = E_HALPNL_DEVICE1_XC_BANK_OFFSET; // Set SC2 reg ban… in MHal_PNL_Set_Device_Bank_Offset()
3278 …u32PNL_XCDeviceBankOffset[E_PNL_DEVICE_ID_1] = E_HALPNL_DEVICE1_XC_BANK_OFFSET; // Set SC2 reg ban… in MHal_PNL_Set_Device_Bank_Offset()
3662 …u32PNL_XCDeviceBankOffset[E_PNL_DEVICE_ID_1] = E_HALPNL_DEVICE1_XC_BANK_OFFSET; // Set SC2 reg ban… in MHal_PNL_Set_Device_Bank_Offset()
4009 …u32PNL_XCDeviceBankOffset[E_PNL_DEVICE_ID_1] = E_HALPNL_DEVICE1_XC_BANK_OFFSET; // Set SC2 reg ban… in MHal_PNL_Set_Device_Bank_Offset()
4055 …u32PNL_XCDeviceBankOffset[E_PNL_DEVICE_ID_1] = E_HALPNL_DEVICE1_XC_BANK_OFFSET; // Set SC2 reg ban… in MHal_PNL_Set_Device_Bank_Offset()
5040 …u32PNL_XCDeviceBankOffset[E_PNL_DEVICE_ID_1] = E_HALPNL_DEVICE1_XC_BANK_OFFSET; // Set SC2 reg ban… in MHal_PNL_Set_Device_Bank_Offset()
5070 …u32PNL_XCDeviceBankOffset[E_PNL_DEVICE_ID_1] = E_HALPNL_DEVICE1_XC_BANK_OFFSET; // Set SC2 reg ban… in MHal_PNL_Set_Device_Bank_Offset()
71326 E_PNL_DEVICE_ID_1 = 1,71333 ((u32Id == E_PNL_DEVICE_ID_1) ? E_PNL_POOL_ID_INTERNAL1 : E_PNL_POOL_ID_INTERNAL)