Searched refs:E_PNL_DEVICE_ID_0 (Results 1 – 18 of 18) sorted by relevance
100 E_PNL_DEVICE_ID_0 = 0, enumerator
101 E_PNL_DEVICE_ID_0 = 0, enumerator
1059 …u32PNL_XCDeviceBankOffset[E_PNL_DEVICE_ID_0] = E_HALPNL_DEVICE0_XC_BANK_OFFSET; // Set SC0 reg ban… in MHal_PNL_Set_Device_Bank_Offset()
1941 …u32PNL_XCDeviceBankOffset[E_PNL_DEVICE_ID_0] = E_HALPNL_DEVICE0_XC_BANK_OFFSET; // Set SC0 reg ban… in MHal_PNL_Set_Device_Bank_Offset()
2786 …u32PNL_XCDeviceBankOffset[E_PNL_DEVICE_ID_0] = E_HALPNL_DEVICE0_XC_BANK_OFFSET; // Set SC0 reg ban… in MHal_PNL_Set_Device_Bank_Offset()
3277 …u32PNL_XCDeviceBankOffset[E_PNL_DEVICE_ID_0] = E_HALPNL_DEVICE0_XC_BANK_OFFSET; // Set SC0 reg ban… in MHal_PNL_Set_Device_Bank_Offset()
3661 …u32PNL_XCDeviceBankOffset[E_PNL_DEVICE_ID_0] = E_HALPNL_DEVICE0_XC_BANK_OFFSET; // Set SC0 reg ban… in MHal_PNL_Set_Device_Bank_Offset()
4008 …u32PNL_XCDeviceBankOffset[E_PNL_DEVICE_ID_0] = E_HALPNL_DEVICE0_XC_BANK_OFFSET; // Set SC0 reg ban… in MHal_PNL_Set_Device_Bank_Offset()
4054 …u32PNL_XCDeviceBankOffset[E_PNL_DEVICE_ID_0] = E_HALPNL_DEVICE0_XC_BANK_OFFSET; // Set SC0 reg ban… in MHal_PNL_Set_Device_Bank_Offset()
5039 …u32PNL_XCDeviceBankOffset[E_PNL_DEVICE_ID_0] = E_HALPNL_DEVICE0_XC_BANK_OFFSET; // Set SC0 reg ban… in MHal_PNL_Set_Device_Bank_Offset()
5069 …u32PNL_XCDeviceBankOffset[E_PNL_DEVICE_ID_0] = E_HALPNL_DEVICE0_XC_BANK_OFFSET; // Set SC0 reg ban… in MHal_PNL_Set_Device_Bank_Offset()
71325 E_PNL_DEVICE_ID_0 = 0,