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/rk3399_rockchip-uboot/include/andestech/
H A Dandes_pcu.h80 #define ANDES_PCU_REV_NUMBER_PCS(x) (((x) >> 0) & 0xff) argument
81 #define ANDES_PCU_REV_VER(x) (((x) >> 16) & 0xffff) argument
86 #define ANDES_PCU_SPINFO_SIZE(x) (((x) >> 0) & 0xff) argument
87 #define ANDES_PCU_SPINFO_OFFSET(x) (((x) >> 8) & 0xf) argument
92 #define ANDES_PCU_SOC_ID_VER_MINOR(x) (((x) >> 0) & 0xf) argument
93 #define ANDES_PCU_SOC_ID_VER_MAJOR(x) (((x) >> 4) & 0xfff) argument
94 #define ANDES_PCU_SOC_ID_DEVICEID(x) (((x) >> 16) & 0xffff) argument
99 #define ANDES_PCU_SOC_AHB_AHBC(x) ((x) << 0) argument
100 #define ANDES_PCU_SOC_AHB_APBREG(x) ((x) << 1) argument
101 #define ANDES_PCU_SOC_AHB_APB(x) ((x) << 2) argument
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/rk3399_rockchip-uboot/include/synopsys/
H A Ddwcddr21mctl.h48 #define DWCDDR21MCTL_CCR_ECCEN(x) ((x) << 0) argument
49 #define DWCDDR21MCTL_CCR_NOMRWR(x) ((x) << 1) argument
50 #define DWCDDR21MCTL_CCR_HOSTEN(x) ((x) << 2) argument
51 #define DWCDDR21MCTL_CCR_XBISC(x) ((x) << 3) argument
52 #define DWCDDR21MCTL_CCR_NOAPD(x) ((x) << 4) argument
53 #define DWCDDR21MCTL_CCR_RRB(x) ((x) << 13) argument
54 #define DWCDDR21MCTL_CCR_DQSCFG(x) ((x) << 14) argument
55 #define DWCDDR21MCTL_CCR_DFTLM(x) (((x) & 0x3) << 15) argument
56 #define DWCDDR21MCTL_CCR_DFTCMP(x) ((x) << 17) argument
57 #define DWCDDR21MCTL_CCR_FLUSH(x) ((x) << 27) argument
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/rk3399_rockchip-uboot/board/samsung/odroid/
H A Dsetup.h12 #define SDIV(x) ((x) & 0x7) argument
13 #define PDIV(x) (((x) & 0x3f) << 8) argument
14 #define MDIV(x) (((x) & 0x3ff) << 16) argument
15 #define FSEL(x) (((x) & 0x1) << 27) argument
17 #define PLL_ENABLE(x) (((x) & 0x1) << 31) argument
20 #define MUX_APLL_SEL(x) ((x) & 0x1) argument
21 #define MUX_CORE_SEL(x) (((x) & 0x1) << 16) argument
22 #define MUX_HPM_SEL(x) (((x) & 0x1) << 20) argument
23 #define MUX_MPLL_USER_SEL_C(x) (((x) & 0x1) << 24) argument
28 #define APLL_SEL(x) ((x) & 0x7) argument
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/rk3399_rockchip-uboot/arch/arm/include/asm/arch-rockchip/
H A Dvop_rk3288.h123 #define V_AUTO_GATING_EN(x) (((x) & 1) << 23) argument
124 #define V_STANDBY_EN(x) (((x) & 1) << 22) argument
125 #define V_DMA_STOP(x) (((x) & 1) << 21) argument
126 #define V_MMU_EN(x) (((x) & 1) << 20) argument
127 #define V_DMA_BURST_LENGTH(x) (((x) & 3) << 18) argument
128 #define V_MIPI_OUT_EN(x) (((x) & 1) << 15) argument
129 #define V_EDP_OUT_EN(x) (((x) & 1) << 14) argument
130 #define V_HDMI_OUT_EN(x) (((x) & 1) << 13) argument
131 #define V_RGB_OUT_EN(x) (((x) & 1) << 12) argument
132 #define V_EDPI_WMS_FS(x) (((x) & 1) << 10) argument
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/rk3399_rockchip-uboot/arch/m68k/include/asm/
H A Dm5329.h18 #define SCM_MPR_MPROT0(x) (((x)&0x0F)<<28) argument
19 #define SCM_MPR_MPROT1(x) (((x)&0x0F)<<24) argument
20 #define SCM_MPR_MPROT2(x) (((x)&0x0F)<<20) argument
21 #define SCM_MPR_MPROT4(x) (((x)&0x0F)<<12) argument
22 #define SCM_MPR_MPROT5(x) (((x)&0x0F)<<8) argument
23 #define SCM_MPR_MPROT6(x) (((x)&0x0F)<<4) argument
40 #define SCM_PACRA_PACR0(x) (((x)&0x0F)<<28) argument
41 #define SCM_PACRA_PACR1(x) (((x)&0x0F)<<24) argument
42 #define SCM_PACRA_PACR2(x) (((x)&0x0F)<<20) argument
48 #define SCM_PACRB_PACR8(x) (((x)&0x0F)<<28) argument
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H A Dm5301x.h14 #define SCM_MPR_MPROT0(x) (((x) & 0x0F) << 28) argument
15 #define SCM_MPR_MPROT1(x) (((x) & 0x0F) << 24) argument
16 #define SCM_MPR_MPROT2(x) (((x) & 0x0F) << 20) argument
17 #define SCM_MPR_MPROT4(x) (((x) & 0x0F) << 12) argument
18 #define SCM_MPR_MPROT5(x) (((x) & 0x0F) << 8) argument
19 #define SCM_MPR_MPROT6(x) (((x) & 0x0F) << 4) argument
24 #define SCM_PACRA_PACR0(x) (((x) & 0x0F) << 28) argument
25 #define SCM_PACRA_PACR1(x) (((x) & 0x0F) << 24) argument
26 #define SCM_PACRA_PACR2(x) (((x) & 0x0F) << 20) argument
27 #define SCM_PACRA_PACR5(x) (((x) & 0x0F) << 8) argument
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H A Dm520x.h14 #define SCM_MPR_MPROT0(x) (((x) & 0x0F) << 28) argument
15 #define SCM_MPR_MPROT1(x) (((x) & 0x0F) << 24) argument
16 #define SCM_MPR_MPROT2(x) (((x) & 0x0F) << 20) argument
21 #define SCM_PACRA_PACR0(x) (((x) & 0x0F) << 28) argument
22 #define SCM_PACRA_PACR1(x) (((x) & 0x0F) << 24) argument
23 #define SCM_PACRA_PACR2(x) (((x) & 0x0F) << 20) argument
25 #define SCM_PACRB_PACR12(x) (((x) & 0x0F) << 12) argument
27 #define SCM_PACRC_PACR16(x) (((x) & 0x0F) << 28) argument
28 #define SCM_PACRC_PACR17(x) (((x) & 0x0F) << 24) argument
29 #define SCM_PACRC_PACR18(x) (((x) & 0x0F) << 20) argument
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H A Dm547x_8x.h20 #define XARB_CFG_PM(x) (((x)&0x00000003)<<5) argument
21 #define XARB_CFG_SP(x) (((x)&0x00000007)<<8) argument
47 #define XARB_SIGCAP_TT(x) ((x)&0x0000001F) argument
49 #define XARB_SIGCAP_TSIZ(x) (((x)&0x00000007)<<7) argument
57 #define XARB_PRI_M0P(x) (((x)&0x00000007)<<0) argument
58 #define XARB_PRI_M2P(x) (((x)&0x00000007)<<8) argument
59 #define XARB_PRI_M3P(x) (((x)&0x00000007)<<12) argument
65 #define GPIO_PAR_FBCTL_TS(x) (((x)&0x0003)<<0) argument
67 #define GPIO_PAR_FBCTL_RWB(x) (((x)&0x0003)<<4) argument
88 #define GPIO_PAR_DMA_DREQ0(x) (((x)&0x03)<<0) argument
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H A Dm5441x.h192 #define SBF_SBFCR_BLDIV(x) (((x)&0x000F)) argument
227 #define CCM_MISCCR_PWM_EXTCLK(x) (((x)&(0x0003)<<14) argument
235 #define CCM_MISCCR_BMT(x) (((x)&0x0007)<<8) argument
252 #define CCM_CDRH_SSI0DIV(x) (((x)&0x00FF)<<8) argument
254 #define CCM_CDRH_SSI1DIV(x) (((x)&0x00FF)) argument
256 #define CCM_CDRL_LPDIV(x) (((x)&0x000F)<<8) argument
258 #define CCM_CDR_LPDIV(x) CCM_CDRL_LPDIV(x) argument
282 #define CCM_MISCCR3_ENETCLK(x) (((x)&7)<<8) argument
297 #define CCM_MISCCR2_PLLMODE(x) (((x)&7)<<8) argument
308 #define CCM_FNACR_PCR(x) (((x)&0x0F)<<24) argument
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H A Dm5235.h19 #define SCM_IPSBAR_BA(x) (((x)&0x03)<<30) argument
23 #define SCM_RAMBAR_BA(x) (((x)&0xFFFF)<<16) argument
32 #define SCM_CWCR_CWT(x) (((x)&0x07)<<3) argument
39 #define SCM_LPICR_XLPM_IPL(x) (((x)&0x07)<<4) argument
49 #define SCM_DMAREQC_EXT(x) (((x)&0x0F)<<16) argument
54 #define SCM_DMAREQC_DMAC3(x) (((x)&0x0F)<<12) argument
55 #define SCM_DMAREQC_DMAC2(x) (((x)&0x0F)<<8) argument
56 #define SCM_DMAREQC_DMAC1(x) (((x)&0x0F)<<4) argument
57 #define SCM_DMAREQC_DMAC0(x) (((x)&0x0F)) argument
89 #define SCM_MPARK_LCKOUT_TIME(x) (((x)&0x0F)<<8) argument
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H A Dm5445x.h116 #define SBF_SBFCR_BLDIV(x) (((x)&0x000F)) /* Boot loader clock divider */ argument
139 #define CCM_CCR_360_PLLMULT2(x) (((x)&0x0003)) /* 2-Bit PLL clock mode */ argument
143 #define CCM_CCR_360_FBCONFIG(x) (((x)&0x0007)<<5) /* Flexbus/PCI port size configuration */ argument
144 #define CCM_CCR_360_PLLMULT3(x) (((x)&0x0007)) /* 3-Bit PLL Clock Mode */ argument
171 #define CCM_CCR_256_PLLMULT3(x) (((x)&0x0007)) /* 3-Bit PLL clock mode */ argument
174 #define CCM_CCR_256_FBCONFIG(x) (((x)&0x0007)<<5) /* Flexbus/PCI port size configuration */ argument
193 #define CCM_RCON_360_PLLMULT(x) (((x)&0x0003)) /* PLL clock mode */ argument
197 #define CCM_RCON_360_FBCONFIG(x) (((x)&0x0007)<<5) /* Flexbus/PCI port size configuration */ argument
200 #define CCM_RCON_256_PLLMULT(x) (((x)&0x0007)) /* PLL clock mode */ argument
203 #define CCM_RCON_256_FBCONFIG(x) (((x)&0x0007)<<5) /* Flexbus/PCI port size configuration */ argument
[all …]
/rk3399_rockchip-uboot/arch/arm/include/asm/
H A Dopcodes.h25 #define ___asm_opcode_swab32(x) ( \ argument
26 (((x) << 24) & 0xFF000000) \
27 | (((x) << 8) & 0x00FF0000) \
28 | (((x) >> 8) & 0x0000FF00) \
29 | (((x) >> 24) & 0x000000FF) \
31 #define ___asm_opcode_swab16(x) ( \ argument
32 (((x) << 8) & 0xFF00) \
33 | (((x) >> 8) & 0x00FF) \
35 #define ___asm_opcode_swahb32(x) ( \ argument
36 (((x) << 8) & 0xFF00FF00) \
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/rk3399_rockchip-uboot/arch/m68k/include/asm/coldfire/
H A Dlcd.h51 #define LCDC_SSAR_SSA(x) (((x)&0x3FFFFFFF)<<2) argument
54 #define LCDC_SR_XMAX(x) (((x)&0x0000003F)<<20) argument
55 #define LCDC_SR_YMAX(x) ((x)&0x000003FF) argument
58 #define LCDC_VPWR_VPW(x) (((x)&0x000003FF) argument
61 #define LCDC_CPR_CC(x) (((x)&0x00000003)<<30) argument
67 #define LCDC_CPR_CXP(x) (((x)&0x000003FF)<<16) argument
68 #define LCDC_CPR_CYP(x) ((x)&0x000003FF) argument
72 #define LCDC_CWHBR_CW(x) (((x)&0x0000001F)<<24) argument
73 #define LCDC_CWHBR_CH(x) (((x)&0x0000001F)<<16) argument
74 #define LCDC_CWHBR_BD(x) ((x)&0x000000FF) argument
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/rk3399_rockchip-uboot/include/
H A Dcompiler.h67 #define uswap_16(x) \ argument
68 ((((x) & 0xff00) >> 8) | \
69 (((x) & 0x00ff) << 8))
70 #define uswap_32(x) \ argument
71 ((((x) & 0xff000000) >> 24) | \
72 (((x) & 0x00ff0000) >> 8) | \
73 (((x) & 0x0000ff00) << 8) | \
74 (((x) & 0x000000ff) << 24))
75 #define _uswap_64(x, sfx) \ argument
76 ((((x) & 0xff00000000000000##sfx) >> 56) | \
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H A Dfsl_dspi.h38 #define DSPI_MCR_DCONF(x) (((x) & 0x03) << 28) argument
43 #define DSPI_MCR_PCSIS(x) (1 << (16 + (x))) argument
59 #define DSPI_MCR_SMPL_PT(x) (((x) & 0x03) << 8) argument
65 #define DSPI_TCR_SPI_TCNT(x) (((x) & 0x0000FFFF) << 16) argument
68 #define DSPI_CTAR(x) (0x0c + (x * 4)) argument
70 #define DSPI_CTAR_TRSZ(x) (((x) & 0x0F) << 27) argument
74 #define DSPI_CTAR_PCSSCK(x) (((x) & 0x03) << 22) argument
79 #define DSPI_CTAR_PASC(x) (((x) & 0x03) << 20) argument
84 #define DSPI_CTAR_PDT(x) (((x) & 0x03) << 18) argument
89 #define DSPI_CTAR_PBR(x) (((x) & 0x03) << 16) argument
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/rk3399_rockchip-uboot/include/faraday/
H A Dftsdmc021.h43 #define FTSDMC021_TP1_TCL(x) ((x) & 0x3) /* CAS Latency */ argument
44 #define FTSDMC021_TP1_TWR(x) (((x) & 0x3) << 4) /* W-Recovery Time */ argument
45 #define FTSDMC021_TP1_TRF(x) (((x) & 0xf) << 8) /* Auto-Refresh Cycle */ argument
46 #define FTSDMC021_TP1_TRCD(x) (((x) & 0x7) << 12) /* RAS-to-CAS Delay */ argument
47 #define FTSDMC021_TP1_TRP(x) (((x) & 0xf) << 16) /* Precharge Cycle */ argument
48 #define FTSDMC021_TP1_TRAS(x) (((x) & 0xf) << 20) argument
53 #define FTSDMC021_TP2_REF_INTV(x) ((x) & 0xffff) /* Refresh interval */ argument
55 #define FTSDMC021_TP2_INI_REFT(x) (((x) & 0xf) << 16) argument
57 #define FTSDMC021_TP2_INI_PREC(x) (((x) & 0xf) << 20) argument
62 #define FTSDMC021_CR1_BNKSIZE(x) ((x) & 0xf) /* Bank Size */ argument
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/rk3399_rockchip-uboot/arch/arm/include/asm/arch-omap3/
H A Domap3-regs.h24 #define CLKACTIVATIONTIME(x) (((x) & 3) << 25) argument
25 #define ATTACHEDDEVICEPAGELENGTH(x) (((x) & 3) << 23) argument
28 #define WAITMONITORINGTIME(x) (((x) & 3) << 18) argument
29 #define WAITPINSELECT(x) (((x) & 3) << 16) argument
30 #define DEVICESIZE(x) (((x) & 3) << 12) argument
33 #define DEVICETYPE(x) (((x) & 3) << 10) argument
38 #define GPMCFCLKDIVIDER(x) (((x) & 3) << 0) argument
41 #define CSWROFFTIME(x) (((x) & 0x1f) << 16) argument
42 #define CSRDOFFTIME(x) (((x) & 0x1f) << 8) argument
44 #define CSONTIME(x) (((x) & 0xf) << 0) argument
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/rk3399_rockchip-uboot/drivers/video/drm/
H A Drockchip_tve.h16 #define v_DAC_GAIN(x) (((x) & 0x3f) << 7) argument
26 #define v_CVBS_MODE(x) (((x) & 1) << 24) argument
27 #define v_CLK_UPSTREAM_EN(x) (((x) & 3) << 18) argument
28 #define v_TIMING_EN(x) (((x) & 3) << 16) argument
29 #define v_LUMA_FILTER_GAIN(x) (((x) & 3) << 9) argument
30 #define v_LUMA_FILTER_UPSAMPLE(x) (((x) & 1) << 8) argument
31 #define v_CSC_PATH(x) (((x) & 3) << 1) argument
51 #define v_DAC_SENSE_EN(x) (((x) & 1) << 27) argument
52 #define v_Y_IRE_7_5(x) (((x) & 1) << 19) argument
53 #define v_Y_AGC_PULSE_ON(x) (((x) & 1) << 15) argument
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/rk3399_rockchip-uboot/drivers/ddr/microchip/
H A Dddr2_regs.h47 #define REFCNT_CLK(x) (x) argument
48 #define REFDLY_CLK(x) ((x) << 16) argument
49 #define MAX_PEND_REF(x) ((x) << 24) argument
52 #define PRECH_PWR_DN_ONLY(x) ((x) << 22) argument
53 #define SELF_REF_DLY(x) ((x) << 12) argument
54 #define PWR_DN_DLY(x) ((x) << 4) argument
55 #define EN_AUTO_SELF_REF(x) ((x) << 3) argument
56 #define EN_AUTO_PWR_DN(x) ((x) << 2) argument
57 #define ERR_CORR_EN(x) ((x) << 1) argument
58 #define ECC_EN(x) (x) argument
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/rk3399_rockchip-uboot/include/linux/byteorder/
H A Dswab.h21 #define ___swab16(x) \ argument
23 (((__u16)(x) & (__u16)0x00ffU) << 8) | \
24 (((__u16)(x) & (__u16)0xff00U) >> 8) ))
25 #define ___swab32(x) \ argument
27 (((__u32)(x) & (__u32)0x000000ffUL) << 24) | \
28 (((__u32)(x) & (__u32)0x0000ff00UL) << 8) | \
29 (((__u32)(x) & (__u32)0x00ff0000UL) >> 8) | \
30 (((__u32)(x) & (__u32)0xff000000UL) >> 24) ))
31 #define ___swab64(x) \ argument
33 (__u64)(((__u64)(x) & (__u64)0x00000000000000ffULL) << 56) | \
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H A Dbig_endian.h16 #define __constant_htonl(x) ((__force __be32)(__u32)(x)) argument
17 #define __constant_ntohl(x) ((__force __u32)(__be32)(x)) argument
18 #define __constant_htons(x) ((__force __be16)(__u16)(x)) argument
19 #define __constant_ntohs(x) ((__force __u16)(__be16)(x)) argument
20 #define __constant_cpu_to_le64(x) ((__force __le64)___constant_swab64((x))) argument
21 #define __constant_le64_to_cpu(x) ___constant_swab64((__force __u64)(__le64)(x)) argument
22 #define __constant_cpu_to_le32(x) ((__force __le32)___constant_swab32((x))) argument
23 #define __constant_le32_to_cpu(x) ___constant_swab32((__force __u32)(__le32)(x)) argument
24 #define __constant_cpu_to_le16(x) ((__force __le16)___constant_swab16((x))) argument
25 #define __constant_le16_to_cpu(x) ___constant_swab16((__force __u16)(__le16)(x)) argument
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H A Dlittle_endian.h16 #define __constant_htonl(x) ((__force __be32)___constant_swab32((x))) argument
17 #define __constant_ntohl(x) ___constant_swab32((__force __be32)(x)) argument
18 #define __constant_htons(x) ((__force __be16)___constant_swab16((x))) argument
19 #define __constant_ntohs(x) ___constant_swab16((__force __be16)(x)) argument
20 #define __constant_cpu_to_le64(x) ((__force __le64)(__u64)(x)) argument
21 #define __constant_le64_to_cpu(x) ((__force __u64)(__le64)(x)) argument
22 #define __constant_cpu_to_le32(x) ((__force __le32)(__u32)(x)) argument
23 #define __constant_le32_to_cpu(x) ((__force __u32)(__le32)(x)) argument
24 #define __constant_cpu_to_le16(x) ((__force __le16)(__u16)(x)) argument
25 #define __constant_le16_to_cpu(x) ((__force __u16)(__le16)(x)) argument
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/rk3399_rockchip-uboot/arch/arm/include/asm/arch-mx7ulp/
H A Dimx_lpi2c.h92 #define LPI2C_VERID_FEATURE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_VERID_FEATUR… argument
95 #define LPI2C_VERID_MINOR(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_VERID_MINOR_… argument
98 #define LPI2C_VERID_MAJOR(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_VERID_MAJOR_… argument
103 #define LPI2C_PARAM_MTXFIFO(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_PARAM_MTXFIF… argument
106 #define LPI2C_PARAM_MRXFIFO(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_PARAM_MRXFIF… argument
111 #define LPI2C_MCR_MEN(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCR_MEN_SHIF… argument
114 #define LPI2C_MCR_RST(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCR_RST_SHIF… argument
117 #define LPI2C_MCR_DOZEN(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCR_DOZEN_SH… argument
120 #define LPI2C_MCR_DBGEN(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCR_DBGEN_SH… argument
123 #define LPI2C_MCR_RTF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCR_RTF_SHIF… argument
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/rk3399_rockchip-uboot/arch/arm/mach-exynos/include/mach/
H A Dfb.h160 #define EXYNOS_WINCON(x) (x * 0x04) argument
161 #define EXYNOS_VIDOSD(x) (x * 0x10) argument
162 #define EXYNOS_BUFFER_OFFSET(x) (x * 0x08) argument
163 #define EXYNOS_BUFFER_SIZE(x) (x * 0x04) argument
192 #define EXYNOS_VIDCON0_CLKVAL_F(x) (((x) & 0xff) << 6) argument
242 #define EXYNOS_VIDTCON0_VBPDE(x) (((x) & 0xff) << 24) argument
243 #define EXYNOS_VIDTCON0_VBPD(x) (((x) & 0xff) << 16) argument
244 #define EXYNOS_VIDTCON0_VFPD(x) (((x) & 0xff) << 8) argument
245 #define EXYNOS_VIDTCON0_VSPW(x) (((x) & 0xff) << 0) argument
248 #define EXYNOS_VIDTCON1_VFPDE(x) (((x) & 0xff) << 24) argument
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/rk3399_rockchip-uboot/arch/arm/mach-at91/include/mach/
H A Dsama5d3_smc.h34 #define AT91_SMC_SETUP_NWE(x) (x & 0x3f) argument
35 #define AT91_SMC_SETUP_NCS_WR(x) ((x & 0x3f) << 8) argument
36 #define AT91_SMC_SETUP_NRD(x) ((x & 0x3f) << 16) argument
37 #define AT91_SMC_SETUP_NCS_RD(x) ((x & 0x3f) << 24) argument
39 #define AT91_SMC_PULSE_NWE(x) (x & 0x3f) argument
40 #define AT91_SMC_PULSE_NCS_WR(x) ((x & 0x3f) << 8) argument
41 #define AT91_SMC_PULSE_NRD(x) ((x & 0x3f) << 16) argument
42 #define AT91_SMC_PULSE_NCS_RD(x) ((x & 0x3f) << 24) argument
44 #define AT91_SMC_CYCLE_NWE(x) (x & 0x1ff) argument
45 #define AT91_SMC_CYCLE_NRD(x) ((x & 0x1ff) << 16) argument
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