Lines Matching refs:x
116 #define SBF_SBFCR_BLDIV(x) (((x)&0x000F)) /* Boot loader clock divider */ argument
139 #define CCM_CCR_360_PLLMULT2(x) (((x)&0x0003)) /* 2-Bit PLL clock mode */ argument
143 #define CCM_CCR_360_FBCONFIG(x) (((x)&0x0007)<<5) /* Flexbus/PCI port size configuration */ argument
144 #define CCM_CCR_360_PLLMULT3(x) (((x)&0x0007)) /* 3-Bit PLL Clock Mode */ argument
171 #define CCM_CCR_256_PLLMULT3(x) (((x)&0x0007)) /* 3-Bit PLL clock mode */ argument
174 #define CCM_CCR_256_FBCONFIG(x) (((x)&0x0007)<<5) /* Flexbus/PCI port size configuration */ argument
193 #define CCM_RCON_360_PLLMULT(x) (((x)&0x0003)) /* PLL clock mode */ argument
197 #define CCM_RCON_360_FBCONFIG(x) (((x)&0x0007)<<5) /* Flexbus/PCI port size configuration */ argument
200 #define CCM_RCON_256_PLLMULT(x) (((x)&0x0007)) /* PLL clock mode */ argument
203 #define CCM_RCON_256_FBCONFIG(x) (((x)&0x0007)<<5) /* Flexbus/PCI port size configuration */ argument
206 #define CCM_CIR_PRN(x) (((x)&0x003F)) /* Part revision number */ argument
207 #define CCM_CIR_PIN(x) (((x)&0x03FF)<<6) /* Part identification number */ argument
225 #define CCM_MISCCR_BMT(x) (((x)&0x0007)<<8) /* Bus monitor timing field */ argument
248 #define CCM_CDR_SSIDIV(x) (((x)&0x00FF)) /* SSI oversampling clock divider */ argument
249 #define CCM_CDR_LPDIV(x) (((x)&0x000F)<<8) /* Low power clock divider */ argument
271 #define GPIO_PAR_FEC_FEC0(x) (((x)&0x07)) argument
272 #define GPIO_PAR_FEC_FEC1(x) (((x)&0x07)<<4) argument
288 #define GPIO_PAR_DMA_DACK0(x) (((x)&0x03)<<2) argument
289 #define GPIO_PAR_DMA_DREQ1(x) (((x)&0x03)<<4) argument
290 #define GPIO_PAR_DMA_DACK1(x) (((x)&0x03)<<6) argument
308 #define GPIO_PAR_FBCTL_TS(x) (((x)&0x03)<<3) argument
350 #define GPIO_PAR_BE_BS2(x) (((x)&0x03)<<4) argument
351 #define GPIO_PAR_BE_BS3(x) (((x)&0x03)<<6) argument
377 #define GPIO_PAR_TIMER_T0IN(x) (((x)&0x03)) argument
378 #define GPIO_PAR_TIMER_T1IN(x) (((x)&0x03)<<2) argument
379 #define GPIO_PAR_TIMER_T2IN(x) (((x)&0x03)<<4) argument
380 #define GPIO_PAR_TIMER_T3IN(x) (((x)&0x03)<<6) argument
403 #define GPIO_PAR_USB_VBUSOC(x) (((x)&0x03)) argument
404 #define GPIO_PAR_USB_VBUSEN(x) (((x)&0x03)<<2) argument
442 #define GPIO_PAR_FECI2C_SDA(x) (((x)&0x0003)) argument
443 #define GPIO_PAR_FECI2C_SCL(x) (((x)&0x0003)<<2) argument
446 #define GPIO_PAR_FECI2C_MDIO1(x) (((x)&0x0003)<<8) argument
447 #define GPIO_PAR_FECI2C_MDC1(x) (((x)&0x0003)<<10) argument
471 #define GPIO_PAR_SSI_STXD(x) (((x)&0x0003)<<2) argument
472 #define GPIO_PAR_SSI_SRXD(x) (((x)&0x0003)<<4) argument
473 #define GPIO_PAR_SSI_FS(x) (((x)&0x0003)<<6) argument
474 #define GPIO_PAR_SSI_BCLK(x) (((x)&0x0003)<<8) argument
535 #define GPIO_PAR_PCI_REQ3(x) (((x)&0x0003)<<6) argument
539 #define GPIO_PAR_PCI_GNT3(x) (((x)&0x0003)<<14) argument
562 #define GPIO_MSCR_SDRAM_SDCTL(x) (((x)&0x03)) argument
563 #define GPIO_MSCR_SDRAM_SDCLK(x) (((x)&0x03)<<2) argument
564 #define GPIO_MSCR_SDRAM_SDDQS(x) (((x)&0x03)<<4) argument
565 #define GPIO_MSCR_SDRAM_SDDATA(x) (((x)&0x03)<<6) argument
593 #define GPIO_DSCR_I2C_I2C(x) (((x)&0x03)) argument
600 #define GPIO_DSCR_FLEXBUS_FBADL(x) (((x)&0x03)) argument
601 #define GPIO_DSCR_FLEXBUS_FBADH(x) (((x)&0x03)<<2) argument
602 #define GPIO_DSCR_FLEXBUS_FBCTL(x) (((x)&0x03)<<4) argument
603 #define GPIO_DSCR_FLEXBUS_FBCLK(x) (((x)&0x03)<<6) argument
622 #define GPIO_DSCR_FEC_FEC0(x) (((x)&0x03)) argument
623 #define GPIO_DSCR_FEC_FEC1(x) (((x)&0x03)<<2) argument
634 #define GPIO_DSCR_UART_UART0(x) (((x)&0x03)) argument
635 #define GPIO_DSCR_UART_UART1(x) (((x)&0x03)<<2) argument
646 #define GPIO_DSCR_DSPI_DSPI(x) (((x)&0x03)) argument
653 #define GPIO_DSCR_TIMER_TIMER(x) (((x)&0x03)) argument
660 #define GPIO_DSCR_SSI_SSI(x) (((x)&0x03)) argument
667 #define GPIO_DSCR_DMA_DMA(x) (((x)&0x03)) argument
674 #define GPIO_DSCR_DEBUG_DEBUG(x) (((x)&0x03)) argument
681 #define GPIO_DSCR_RESET_RESET(x) (((x)&0x03)) argument
688 #define GPIO_DSCR_IRQ_IRQ(x) (((x)&0x03)) argument
695 #define GPIO_DSCR_USB_USB(x) (((x)&0x03)) argument
702 #define GPIO_DSCR_ATA_ATA(x) (((x)&0x03)) argument
713 #define SDRAMC_SDMR_DDR2_AD(x) (((x)&0x00003FFF)) /* Address for DDR2 */ argument
715 #define SDRAMC_SDMR_AD(x) (((x)&0x00000FFF)<<18) /* Address */ argument
716 #define SDRAMC_SDMR_BK(x) (((x)&0x00000003)<<30) /* Bank Address */ argument
724 #define SDRAMC_SDCR_DQS_OE(x) (((x)&0x00000003)<<10) /* DQS Output Enable */ argument
726 #define SDRAMC_SDCR_REF_CNT(x) (((x)&0x0000003F)<<16) /* Periodic Refresh Counter */ argument
728 #define SDRAMC_SDCR_ADDR_MUX(x) (((x)&0x00000003)<<24) /* Internal Address Mux Select */ argument
737 #define SDRAMC_SDCFG1_WT_LAT(x) (((x)&0x00000007)<<4) /* Write Latency */ argument
738 #define SDRAMC_SDCFG1_REF2ACT(x) (((x)&0x0000000F)<<8) /* Refresh to active delay */ argument
739 #define SDRAMC_SDCFG1_PRE2ACT(x) (((x)&0x00000007)<<12) /* Precharge to active delay */ argument
740 #define SDRAMC_SDCFG1_ACT2RW(x) (((x)&0x00000007)<<16) /* Active to read/write delay */ argument
741 #define SDRAMC_SDCFG1_RD_LAT(x) (((x)&0x0000000F)<<20) /* Read CAS Latency */ argument
742 #define SDRAMC_SDCFG1_SWT2RWP(x) (((x)&0x00000007)<<24) /* Single write to read/write/precharge del… argument
743 #define SDRAMC_SDCFG1_SRD2RWP(x) (((x)&0x0000000F)<<28) /* Single read to read/write/precharge dela… argument
746 #define SDRAMC_SDCFG2_BL(x) (((x)&0x0000000F)<<16) /* Burst Length */ argument
747 #define SDRAMC_SDCFG2_BRD2W(x) (((x)&0x0000000F)<<20) /* Burst read to write delay */ argument
748 #define SDRAMC_SDCFG2_BWT2RWP(x) (((x)&0x0000000F)<<24) /* Burst write to read/write/precharge dela… argument
749 #define SDRAMC_SDCFG2_BRD2RP(x) (((x)&0x0000000F)<<28) /* Burst read to read/precharge delay */ argument
752 #define SDRAMC_SDCS_CSSZ(x) (((x)&0x0000001F)) /* Chip-Select Size */ argument
753 #define SDRAMC_SDCS_CSBA(x) (((x)&0x00000FFF)<<20) /* Chip-Select Base Address */ argument
754 #define SDRAMC_SDCS_BA(x) ((x)&0xFFF00000) argument
775 #define PLL_PCR_OUTDIV1(x) (((x)&0x0000000F)) /* Output divider for CPU clock frequency */ argument
776 #define PLL_PCR_OUTDIV2(x) (((x)&0x0000000F)<<4) /* Output divider for internal bus clock frequenc… argument
777 #define PLL_PCR_OUTDIV3(x) (((x)&0x0000000F)<<8) /* Output divider for Flexbus clock frequency */ argument
778 #define PLL_PCR_OUTDIV4(x) (((x)&0x0000000F)<<12) /* Output divider for PCI clock frequency */ argument
779 #define PLL_PCR_OUTDIV5(x) (((x)&0x0000000F)<<16) /* Output divider for USB clock frequency */ argument
780 #define PLL_PCR_PFDR(x) (((x)&0x000000FF)<<24) /* Feedback divider for VCO frequency */ argument
821 #define PCI_CR1_BIST(x) ((x & 0xFF) << 24) /* Built in self test */ argument
822 #define PCI_CR1_HDR(x) ((x & 0xFF) << 16) /* Header type */ argument
823 #define PCI_CR1_LTMR(x) ((x & 0xF8) << 8) /* Latency timer */ argument
824 #define PCI_CR1_CLS(x) (x & 0x0F) /* Cache line size */ argument
826 #define PCI_BAR_BAR0(x) (x & 0xFFFC0000) argument
827 #define PCI_BAR_BAR1(x) (x & 0xFFF00000) argument
828 #define PCI_BAR_BAR2(x) (x & 0xFFC00000) argument
829 #define PCI_BAR_BAR3(x) (x & 0xFF000000) argument
830 #define PCI_BAR_BAR4(x) (x & 0xF8000000) argument
831 #define PCI_BAR_BAR5(x) (x & 0xE0000000) argument
836 #define PCI_CR2_MAXLAT(x) ((x & 0xFF) << 24) /* Maximum latency */ argument
837 #define PCI_CR2_MINGNT(x) ((x & 0xFF) << 16) /* Minimum grant */ argument
838 #define PCI_CR2_INTPIN(x) ((x & 0xFF) << 8) /* Interrupt Pin */ argument
839 #define PCI_CR2_INTLIN(x) (x & 0xFF) /* Interrupt Line */ argument
863 #define PCI_TBATR_BAT(x) ((x & 0xFFF) << 20) argument
885 #define PCI_ICR_MAXRETRY(x) ((x) & 0x000000FF) argument