34 #define AT91_SMC_SETUP_NWE(x)		(x & 0x3f)  argument
35 #define AT91_SMC_SETUP_NCS_WR(x)	((x & 0x3f) << 8)  argument
36 #define AT91_SMC_SETUP_NRD(x)		((x & 0x3f) << 16)  argument
37 #define AT91_SMC_SETUP_NCS_RD(x)	((x & 0x3f) << 24)  argument
39 #define AT91_SMC_PULSE_NWE(x)		(x & 0x3f)  argument
40 #define AT91_SMC_PULSE_NCS_WR(x)	((x & 0x3f) << 8)  argument
41 #define AT91_SMC_PULSE_NRD(x)		((x & 0x3f) << 16)  argument
42 #define AT91_SMC_PULSE_NCS_RD(x)	((x & 0x3f) << 24)  argument
44 #define AT91_SMC_CYCLE_NWE(x)		(x & 0x1ff)  argument
45 #define AT91_SMC_CYCLE_NRD(x)		((x & 0x1ff) << 16)  argument
47 #define AT91_SMC_TIMINGS_TCLR(x)	(x & 0xf)  argument
48 #define AT91_SMC_TIMINGS_TADL(x)	((x & 0xf) << 4)  argument
49 #define AT91_SMC_TIMINGS_TAR(x)		((x & 0xf) << 8)  argument
50 #define AT91_SMC_TIMINGS_OCMS(x)	((x & 0x1) << 12)  argument
51 #define AT91_SMC_TIMINGS_TRR(x)		((x & 0xf) << 16)  argument
52 #define AT91_SMC_TIMINGS_TWB(x)		((x & 0xf) << 24)  argument
53 #define AT91_SMC_TIMINGS_RBNSEL(x)	((x & 0xf) << 28)  argument
54 #define AT91_SMC_TIMINGS_NFSEL(x)	((x & 0x1) << 31)  argument
69 #define AT91_SMC_MODE_TDF_CYCLE(x)	((x & 0xf) << 16)  argument