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Searched refs:reg_val (Results 1 – 25 of 34) sorted by relevance

12

/rk3399_rockchip-uboot/drivers/net/phy/
H A Dmscc.c139 u16 reg_val; in mscc_vsc8531_vsc8541_init_scripts() local
149 reg_val = phy_read(phydev, MDIO_DEVAD_NONE, MSCC_PHY_REG_TR_DATA_17); in mscc_vsc8531_vsc8541_init_scripts()
150 reg_val = bitfield_replace(reg_val, MSCC_PHY_TR_LINKDETCTRL_POS, in mscc_vsc8531_vsc8541_init_scripts()
154 phy_write(phydev, MDIO_DEVAD_NONE, MSCC_PHY_REG_TR_DATA_17, reg_val); in mscc_vsc8531_vsc8541_init_scripts()
163 reg_val = phy_read(phydev, MDIO_DEVAD_NONE, MSCC_PHY_REG_TR_DATA_18); in mscc_vsc8531_vsc8541_init_scripts()
164 reg_val = bitfield_replace(reg_val, MSCC_PHY_TR_VGATHRESH100_POS, in mscc_vsc8531_vsc8541_init_scripts()
168 phy_write(phydev, MDIO_DEVAD_NONE, MSCC_PHY_REG_TR_DATA_18, reg_val); in mscc_vsc8531_vsc8541_init_scripts()
177 reg_val = phy_read(phydev, MDIO_DEVAD_NONE, MSCC_PHY_REG_TR_DATA_18); in mscc_vsc8531_vsc8541_init_scripts()
178 reg_val = bitfield_replace(reg_val, MSCC_PHY_TR_VGAGAIN10_U_POS, in mscc_vsc8531_vsc8541_init_scripts()
182 phy_write(phydev, MDIO_DEVAD_NONE, MSCC_PHY_REG_TR_DATA_18, reg_val); in mscc_vsc8531_vsc8541_init_scripts()
[all …]
H A Dbroadcom.c41 int reg_val; in bcm_phy_write_misc() local
46 reg_val = phy_read(phydev, MDIO_DEVAD_NONE, MIIM_BCM54xx_AUXCNTL); in bcm_phy_write_misc()
47 reg_val |= MIIM_BCM_AUXCNTL_ACTL_SMDSP_EN; in bcm_phy_write_misc()
48 phy_write(phydev, MDIO_DEVAD_NONE, MIIM_BCM54xx_AUXCNTL, reg_val); in bcm_phy_write_misc()
50 reg_val = (chl * MIIM_BCM_CHANNEL_WIDTH) | reg; in bcm_phy_write_misc()
51 phy_write(phydev, MDIO_DEVAD_NONE, MIIM_BCM54XX_EXP_SEL, reg_val); in bcm_phy_write_misc()
/rk3399_rockchip-uboot/drivers/usb/musb-new/
H A Dsunxi.c86 static u32 USBC_WakeUp_ClearChangeDetect(u32 reg_val) in USBC_WakeUp_ClearChangeDetect() argument
88 u32 temp = reg_val; in USBC_WakeUp_ClearChangeDetect()
99 u32 reg_val; in USBC_EnableIdPullUp() local
101 reg_val = musb_readl(base, USBC_REG_o_ISCR); in USBC_EnableIdPullUp()
102 reg_val |= (1 << USBC_BP_ISCR_ID_PULLUP_EN); in USBC_EnableIdPullUp()
103 reg_val = USBC_WakeUp_ClearChangeDetect(reg_val); in USBC_EnableIdPullUp()
104 musb_writel(base, USBC_REG_o_ISCR, reg_val); in USBC_EnableIdPullUp()
109 u32 reg_val; in USBC_EnableDpDmPullUp() local
111 reg_val = musb_readl(base, USBC_REG_o_ISCR); in USBC_EnableDpDmPullUp()
112 reg_val |= (1 << USBC_BP_ISCR_DPDM_PULLUP_EN); in USBC_EnableDpDmPullUp()
[all …]
/rk3399_rockchip-uboot/drivers/mtd/nand/raw/
H A Darasan_nfc.c267 u32 reg_val; in arasan_nand_select_chip() local
269 reg_val = readl(&arasan_nand_base->memadr_reg2); in arasan_nand_select_chip()
271 reg_val &= ~ARASAN_NAND_MEM_ADDR2_CS0_MASK; in arasan_nand_select_chip()
272 writel(reg_val, &arasan_nand_base->memadr_reg2); in arasan_nand_select_chip()
274 reg_val |= ARASAN_NAND_MEM_ADDR2_CS1_MASK; in arasan_nand_select_chip()
275 writel(reg_val, &arasan_nand_base->memadr_reg2); in arasan_nand_select_chip()
281 u32 reg_val; in arasan_nand_enable_ecc() local
283 reg_val = readl(&arasan_nand_base->cmd_reg); in arasan_nand_enable_ecc()
284 reg_val |= ARASAN_NAND_CMD_ECC_ON_MASK; in arasan_nand_enable_ecc()
286 writel(reg_val, &arasan_nand_base->cmd_reg); in arasan_nand_enable_ecc()
[all …]
H A Dtegra_nand.c118 u32 reg_val; in nand_waitfor_cmd_completion() local
129 reg_val = readl(&reg->dma_mst_ctrl); in nand_waitfor_cmd_completion()
137 running = reg_val & (DMA_MST_CTRL_EN_A_ENABLE | in nand_waitfor_cmd_completion()
139 if (!running || (reg_val & DMA_MST_CTRL_IS_DMA_DONE)) in nand_waitfor_cmd_completion()
208 int reg_val; in nand_dev_ready() local
213 reg_val = readl(&info->reg->status); in nand_dev_ready()
214 if (reg_val & STATUS_RBSY0) in nand_dev_ready()
240 u32 reg_val; in nand_clear_interrupt_status() local
243 reg_val = readl(&reg->isr); in nand_clear_interrupt_status()
244 writel(reg_val, &reg->isr); in nand_clear_interrupt_status()
[all …]
H A Dkmeter1_nand.c51 u8 reg_val = read_mode(); in kpn_nand_hwcontrol() local
54 reg_val = reg_val & ~(KPN_ALE + KPN_CLE); in kpn_nand_hwcontrol()
57 reg_val = reg_val | KPN_CLE; in kpn_nand_hwcontrol()
59 reg_val = reg_val | KPN_ALE; in kpn_nand_hwcontrol()
61 reg_val = reg_val & ~KPN_CE1N; in kpn_nand_hwcontrol()
63 reg_val = reg_val | KPN_CE1N; in kpn_nand_hwcontrol()
65 write_mode(reg_val); in kpn_nand_hwcontrol()
/rk3399_rockchip-uboot/drivers/video/tegra124/
H A Dsor.c65 u32 reg_val = tegra_sor_readl(sor, reg); in tegra_sor_write_field() local
66 reg_val &= ~mask; in tegra_sor_write_field()
67 reg_val |= val; in tegra_sor_write_field()
68 tegra_sor_writel(sor, reg, reg_val); in tegra_sor_write_field()
96 u32 reg_val = 0; in tegra_dc_sor_poll_register() local
101 reg_val = tegra_sor_readl(sor, reg); in tegra_dc_sor_poll_register()
102 if (((reg_val & mask) == exp_val)) in tegra_dc_sor_poll_register()
108 reg, reg_val, mask, exp_val); in tegra_dc_sor_poll_register()
116 u32 reg_val; in tegra_dc_sor_set_power_state() local
121 reg_val = pu_pd ? PWR_NORMAL_STATE_PU : in tegra_dc_sor_set_power_state()
[all …]
H A Ddp.c60 u32 reg_val = 0; in tegra_dc_dpaux_poll_register() local
65 reg_val = tegra_dpaux_readl(dp, reg); in tegra_dc_dpaux_poll_register()
70 } while ((reg_val & mask) != exp_val); in tegra_dc_dpaux_poll_register()
72 if ((reg_val & mask) == exp_val) in tegra_dc_dpaux_poll_register()
75 reg, reg_val, mask, exp_val); in tegra_dc_dpaux_poll_register()
98 u32 reg_val; in tegra_dc_dpaux_write_chunk() local
124 reg_val = tegra_dpaux_readl(dp, DPAUX_DP_AUXCTL); in tegra_dc_dpaux_write_chunk()
125 reg_val &= ~DPAUX_DP_AUXCTL_CMD_MASK; in tegra_dc_dpaux_write_chunk()
126 reg_val |= cmd; in tegra_dc_dpaux_write_chunk()
127 reg_val &= ~DPAUX_DP_AUXCTL_CMDLEN_FIELD; in tegra_dc_dpaux_write_chunk()
[all …]
/rk3399_rockchip-uboot/arch/arm/mach-sunxi/
H A Ddram_sun4i.c67 u32 reg_val; in mctl_ddr3_reset() local
70 reg_val = readl(&timer->cpu_cfg); in mctl_ddr3_reset()
72 if ((reg_val & CPU_CFG_CHIP_VER_MASK) != in mctl_ddr3_reset()
240 u32 reg_val; in mctl_setup_dram_clock() local
247 reg_val = readl(&ccm->pll5_cfg); in mctl_setup_dram_clock()
248 reg_val &= ~CCM_PLL5_CTRL_M_MASK; /* set M to 0 (x1) */ in mctl_setup_dram_clock()
249 reg_val &= ~CCM_PLL5_CTRL_K_MASK; /* set K to 0 (x1) */ in mctl_setup_dram_clock()
250 reg_val &= ~CCM_PLL5_CTRL_N_MASK; /* set N to 0 (x0) */ in mctl_setup_dram_clock()
251 reg_val &= ~CCM_PLL5_CTRL_P_MASK; /* set P to 0 (x1) */ in mctl_setup_dram_clock()
254 reg_val |= CCM_PLL5_CTRL_P(1); in mctl_setup_dram_clock()
[all …]
H A Dcpu_info.c117 uint32_t reg_val; in sun8i_efuse_read() local
119 reg_val = readl(SUNXI_SIDC_BASE + SIDC_PRCTL); in sun8i_efuse_read()
120 reg_val &= ~(((0x1ff) << 16) | 0x3); in sun8i_efuse_read()
121 reg_val |= (offset << 16); in sun8i_efuse_read()
122 writel(reg_val, SUNXI_SIDC_BASE + SIDC_PRCTL); in sun8i_efuse_read()
124 reg_val &= ~(((0xff) << 8) | 0x3); in sun8i_efuse_read()
125 reg_val |= (SIDC_OP_LOCK << 8) | 0x2; in sun8i_efuse_read()
126 writel(reg_val, SUNXI_SIDC_BASE + SIDC_PRCTL); in sun8i_efuse_read()
130 reg_val &= ~(((0x1ff) << 16) | ((0xff) << 8) | 0x3); in sun8i_efuse_read()
131 writel(reg_val, SUNXI_SIDC_BASE + SIDC_PRCTL); in sun8i_efuse_read()
[all …]
H A Ddram_sun8i_a33.c91 u32 reg_val; in auto_set_timing_para() local
139 reg_val = (twtp << 24) | (tfaw << 16) | (trasmax << 8) | (tras << 0); in auto_set_timing_para()
140 writel(reg_val, &mctl_ctl->dramtmg0); in auto_set_timing_para()
141 reg_val = (txp << 16) | (trtp << 8) | (trc << 0); in auto_set_timing_para()
142 writel(reg_val, &mctl_ctl->dramtmg1); in auto_set_timing_para()
143 reg_val = (tcwl << 24) | (tcl << 16) | (trd2wr << 8) | (twr2rd << 0); in auto_set_timing_para()
144 writel(reg_val, &mctl_ctl->dramtmg2); in auto_set_timing_para()
145 reg_val = (tmrw << 16) | (tmrd << 12) | (tmod << 0); in auto_set_timing_para()
146 writel(reg_val, &mctl_ctl->dramtmg3); in auto_set_timing_para()
147 reg_val = (trcd << 24) | (tccd << 16) | (trrd << 8) | (trp << 0); in auto_set_timing_para()
[all …]
H A Ddram_sun8i_a83t.c91 u32 reg_val; in auto_set_timing_para() local
171 reg_val = (twtp << 24) | (tfaw << 16) | (trasmax << 8) | (tras << 0); in auto_set_timing_para()
172 writel(reg_val, &mctl_ctl->dramtmg0); in auto_set_timing_para()
173 reg_val = (txp << 16) | (trtp << 8) | (trc << 0); in auto_set_timing_para()
174 writel(reg_val, &mctl_ctl->dramtmg1); in auto_set_timing_para()
175 reg_val = (tcwl << 24) | (tcl << 16) | (trd2wr << 8) | (twr2rd << 0); in auto_set_timing_para()
176 writel(reg_val, &mctl_ctl->dramtmg2); in auto_set_timing_para()
177 reg_val = (tmrw << 16) | (tmrd << 12) | (tmod << 0); in auto_set_timing_para()
178 writel(reg_val, &mctl_ctl->dramtmg3); in auto_set_timing_para()
179 reg_val = (trcd << 24) | (tccd << 16) | (trrd << 8) | (trp << 0); in auto_set_timing_para()
[all …]
H A Ddram_sunxi_dw.c282 u32 reg_val; in mctl_h3_zq_calibration_quirk() local
290 reg_val = readl(&mctl_ctl->zqdr[0]); in mctl_h3_zq_calibration_quirk()
291 reg_val &= (0x1f << 16) | (0x1f << 0); in mctl_h3_zq_calibration_quirk()
292 reg_val |= reg_val << 8; in mctl_h3_zq_calibration_quirk()
293 writel(reg_val, &mctl_ctl->zqdr[0]); in mctl_h3_zq_calibration_quirk()
295 reg_val = readl(&mctl_ctl->zqdr[1]); in mctl_h3_zq_calibration_quirk()
296 reg_val &= (0x1f << 16) | (0x1f << 0); in mctl_h3_zq_calibration_quirk()
297 reg_val |= reg_val << 8; in mctl_h3_zq_calibration_quirk()
298 writel(reg_val, &mctl_ctl->zqdr[1]); in mctl_h3_zq_calibration_quirk()
299 writel(reg_val, &mctl_ctl->zqdr[2]); in mctl_h3_zq_calibration_quirk()
H A Ddram_sun9i.c831 unsigned int reg_val; in DRAMC_get_dram_size() local
835 reg_val = readl(&mctl_com->cr); in DRAMC_get_dram_size()
837 temp = (reg_val >> 8) & 0xf; /* page size code */ in DRAMC_get_dram_size()
840 temp = (reg_val >> 4) & 0xf; /* row width code */ in DRAMC_get_dram_size()
843 temp = (reg_val >> 2) & 0x3; /* bank number code */ in DRAMC_get_dram_size()
846 temp = reg_val & 0x3; /* rank number code */ in DRAMC_get_dram_size()
849 temp = (reg_val >> 19) & 0x1; /* channel number code */ in DRAMC_get_dram_size()
/rk3399_rockchip-uboot/include/
H A Dbitfield.h49 static inline uint bitfield_extract(uint reg_val, uint shift, uint width) in bitfield_extract() argument
51 return (reg_val & bitfield_mask(shift, width)) >> shift; in bitfield_extract()
58 static inline uint bitfield_replace(uint reg_val, uint shift, uint width, in bitfield_replace() argument
63 return (reg_val & ~mask) | ((bitfield_val << shift) & mask); in bitfield_replace()
73 static inline uint bitfield_extract_by_mask(uint reg_val, uint mask) in bitfield_extract_by_mask() argument
77 return (reg_val & mask) >> shift; in bitfield_extract_by_mask()
84 static inline uint bitfield_replace_by_mask(uint reg_val, uint mask, in bitfield_replace_by_mask() argument
89 return (reg_val & ~mask) | ((bitfield_val << shift) & mask); in bitfield_replace_by_mask()
/rk3399_rockchip-uboot/drivers/power/fuel_gauge/
H A Dfg_cw221x.c342 unsigned char reg_val = CONFIG_MODE_RESTART; in cw221X_active() local
344 cw221x_write(cw221x, REG_MODE_CONFIG, reg_val); in cw221X_active()
346 reg_val = CONFIG_MODE_ACTIVE; in cw221X_active()
347 cw221x_write(cw221x, REG_MODE_CONFIG, reg_val); in cw221X_active()
355 unsigned char reg_val = CONFIG_MODE_RESTART; in cw221X_sleep() local
357 cw221x_write(cw221x, REG_MODE_CONFIG, reg_val); in cw221X_sleep()
359 reg_val = CONFIG_MODE_SLEEP; in cw221X_sleep()
360 cw221x_write(cw221x, REG_MODE_CONFIG, reg_val); in cw221X_sleep()
388 unsigned char reg_val; in cw221X_get_state() local
392 ret = cw221x_read(cw221x, REG_MODE_CONFIG, &reg_val); in cw221X_get_state()
[all …]
/rk3399_rockchip-uboot/arch/arm/mach-omap2/
H A Dvc.c101 u32 reg_val; in omap_vc_bypass_send_value() local
108 reg_val = sa << PRM_VC_VAL_BYPASS_SLAVEADDR_SHIFT | in omap_vc_bypass_send_value()
111 writel(reg_val, (*prcm)->prm_vc_val_bypass); in omap_vc_bypass_send_value()
114 writel(reg_val | PRM_VC_VAL_BYPASS_VALID_BIT, in omap_vc_bypass_send_value()
119 reg_val = readl((*prcm)->prm_vc_val_bypass) & in omap_vc_bypass_send_value()
121 if (!reg_val) in omap_vc_bypass_send_value()
/rk3399_rockchip-uboot/arch/arm/mach-mvebu/serdes/a38x/
H A Dsys_env_lib.h110 #define REF_CLK_SELECTOR_VAL_PEX0(reg_val) (reg_val >> 2) & 0x1 argument
111 #define REF_CLK_SELECTOR_VAL_PEX1(reg_val) (reg_val >> 3) & 0x1 argument
112 #define REF_CLK_SELECTOR_VAL_PEX2(reg_val) (reg_val >> 30) & 0x1 argument
113 #define REF_CLK_SELECTOR_VAL_PEX3(reg_val) (reg_val >> 31) & 0x1 argument
114 #define REF_CLK_SELECTOR_VAL(reg_val) (reg_val & 0x1) argument
/rk3399_rockchip-uboot/drivers/power/regulator/
H A Dsandbox.c85 uint8_t reg_val; in out_get_value() local
96 ret = pmic_read(dev->parent, reg, &reg_val, 1); in out_get_value()
104 reg_val); in out_get_value()
112 uint8_t reg_val; in out_set_value() local
130 reg_val = VAL2REG(range[dev->driver_data - 1].min, in out_set_value()
135 ret = pmic_write(dev->parent, reg, &reg_val, 1); in out_set_value()
147 uint8_t reg_val; in out_get_mode() local
155 ret = pmic_read(dev->parent, reg, &reg_val, 1); in out_get_mode()
162 if (reg_val == uc_pdata->mode[i].register_value) in out_get_mode()
173 int reg_val = -1; in out_set_mode() local
[all …]
/rk3399_rockchip-uboot/drivers/power/charge/
H A Dsgm41542_charger.c230 u8 reg_val; in sgm4154x_set_input_curr_lim() local
240 reg_val = (iindpm - SGM4154x_IINDPM_I_MIN_uA) / SGM4154x_IINDPM_STEP_uA; in sgm4154x_set_input_curr_lim()
245 reg_val); in sgm4154x_set_input_curr_lim()
266 u8 reg_val; in sgm4154x_set_ichrg_curr() local
274 reg_val = uA / SGM4154x_ICHRG_I_STEP_uA; in sgm4154x_set_ichrg_curr()
279 reg_val); in sgm4154x_set_ichrg_curr()
288 u8 reg_val; in sgm4154x_set_prechrg_curr() local
296 reg_val = (uA - SGM4154x_PRECHRG_I_MIN_uA) / SGM4154x_PRECHRG_CURRENT_STEP_uA; in sgm4154x_set_prechrg_curr()
298 reg_val = reg_val << 4; in sgm4154x_set_prechrg_curr()
302 reg_val); in sgm4154x_set_prechrg_curr()
[all …]
/rk3399_rockchip-uboot/board/sunxi/
H A Dahci.c19 u32 reg_val; in sunxi_ahci_phy_init() local
42 reg_val = readl(reg_base + AHCI_PHYCS0R) & (0x7 << 28); in sunxi_ahci_phy_init()
43 if (reg_val == (0x2 << 28)) in sunxi_ahci_phy_init()
56 reg_val = readl(reg_base + AHCI_PHYCS2R) & (0x1 << 24); in sunxi_ahci_phy_init()
57 if (reg_val == 0x0) in sunxi_ahci_phy_init()
/rk3399_rockchip-uboot/arch/arm/mach-exynos/
H A Dlowlevel_init.c66 uint32_t val, reg_val; in low_power_start() local
68 reg_val = readl(EXYNOS5420_SPARE_BASE); in low_power_start()
69 if (reg_val != CPU_RST_FLAG_VAL) { in low_power_start()
74 reg_val = readl(CONFIG_PHY_IRAM_BASE + 0x4); in low_power_start()
75 if (reg_val != (uint32_t)&low_power_start) { in low_power_start()
/rk3399_rockchip-uboot/arch/arm/mach-zynq/
H A Dslcr.c128 u32 reg_val; in zynq_slcr_devcfg_disable() local
136 reg_val = readl(&slcr_base->lvl_shftr_en); in zynq_slcr_devcfg_disable()
137 reg_val &= ~0xF; in zynq_slcr_devcfg_disable()
138 writel(reg_val, &slcr_base->lvl_shftr_en); in zynq_slcr_devcfg_disable()
/rk3399_rockchip-uboot/drivers/net/
H A Dsunxi_emac.c285 u32 reg_val; in emac_setup() local
298 reg_val = 0; in emac_setup()
300 reg_val = (0x1 << 0); in emac_setup()
301 writel(EMAC_MAC_CTL1_SETUP | reg_val, &regs->mac_ctl1); in emac_setup()
412 u32 reg_val; in _sunxi_emac_eth_recv() local
430 reg_val = readl(&regs->rx_io_data); in _sunxi_emac_eth_recv()
431 if (reg_val != 0x0143414d) { in _sunxi_emac_eth_recv()
/rk3399_rockchip-uboot/drivers/irq/
H A Dvirq.c330 uint reg_val; in __virq_enable() local
349 reg_val = chip->read(desc->parent, mask_reg); in __virq_enable()
351 reg_val &= ~mask_val; in __virq_enable()
353 reg_val |= mask_val; in __virq_enable()
355 ret = chip->write(desc->parent, mask_reg, reg_val); in __virq_enable()

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