Lines Matching refs:reg_val
118 u32 reg_val; in nand_waitfor_cmd_completion() local
129 reg_val = readl(®->dma_mst_ctrl); in nand_waitfor_cmd_completion()
137 running = reg_val & (DMA_MST_CTRL_EN_A_ENABLE | in nand_waitfor_cmd_completion()
139 if (!running || (reg_val & DMA_MST_CTRL_IS_DMA_DONE)) in nand_waitfor_cmd_completion()
208 int reg_val; in nand_dev_ready() local
213 reg_val = readl(&info->reg->status); in nand_dev_ready()
214 if (reg_val & STATUS_RBSY0) in nand_dev_ready()
240 u32 reg_val; in nand_clear_interrupt_status() local
243 reg_val = readl(®->isr); in nand_clear_interrupt_status()
244 writel(reg_val, ®->isr); in nand_clear_interrupt_status()
392 u32 reg_val; in check_ecc_error() local
401 reg_val = readl(®->dec_status); in check_ecc_error()
402 if ((reg_val & DEC_STATUS_A_ECC_FAIL) && databuf) { in check_ecc_error()
403 reg_val = readl(®->bch_dec_status_buf); in check_ecc_error()
409 if ((reg_val & BCH_DEC_STATUS_FAIL_SEC_FLAG_MASK) && in check_ecc_error()
414 if ((reg_val & DEC_STATUS_B_ECC_FAIL) && oobbuf) { in check_ecc_error()
415 reg_val = readl(®->bch_dec_status_buf); in check_ecc_error()
421 if ((reg_val & BCH_DEC_STATUS_FAIL_TAG_MASK) && in check_ecc_error()
436 u32 reg_val; in start_command() local
438 reg_val = readl(®->command); in start_command()
439 reg_val |= CMD_GO; in start_command()
440 writel(reg_val, ®->command); in start_command()
467 struct fdt_nand *config, u32 *reg_val) in set_bus_width_page_size() argument
470 *reg_val = CFG_BUS_WIDTH_8BIT; in set_bus_width_page_size()
472 *reg_val = CFG_BUS_WIDTH_16BIT; in set_bus_width_page_size()
480 *reg_val |= CFG_PAGE_SIZE_512; in set_bus_width_page_size()
482 *reg_val |= CFG_PAGE_SIZE_2048; in set_bus_width_page_size()
484 *reg_val |= CFG_PAGE_SIZE_4096; in set_bus_width_page_size()
509 u32 reg_val; in nand_rw_page() local
527 if (set_bus_width_page_size(mtd, config, ®_val)) in nand_rw_page()
551 reg_val |= (CFG_SKIP_SPARE_SEL_4 in nand_rw_page()
566 reg_val |= (CFG_SKIP_SPARE_DISABLE in nand_rw_page()
574 writel(reg_val, &info->reg->config); in nand_rw_page()
581 reg_val = CMD_CLE | CMD_ALE in nand_rw_page()
589 reg_val |= (CMD_AFT_DAT_DISABLE | CMD_RX); in nand_rw_page()
591 reg_val |= (CMD_AFT_DAT_ENABLE | CMD_TX); in nand_rw_page()
592 writel(reg_val, &info->reg->command); in nand_rw_page()
595 reg_val = DMA_MST_CTRL_GO_ENABLE in nand_rw_page()
601 reg_val |= DMA_MST_CTRL_DIR_READ; in nand_rw_page()
603 reg_val |= DMA_MST_CTRL_DIR_WRITE; in nand_rw_page()
605 writel(reg_val, &info->reg->dma_mst_ctrl); in nand_rw_page()
631 reg_val = (u32)check_ecc_error(info->reg, (u8 *)buf, in nand_rw_page()
635 if (reg_val & ECC_TAG_ERROR) in nand_rw_page()
637 if (reg_val & ECC_DATA_ERROR) in nand_rw_page()
640 if (reg_val & (ECC_DATA_ERROR | ECC_TAG_ERROR)) in nand_rw_page()
725 u32 reg_val; in nand_rw_oob() local
735 if (set_bus_width_page_size(mtd, &info->config, ®_val)) in nand_rw_oob()
743 reg_val |= CFG_ECC_EN_TAG_ENABLE; in nand_rw_oob()
745 reg_val |= (CFG_ECC_EN_TAG_DISABLE); in nand_rw_oob()
747 reg_val |= ((tag_size - 1) | in nand_rw_oob()
751 writel(reg_val, &info->reg->config); in nand_rw_oob()
771 reg_val = CMD_CLE | CMD_ALE in nand_rw_oob()
777 reg_val |= (CMD_AFT_DAT_DISABLE | CMD_RX); in nand_rw_oob()
779 reg_val |= (CMD_AFT_DAT_ENABLE | CMD_TX); in nand_rw_oob()
780 writel(reg_val, &info->reg->command); in nand_rw_oob()
783 reg_val = DMA_MST_CTRL_GO_ENABLE in nand_rw_oob()
787 reg_val |= DMA_MST_CTRL_DIR_READ; in nand_rw_oob()
789 reg_val |= DMA_MST_CTRL_DIR_WRITE; in nand_rw_oob()
791 writel(reg_val, &info->reg->dma_mst_ctrl); in nand_rw_oob()
806 reg_val = (u32)check_ecc_error(info->reg, 0, 0, in nand_rw_oob()
809 if (reg_val & ECC_TAG_ERROR) in nand_rw_oob()
857 u32 reg_val, clk_rate, clk_period, time_val; in setup_timing() local
862 reg_val = ((timing[FDT_NAND_MAX_TRP_TREA] / clk_period) << in setup_timing()
864 reg_val |= ((timing[FDT_NAND_TWB] / clk_period) << in setup_timing()
868 reg_val |= ((time_val - 2) << TIMING_TCR_TAR_TRR_CNT_SHIFT) & in setup_timing()
870 reg_val |= ((timing[FDT_NAND_TWHR] / clk_period) << in setup_timing()
874 reg_val |= ((time_val - 1) << TIMING_TCS_CNT_SHIFT) & in setup_timing()
876 reg_val |= ((timing[FDT_NAND_TWH] / clk_period) << in setup_timing()
878 reg_val |= ((timing[FDT_NAND_TWP] / clk_period) << in setup_timing()
880 reg_val |= ((timing[FDT_NAND_TRH] / clk_period) << in setup_timing()
882 reg_val |= ((timing[FDT_NAND_MAX_TRP_TREA] / clk_period) << in setup_timing()
884 writel(reg_val, ®->timing); in setup_timing()
886 reg_val = 0; in setup_timing()
889 reg_val = (time_val - 2) & TIMING2_TADL_CNT_MASK; in setup_timing()
890 writel(reg_val, ®->timing2); in setup_timing()