xref: /rk3399_rockchip-uboot/arch/arm/mach-omap2/vc.c (revision 302acbede91d7dc8b6bedad69679b9fc63963ea2)
1983e3700STom Rini /*
2983e3700STom Rini  * Voltage Controller implementation for OMAP
3983e3700STom Rini  *
4983e3700STom Rini  * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/
5983e3700STom Rini  *	Nishanth Menon
6983e3700STom Rini  *
7983e3700STom Rini  * This program is free software; you can redistribute it and/or modify
8983e3700STom Rini  * it under the terms of the GNU General Public License version 2 as
9983e3700STom Rini  * published by the Free Software Foundation.
10983e3700STom Rini  *
11983e3700STom Rini  * This program is distributed "as is" WITHOUT ANY WARRANTY of any
12983e3700STom Rini  * kind, whether express or implied; without even the implied warranty
13983e3700STom Rini  * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
14983e3700STom Rini  * GNU General Public License for more details.
15983e3700STom Rini  */
16983e3700STom Rini 
17983e3700STom Rini #include <common.h>
18983e3700STom Rini #include <asm/omap_common.h>
19983e3700STom Rini #include <asm/arch/sys_proto.h>
20983e3700STom Rini #include <asm/arch/clock.h>
21983e3700STom Rini 
22983e3700STom Rini /* Register defines and masks for VC IP Block */
23983e3700STom Rini /* PRM_VC_CFG_I2C_MODE */
24983e3700STom Rini #define PRM_VC_CFG_I2C_MODE_DFILTEREN_BIT	(0x1 << 6)
25983e3700STom Rini #define PRM_VC_CFG_I2C_MODE_SRMODEEN_BIT	(0x1 << 4)
26983e3700STom Rini #define PRM_VC_CFG_I2C_MODE_HSMODEEN_BIT	(0x1 << 3)
27983e3700STom Rini #define PRM_VC_CFG_I2C_MODE_HSMCODE_SHIFT	0x0
28983e3700STom Rini #define PRM_VC_CFG_I2C_MODE_HSMCODE_MASK	0x3
29983e3700STom Rini 
30983e3700STom Rini /* PRM_VC_CFG_I2C_CLK */
31983e3700STom Rini #define PRM_VC_CFG_I2C_CLK_HSCLL_SHIFT		24
32983e3700STom Rini #define PRM_VC_CFG_I2C_CLK_HSCLL_MASK		0xFF
33983e3700STom Rini #define PRM_VC_CFG_I2C_CLK_HSCLH_SHIFT		16
34983e3700STom Rini #define PRM_VC_CFG_I2C_CLK_HSCLH_MASK		0xFF
35983e3700STom Rini #define PRM_VC_CFG_I2C_CLK_SCLH_SHIFT		0
36983e3700STom Rini #define PRM_VC_CFG_I2C_CLK_SCLH_MASK		0xFF
37983e3700STom Rini #define PRM_VC_CFG_I2C_CLK_SCLL_SHIFT		8
38983e3700STom Rini #define PRM_VC_CFG_I2C_CLK_SCLL_MASK		(0xFF << 8)
39983e3700STom Rini 
40983e3700STom Rini /* PRM_VC_VAL_BYPASS */
41983e3700STom Rini #define PRM_VC_VAL_BYPASS_VALID_BIT		(0x1 << 24)
42983e3700STom Rini #define PRM_VC_VAL_BYPASS_SLAVEADDR_SHIFT	0
43983e3700STom Rini #define PRM_VC_VAL_BYPASS_SLAVEADDR_MASK	0x7F
44983e3700STom Rini #define PRM_VC_VAL_BYPASS_REGADDR_SHIFT		8
45983e3700STom Rini #define PRM_VC_VAL_BYPASS_REGADDR_MASK		0xFF
46983e3700STom Rini #define PRM_VC_VAL_BYPASS_DATA_SHIFT		16
47983e3700STom Rini #define PRM_VC_VAL_BYPASS_DATA_MASK		0xFF
48983e3700STom Rini 
49983e3700STom Rini /**
50983e3700STom Rini  * omap_vc_init() - Initialization for Voltage controller
51983e3700STom Rini  * @speed_khz: I2C buspeed in KHz
52983e3700STom Rini  */
omap_vc_init(u16 speed_khz)53983e3700STom Rini static void omap_vc_init(u16 speed_khz)
54983e3700STom Rini {
55983e3700STom Rini 	u32 val;
56983e3700STom Rini 	u32 sys_clk_khz, cycles_hi, cycles_low;
57983e3700STom Rini 
58983e3700STom Rini 	sys_clk_khz = get_sys_clk_freq() / 1000;
59983e3700STom Rini 
60983e3700STom Rini 	if (speed_khz > 400) {
61983e3700STom Rini 		puts("higher speed requested - throttle to 400Khz\n");
62983e3700STom Rini 		speed_khz = 400;
63983e3700STom Rini 	}
64983e3700STom Rini 
65983e3700STom Rini 	/*
66983e3700STom Rini 	 * Setup the dedicated I2C controller for Voltage Control
67983e3700STom Rini 	 * I2C clk - high period 40% low period 60%
68983e3700STom Rini 	 */
69983e3700STom Rini 	speed_khz /= 10;
70983e3700STom Rini 	cycles_hi = sys_clk_khz * 4 / speed_khz;
71983e3700STom Rini 	cycles_low = sys_clk_khz * 6 / speed_khz;
72983e3700STom Rini 	/* values to be set in register - less by 5 & 7 respectively */
73983e3700STom Rini 	cycles_hi -= 5;
74983e3700STom Rini 	cycles_low -= 7;
75983e3700STom Rini 	val = (cycles_hi << PRM_VC_CFG_I2C_CLK_SCLH_SHIFT) |
76983e3700STom Rini 	       (cycles_low << PRM_VC_CFG_I2C_CLK_SCLL_SHIFT);
77983e3700STom Rini 	writel(val, (*prcm)->prm_vc_cfg_i2c_clk);
78983e3700STom Rini 
79*302acbedSTom Rini 	/*
80*302acbedSTom Rini 	 * Master code if there are multiple masters on the I2C_SR bus.
81*302acbedSTom Rini 	 */
82*302acbedSTom Rini 	val = 0x0 << PRM_VC_CFG_I2C_MODE_HSMCODE_SHIFT;
83983e3700STom Rini 	/* No HS mode for now */
84983e3700STom Rini 	val &= ~PRM_VC_CFG_I2C_MODE_HSMODEEN_BIT;
85983e3700STom Rini 	writel(val, (*prcm)->prm_vc_cfg_i2c_mode);
86983e3700STom Rini }
87983e3700STom Rini 
88983e3700STom Rini /**
89983e3700STom Rini  * omap_vc_bypass_send_value() - Send a data using VC Bypass command
90983e3700STom Rini  * @sa:		7 bit I2C slave address of the PMIC
91983e3700STom Rini  * @reg_addr:	I2C register address(8 bit) address in PMIC
92983e3700STom Rini  * @reg_data:	what 8 bit data to write
93983e3700STom Rini  */
omap_vc_bypass_send_value(u8 sa,u8 reg_addr,u8 reg_data)94983e3700STom Rini int omap_vc_bypass_send_value(u8 sa, u8 reg_addr, u8 reg_data)
95983e3700STom Rini {
96983e3700STom Rini 	/*
97983e3700STom Rini 	 * Unfortunately we need to loop here instead of a defined time
98983e3700STom Rini 	 * use arbitary large value
99983e3700STom Rini 	 */
100983e3700STom Rini 	u32 timeout = 0xFFFF;
101983e3700STom Rini 	u32 reg_val;
102983e3700STom Rini 
103983e3700STom Rini 	sa &= PRM_VC_VAL_BYPASS_SLAVEADDR_MASK;
104983e3700STom Rini 	reg_addr &= PRM_VC_VAL_BYPASS_REGADDR_MASK;
105983e3700STom Rini 	reg_data &= PRM_VC_VAL_BYPASS_DATA_MASK;
106983e3700STom Rini 
107983e3700STom Rini 	/* program VC to send data */
108983e3700STom Rini 	reg_val = sa << PRM_VC_VAL_BYPASS_SLAVEADDR_SHIFT |
109983e3700STom Rini 	    reg_addr << PRM_VC_VAL_BYPASS_REGADDR_SHIFT |
110983e3700STom Rini 	    reg_data << PRM_VC_VAL_BYPASS_DATA_SHIFT;
111983e3700STom Rini 	writel(reg_val, (*prcm)->prm_vc_val_bypass);
112983e3700STom Rini 
113983e3700STom Rini 	/* Signal VC to send data */
114983e3700STom Rini 	writel(reg_val | PRM_VC_VAL_BYPASS_VALID_BIT,
115983e3700STom Rini 				(*prcm)->prm_vc_val_bypass);
116983e3700STom Rini 
117983e3700STom Rini 	/* Wait on VC to complete transmission */
118983e3700STom Rini 	do {
119983e3700STom Rini 		reg_val = readl((*prcm)->prm_vc_val_bypass) &
120983e3700STom Rini 				PRM_VC_VAL_BYPASS_VALID_BIT;
121983e3700STom Rini 		if (!reg_val)
122983e3700STom Rini 			break;
123983e3700STom Rini 
124983e3700STom Rini 		sdelay(100);
125983e3700STom Rini 	} while (--timeout);
126983e3700STom Rini 
127983e3700STom Rini 	/* Optional: cleanup PRM_IRQSTATUS_Ax */
128983e3700STom Rini 	/* In case we can do something about it in future.. */
129983e3700STom Rini 	if (!timeout)
130983e3700STom Rini 		return -1;
131983e3700STom Rini 
132983e3700STom Rini 	/* All good.. */
133983e3700STom Rini 	return 0;
134983e3700STom Rini }
135983e3700STom Rini 
sri2c_init(void)136983e3700STom Rini void sri2c_init(void)
137983e3700STom Rini {
138983e3700STom Rini 	static int sri2c = 1;
139983e3700STom Rini 
140983e3700STom Rini 	if (sri2c) {
141983e3700STom Rini 		omap_vc_init(PRM_VC_I2C_CHANNEL_FREQ_KHZ);
142983e3700STom Rini 		sri2c = 0;
143983e3700STom Rini 	}
144983e3700STom Rini 	return;
145983e3700STom Rini }
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