60 	u32 reg_val = 0;  in tegra_dc_dpaux_poll_register()  local
65 		reg_val = tegra_dpaux_readl(dp, reg);  in tegra_dc_dpaux_poll_register()
70 	} while ((reg_val & mask) != exp_val);  in tegra_dc_dpaux_poll_register()
72 	if ((reg_val & mask) == exp_val)  in tegra_dc_dpaux_poll_register()
75 	      reg, reg_val, mask, exp_val);  in tegra_dc_dpaux_poll_register()
98 	u32 reg_val;  in tegra_dc_dpaux_write_chunk()  local
124 	reg_val = tegra_dpaux_readl(dp, DPAUX_DP_AUXCTL);  in tegra_dc_dpaux_write_chunk()
125 	reg_val &= ~DPAUX_DP_AUXCTL_CMD_MASK;  in tegra_dc_dpaux_write_chunk()
126 	reg_val |= cmd;  in tegra_dc_dpaux_write_chunk()
127 	reg_val &= ~DPAUX_DP_AUXCTL_CMDLEN_FIELD;  in tegra_dc_dpaux_write_chunk()
128 	reg_val |= ((*size - 1) << DPAUX_DP_AUXCTL_CMDLEN_SHIFT);  in tegra_dc_dpaux_write_chunk()
135 		reg_val |= DPAUX_DP_AUXCTL_TRANSACTREQ_PENDING;  in tegra_dc_dpaux_write_chunk()
136 		tegra_dpaux_writel(dp, DPAUX_DP_AUXCTL, reg_val);  in tegra_dc_dpaux_write_chunk()
194 	u32 reg_val;  in tegra_dc_dpaux_read_chunk()  local
223 	reg_val = tegra_dpaux_readl(dp, DPAUX_DP_AUXCTL);  in tegra_dc_dpaux_read_chunk()
224 	reg_val &= ~DPAUX_DP_AUXCTL_CMD_MASK;  in tegra_dc_dpaux_read_chunk()
225 	reg_val |= cmd;  in tegra_dc_dpaux_read_chunk()
226 	reg_val &= ~DPAUX_DP_AUXCTL_CMDLEN_FIELD;  in tegra_dc_dpaux_read_chunk()
227 	reg_val |= ((*size - 1) << DPAUX_DP_AUXCTL_CMDLEN_SHIFT);  in tegra_dc_dpaux_read_chunk()
233 		reg_val |= DPAUX_DP_AUXCTL_TRANSACTREQ_PENDING;  in tegra_dc_dpaux_read_chunk()
234 		tegra_dpaux_writel(dp, DPAUX_DP_AUXCTL, reg_val);  in tegra_dc_dpaux_read_chunk()