| /rk3399_rockchip-uboot/board/wandboard/ |
| H A D | spl.c | 190 .refsel = 1, /* Refresh cycles at 32KHz */
233 .refsel = 1, /* Refresh cycles at 32KHz */
252 .refsel = 1, /* Refresh cycles at 32KHz */
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| /rk3399_rockchip-uboot/board/ccv/xpress/ |
| H A D | spl.c | 63 .refsel = 1, /* Refresh cycles at 32KHz */
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| /rk3399_rockchip-uboot/board/bachmann/ot1200/ |
| H A D | ot1200_spl.c | 88 .refsel = 1, /* Refresh cycles at 32KHz */
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| /rk3399_rockchip-uboot/board/compulab/cm_fx6/ |
| H A D | spl.c | 110 .refsel = 1, /* Refresh cycles at 32KHz */
179 .refsel = 1, /* Refresh cycles at 32KHz */
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| /rk3399_rockchip-uboot/board/barco/platinum/ |
| H A D | spl_picon.c | 141 .refsel = 1, /* Refresh cycles at 32KHz */ in spl_dram_init()
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| H A D | spl_titanium.c | 144 .refsel = 1, /* Refresh cycles at 32KHz */ in spl_dram_init()
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| /rk3399_rockchip-uboot/arch/arm/mach-imx/mx6/ |
| H A D | litesom.c | 131 .refsel = 0, /* Refresh cycles at 64KHz */
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| H A D | ddr.c | 1189 mmdc0->mdref = (sysinfo->refsel << 14) | (sysinfo->refr << 11); in mx6_lpddr2_cfg()
1494 mmdc0->mdref = (sysinfo->refsel << 14) | (sysinfo->refr << 11); in mx6_ddr3_cfg()
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| /rk3399_rockchip-uboot/board/liebherr/display5/ |
| H A D | spl.c | 138 .refsel = 1, /* Refresh cycles at 32KHz */ in spl_dram_init()
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| /rk3399_rockchip-uboot/board/udoo/ |
| H A D | udoo_spl.c | 196 .refsel = 1, /* Refresh cycles at 32KHz */
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| /rk3399_rockchip-uboot/board/freescale/mx6ul_14x14_evk/ |
| H A D | mx6ul_14x14_evk.c | 769 .refsel = 0, /* Refresh cycles at 64KHz */
809 .refsel = 0, /* Refresh cycles at 64KHz */
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| /rk3399_rockchip-uboot/board/gateworks/gw_ventana/ |
| H A D | gw_ventana_spl.c | 454 .refsel = 1, /* Refresh cycles at 32KHz */ in spl_dram_init()
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| /rk3399_rockchip-uboot/board/freescale/mx6slevk/ |
| H A D | mx6slevk.c | 461 .refsel = 0, /* Refresh cycles at 64KHz */ in spl_dram_init()
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| /rk3399_rockchip-uboot/board/kosagi/novena/ |
| H A D | novena_spl.c | 523 .refsel = 1, /* Refresh cycles at 32KHz */
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| /rk3399_rockchip-uboot/board/phytec/pcm058/ |
| H A D | pcm058.c | 509 .refsel = 1, /* Refresh cycles at 32KHz */ in spl_dram_init()
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| /rk3399_rockchip-uboot/board/solidrun/mx6cuboxi/ |
| H A D | mx6cuboxi.c | 602 .refsel = 1, /* Refresh cycles at 32KHz */ in spl_dram_init()
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| /rk3399_rockchip-uboot/board/el/el6x/ |
| H A D | el6x.c | 596 .refsel = 1, /* Refresh cycles at 32KHz */ in spl_dram_init()
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| /rk3399_rockchip-uboot/arch/arm/include/asm/arch-mx6/ |
| H A D | mx6-ddr.h | 411 u8 refsel; /* REF_SEL field of register MDREF */ member
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| /rk3399_rockchip-uboot/board/freescale/mx6sxsabresd/ |
| H A D | mx6sxsabresd.c | 640 .refsel = 1, /* Refresh cycles at 32KHz */ in spl_dram_init()
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| /rk3399_rockchip-uboot/board/phytec/pfla02/ |
| H A D | pfla02.c | 651 .refsel = 1, /* Refresh cycles at 32KHz */ in board_init_f()
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| /rk3399_rockchip-uboot/board/congatec/cgtqmx6eval/ |
| H A D | cgtqmx6eval.c | 1031 .refsel = 1, /* Refresh cycles at 32KHz */ in spl_dram_init()
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