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Searched refs:r4 (Results 1 – 25 of 92) sorted by relevance

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/rk3399_rockchip-uboot/arch/sh/lib/
H A Dashiftrt.S57 rotcl r4
59 subc r4,r4
61 shar r4
63 shar r4
65 shar r4
67 shar r4
69 shar r4
71 shar r4
73 shlr16 r4
74 shlr8 r4
[all …]
H A Dudivsi3_i4i-Os.S28 mov.l r4,@-r15
31 swap.w r4,r0
32 shlr16 r4
38 div1 r5,r4
40 div1 r5,r4
41 div1 r5,r4
43 div1 r5,r4
44 xtrct r4,r0
45 xtrct r0,r4
47 swap.w r4,r4
[all …]
H A Dudivsi3.S16 div1 r5,r4
18 div1 r5,r4; div1 r5,r4; div1 r5,r4
19 div1 r5,r4; div1 r5,r4; div1 r5,r4; rts; div1 r5,r4
22 div1 r5,r4; rotcl r0
23 div1 r5,r4; rotcl r0
24 div1 r5,r4; rotcl r0
25 rts; div1 r5,r4
33 swap.w r4,r0
34 shlr16 r4
38 div1 r5,r4
[all …]
H A Dmovmem.S36 mov.l r0,@(60,r4)
40 mov.l r0,@(56,r4)
44 mov.l r0,@(52,r4)
45 add #64,r4
54 mov.l r0,@(56,r4)
57 mov.l r0,@(52,r4)
65 mov.l r0,@(60,r4)
71 mov.l r0,@(56,r4)
77 mov.l r0,@(52,r4)
83 mov.l r0,@(48,r4)
[all …]
H A Dudivsi3_i4i.S44 mov r4,r0
54 mov.l r4,@-r15
67 mov.l r4,@-r15
77 dmulu.l r1,r4
80 mov r4,r0
84 addc r4,r0
85 mov.l @r15+,r4
91 neg r4,r0
95 mov.l @r15+,r4
108 mov.l r4,@-r15
[all …]
H A Dstart.S29 mov.l ._reloc_dst, r4
34 mov.l r1, @r4
35 add #4, r4
36 cmp/hs r6, r4
39 mov.l ._bss_start, r4
43 3: mov.l r1, @r4 /* bss clear */
44 add #4, r4
45 cmp/hs r5, r4
53 mov #0, r4
/rk3399_rockchip-uboot/arch/powerpc/cpu/mpc83xx/
H A Dstart.S110 mflr r4
115 mtspr SRR0, r4
121 lfd 1, 0(r4)
128 stfd 1, 0(r4)
165 lis r4, CONFIG_DEFAULT_IMMR@h
177 lwz r6, IMMRBAR(r4)
180 stw r3, IMMRBAR(r4)
210 lis r4, (CONFIG_SYS_MONITOR_BASE)@h
211 ori r4, r4, (CONFIG_SYS_MONITOR_BASE)@l
212 addi r5, r4, in_flash - _start + EXC_OFF_SYS_RESET
[all …]
/rk3399_rockchip-uboot/arch/arm/cpu/armv7/
H A Dsleep.S27 push {r4 - r12, lr}
34 adr r4, __suspend_gd
35 str r9, [r4]
52 pop {r4 - r12, pc}
56 push {r4 - r11}
58 read_midr r4
59 ubfx r5, r4, #4, #12
61 ldr r4, CORTEX_A7_PART_NUM
62 cmp r5, r4
65 ldr r4, CORTEX_A9_PART_NUM
[all …]
/rk3399_rockchip-uboot/arch/powerpc/lib/
H A Dppcstring.S14 addi r4,r4,-1
15 1: lbzu r0,1(r4)
27 addi r4,r4,-1
28 1: lbzu r0,1(r4)
37 addi r4,r4,-1
42 1: lbzu r0,1(r4)
51 addi r4,r4,-1
54 lbzu r0,1(r4)
62 addi r4,r3,-1
63 1: lbzu r0,1(r4)
[all …]
H A Dppccache.S71 subf r4,r3,r4
72 add r4,r4,r5
73 srwi. r4,r4,L1_CACHE_SHIFT
75 mtctr r4
95 subf r4,r3,r4
96 add r4,r4,r5
97 srwi. r4,r4,L1_CACHE_SHIFT
99 mtctr r4
/rk3399_rockchip-uboot/post/lib_powerpc/
H A Dasm.S27 mr r3, r4
28 mr r4, r5
50 mr r3, r4
51 mr r4, r5
70 stwu r4, -4(r1)
74 mr r4, r6
77 lwz r4, 0(r1)
78 stw r3, 0(r4)
91 stwu r4, -4(r1)
97 lwz r4, 0(r1)
[all …]
/rk3399_rockchip-uboot/arch/nds32/include/asm/
H A Dmacro.h26 li $r4, \addr
28 swi $r5, [$r4]
32 li $r4, \addr
34 shi $r5, [$r4]
38 li $r4, \addr
40 sbi $r5, [$r4]
49 li $r4, \addr
50 lwi $r5, [$r4]
53 swi $r5, [$r4]
57 li $r4, \addr
[all …]
/rk3399_rockchip-uboot/arch/arm/cpu/armv7/kona-common/
H A Dreset.S11 ldr r4, =0x80000000
12 and r4, r2, r4
14 orr r4, r4, r3
15 orr r4, r4, #0x1
17 str r4, [r1]
21 ldr r4, =0x80000000
22 and r4, r2, r4
23 str r4, [r1]
/rk3399_rockchip-uboot/arch/powerpc/cpu/mpc85xx/
H A Dstart.S93 li r4,CONFIG_SYS_FSL_ERRATUM_A004510_SVR_REV
94 cmpw r3,r4
98 li r4,CONFIG_SYS_FSL_ERRATUM_A004510_SVR_REV2
99 cmpw r3,r4
112 li r4,0x48
113 rlwimi r3,r4,0,0x1f8
138 and. r4, r3, r2
158 andc r4, r3, r2
161 mtspr SPRN_L2CSR0,r4
255 li r4,CriticalInput@l
[all …]
/rk3399_rockchip-uboot/arch/powerpc/cpu/mpc86xx/
H A Dstart.S88 mfspr r4,DAR
89 stw r4,_DAR(r21)
243 lis r4, PIXIS_BASE@h
244 ori r4, r4, 0x6
246 lbz r3, 0(r4)
254 lbz r3, 0(r4)
258 stb r3, 0(r4)
311 lis r4, CONFIG_SYS_IBAT##n##L@h; \
312 ori r4, r4, CONFIG_SYS_IBAT##n##L@l; \
315 mtspr IBAT##n##L, r4; \
[all …]
H A Dcache.S77 subf r4,r3,r4
78 add r4,r4,r5
79 srwi. r4,r4,LG_CACHE_LINE_SIZE
81 mtctr r4
87 mtctr r4
104 subf r4,r3,r4 /* r4 = offset of stop from start of cache line */
105 add r4,r4,r5 /* r4 += cache_line_size-1 */
106 srwi. r4,r4,LG_CACHE_LINE_SIZE /* r4 = number of cache lines to flush */
108 mtctr r4 /* ctr = r4 */
126 li r4,4096/CACHE_LINE_SIZE /* Number of lines in a page */
[all …]
/rk3399_rockchip-uboot/arch/arm/mach-omap2/omap5/
H A Dsec_entry_cpu1.S39 ldr r4, =omap_smc_sec_cpu1_args
40 ldm r4, {r0,r1,r2,r3} @ Retrieve args
62 ldr r4, =omap_smc_sec_cpu1_args
63 str r0, [r4, #0x10] @ save return value
64 ldr r4, =AUX_CORE_BOOT_0
66 str r5, [r4]
67 ldr r4, =ROM_FXN_STARTUP_BOOTSLAVE
69 bx r4 @ Jump back to ROM
80 push {r4, r5, lr}
81 ldr r4, =omap_smc_sec_cpu1_args
[all …]
/rk3399_rockchip-uboot/arch/nios2/cpu/
H A Dstart.S34 ori r4, r0, %lo(ICACHE_LINE_SIZE)
38 sub r5, r5, r4
63 ori r4, r0, %lo(DCACHE_LINE_SIZE_MIN)
68 add r6, r6, r4
77 nextpc r4
80 sub r4, r4, r5 /* r4 <- cur _start */
81 mov r8, r4
85 beq r4, r5, 3f
90 2: ldwio r7, 0(r4)
91 addi r4, r4, 4
[all …]
/rk3399_rockchip-uboot/board/nokia/rx51/
H A Dlowlevel_init.S51 subhi r4, r0, r1
52 sublo r4, r1, r0
56 addhi r0, r0, r4
57 sublo r0, r0, r4
76 ldr r4, [r0] /* r4 - 4 bytes header of kernel */
78 cmp r4, r5
129 add r4, r0, r6
130 add r4, r4, r7
137 cmp r4, r5 /* higher address (r4 or r5) */
138 movhs r2, r4
[all …]
/rk3399_rockchip-uboot/board/freescale/mx35pdk/
H A Dlowlevel_init.S173 ldr r4, =ESDCTL_PRECHARGE
174 strb r3, [r1, r4]
184 ldr r4, =ESDCTL_DDR2_EMR2
185 strb r3, [r1, r4]
186 ldr r4, =ESDCTL_DDR2_EMR3
187 strb r3, [r1, r4]
188 ldr r4, =ESDCTL_DDR2_EN_DLL
189 strb r3, [r1, r4]
190 ldr r4, =ESDCTL_DDR2_RESET_DLL
191 strb r3, [r1, r4]
[all …]
/rk3399_rockchip-uboot/arch/arm/include/asm/arch-mx6/
H A Dmx6_plugin.S25 push {r0-r4, lr}
48 ldr r4, [r3]
49 cmp r4, #ROM_VERSION_TO10
52 ldr r4, =0x50000000
53 str r4, [r3, #0x5c]
56 ldr r4, =0x08000000
57 str r4, [r3, #0xc0]
66 ldr r4, [r3]
69 cmp r4, r3
74 cmp r4, r3
[all …]
/rk3399_rockchip-uboot/board/armadeus/apf27/
H A Dlowlevel_init.S66 ldr r4, =ESDMISC_SDRAM_RDY
68 ands r1, r1, r4
73 ldr r4, =ACFG_ESDMISC_VAL
74 orr r1, r4, #ESDMISC_MDDR_DL_RST
82 str r4, [r0]
99 ldr r4, =PHYS_SDRAM_1 /* CSD0 base address */
102 1: str r5,[r4] /* run auto-refresh cycle to array 0 */
110 ldr r4, = PHYS_SDRAM_1+ACFG_SDRAM_MODE_REGISTER_VAL
111 strb r2, [r4]
114 ldr r4, =PHYS_SDRAM_1+ACFG_SDRAM_EXT_MODE_REGISTER_VAL
[all …]
/rk3399_rockchip-uboot/arch/nds32/cpu/n1213/ag101/
H A Dlowlevel_init.S112 li $r4, BOARD_ID_FAMILY_MASK
113 and $r3, $r3, $r4
114 li $r4, BOARD_ID_FAMILY_K7
115 xor $r4, $r3, $r4
116 beqz $r4, use_flash_16bit_boot
200 li $r4, CONFIG_FTSDMC021_BASE
202 swi $r5, [$r4 + FTSDMC021_BANK2_BSR]
203 swi $r5, [$r4 + FTSDMC021_BANK3_BSR]
238 li $r4, 0xfff00000 /* r4 = bank6 base */
239 and $r4, $r4, $r8
[all …]
/rk3399_rockchip-uboot/arch/arc/lib/
H A Dmemcmp.S22 ld %r4, [%r0, 0]
28 brne %r4, %r5, .Leven
29 ld.a %r4, [%r0, 8]
36 brne %r4, %r5, .Leven
37 ld %r4, [%r0, 4]
43 xor %r0, %r4, %r5
51 xor %r0, %r4, %r5
58 asl %r2, %r4, %r1
81 lsr %r4, %r4, SHIFT
85 sub.f %r0, %r4, %r5
[all …]
/rk3399_rockchip-uboot/arch/arm/cpu/arm920t/ep93xx/
H A Dlowlevel_init.S47 ldr r4, =(EP93XX_SDRAMCTRL_GLOBALCFG_INIT | \
50 str r4, [r3, #SDRAM_OFF_GLCONFIG]
53 mov r4, #0x3000
55 subs r4, r4, #1
59 ldr r4, =(EP93XX_SDRAMCTRL_GLOBALCFG_INIT | \
61 str r4, [r3, #SDRAM_OFF_GLCONFIG]
66 ldr r4, =0x10
67 str r4, [r3, #SDRAM_OFF_REFRSHTIMR]
70 mov r4, #80
72 subs r4, r4, #1
[all …]

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