1a47a12beSStefan Roese/* 21605cc9eSBecky Bruce * Copyright 2004, 2007, 2011 Freescale Semiconductor. 3a47a12beSStefan Roese * Srikanth Srinivasan <srikanth.srinivaan@freescale.com> 4a47a12beSStefan Roese * 51a459660SWolfgang Denk * SPDX-License-Identifier: GPL-2.0+ 6a47a12beSStefan Roese */ 7a47a12beSStefan Roese 8a47a12beSStefan Roese/* U-Boot - Startup Code for 86xx PowerPC based Embedded Boards 9a47a12beSStefan Roese * 10a47a12beSStefan Roese * 11a47a12beSStefan Roese * The processor starts at 0xfff00100 and the code is executed 12a47a12beSStefan Roese * from flash. The code is organized to be at an other address 13a47a12beSStefan Roese * in memory, but as long we don't jump around before relocating. 14a47a12beSStefan Roese * board_init lies at a quite high address and when the cpu has 15a47a12beSStefan Roese * jumped there, everything is ok. 16a47a12beSStefan Roese */ 1725ddd1fbSWolfgang Denk#include <asm-offsets.h> 18a47a12beSStefan Roese#include <config.h> 19a47a12beSStefan Roese#include <mpc86xx.h> 20a47a12beSStefan Roese#include <version.h> 21a47a12beSStefan Roese 22a47a12beSStefan Roese#include <ppc_asm.tmpl> 23a47a12beSStefan Roese#include <ppc_defs.h> 24a47a12beSStefan Roese 25a47a12beSStefan Roese#include <asm/cache.h> 26a47a12beSStefan Roese#include <asm/mmu.h> 27d98b0523SPeter Tyser#include <asm/u-boot.h> 28a47a12beSStefan Roese 29a47a12beSStefan Roese/* 30a47a12beSStefan Roese * Need MSR_DR | MSR_IR enabled to access I/O (printf) in exceptions 31a47a12beSStefan Roese */ 32a47a12beSStefan Roese 33a47a12beSStefan Roese/* 34a47a12beSStefan Roese * Set up GOT: Global Offset Table 35a47a12beSStefan Roese * 36a47a12beSStefan Roese * Use r12 to access the GOT 37a47a12beSStefan Roese */ 38a47a12beSStefan Roese START_GOT 39a47a12beSStefan Roese GOT_ENTRY(_GOT2_TABLE_) 40a47a12beSStefan Roese GOT_ENTRY(_FIXUP_TABLE_) 41a47a12beSStefan Roese 42a47a12beSStefan Roese GOT_ENTRY(_start) 43a47a12beSStefan Roese GOT_ENTRY(_start_of_vectors) 44a47a12beSStefan Roese GOT_ENTRY(_end_of_vectors) 45a47a12beSStefan Roese GOT_ENTRY(transfer_to_handler) 46a47a12beSStefan Roese 47a47a12beSStefan Roese GOT_ENTRY(__init_end) 483929fb0aSSimon Glass GOT_ENTRY(__bss_end) 49a47a12beSStefan Roese GOT_ENTRY(__bss_start) 50a47a12beSStefan Roese END_GOT 51a47a12beSStefan Roese 52a47a12beSStefan Roese/* 53a47a12beSStefan Roese * r3 - 1st arg to board_init(): IMMP pointer 54a47a12beSStefan Roese * r4 - 2nd arg to board_init(): boot flag 55a47a12beSStefan Roese */ 56a47a12beSStefan Roese .text 57a47a12beSStefan Roese .long 0x27051956 /* U-Boot Magic Number */ 58a47a12beSStefan Roese .globl version_string 59a47a12beSStefan Roeseversion_string: 6009c2e90cSAndreas Bießmann .ascii U_BOOT_VERSION_STRING, "\0" 61a47a12beSStefan Roese 62a47a12beSStefan Roese . = EXC_OFF_SYS_RESET 63a47a12beSStefan Roese .globl _start 64a47a12beSStefan Roese_start: 65a47a12beSStefan Roese b boot_cold 66a47a12beSStefan Roese 67a47a12beSStefan Roese /* the boot code is located below the exception table */ 68a47a12beSStefan Roese 69a47a12beSStefan Roese .globl _start_of_vectors 70a47a12beSStefan Roese_start_of_vectors: 71a47a12beSStefan Roese 72a47a12beSStefan Roese/* Machine check */ 73a47a12beSStefan Roese STD_EXCEPTION(0x200, MachineCheck, MachineCheckException) 74a47a12beSStefan Roese 75a47a12beSStefan Roese/* Data Storage exception. */ 76a47a12beSStefan Roese STD_EXCEPTION(0x300, DataStorage, UnknownException) 77a47a12beSStefan Roese 78a47a12beSStefan Roese/* Instruction Storage exception. */ 79a47a12beSStefan Roese STD_EXCEPTION(0x400, InstStorage, UnknownException) 80a47a12beSStefan Roese 81a47a12beSStefan Roese/* External Interrupt exception. */ 82a47a12beSStefan Roese STD_EXCEPTION(0x500, ExtInterrupt, external_interrupt) 83a47a12beSStefan Roese 84a47a12beSStefan Roese/* Alignment exception. */ 85a47a12beSStefan Roese . = 0x600 86a47a12beSStefan RoeseAlignment: 87a47a12beSStefan Roese EXCEPTION_PROLOG(SRR0, SRR1) 88a47a12beSStefan Roese mfspr r4,DAR 89a47a12beSStefan Roese stw r4,_DAR(r21) 90a47a12beSStefan Roese mfspr r5,DSISR 91a47a12beSStefan Roese stw r5,_DSISR(r21) 92a47a12beSStefan Roese addi r3,r1,STACK_FRAME_OVERHEAD 93a47a12beSStefan Roese EXC_XFER_TEMPLATE(Alignment, AlignmentException, MSR_KERNEL, COPY_EE) 94a47a12beSStefan Roese 95a47a12beSStefan Roese/* Program check exception */ 96a47a12beSStefan Roese . = 0x700 97a47a12beSStefan RoeseProgramCheck: 98a47a12beSStefan Roese EXCEPTION_PROLOG(SRR0, SRR1) 99a47a12beSStefan Roese addi r3,r1,STACK_FRAME_OVERHEAD 100a47a12beSStefan Roese EXC_XFER_TEMPLATE(ProgramCheck, ProgramCheckException, 101a47a12beSStefan Roese MSR_KERNEL, COPY_EE) 102a47a12beSStefan Roese 103a47a12beSStefan Roese STD_EXCEPTION(0x800, FPUnavailable, UnknownException) 104a47a12beSStefan Roese 105a47a12beSStefan Roese /* I guess we could implement decrementer, and may have 106a47a12beSStefan Roese * to someday for timekeeping. 107a47a12beSStefan Roese */ 108a47a12beSStefan Roese STD_EXCEPTION(0x900, Decrementer, timer_interrupt) 109a47a12beSStefan Roese STD_EXCEPTION(0xa00, Trap_0a, UnknownException) 110a47a12beSStefan Roese STD_EXCEPTION(0xb00, Trap_0b, UnknownException) 111a47a12beSStefan Roese STD_EXCEPTION(0xc00, SystemCall, UnknownException) 112a47a12beSStefan Roese STD_EXCEPTION(0xd00, SingleStep, UnknownException) 113a47a12beSStefan Roese STD_EXCEPTION(0xe00, Trap_0e, UnknownException) 114a47a12beSStefan Roese STD_EXCEPTION(0xf00, Trap_0f, UnknownException) 115a47a12beSStefan Roese STD_EXCEPTION(0x1000, SoftEmu, SoftEmuException) 116a47a12beSStefan Roese STD_EXCEPTION(0x1100, InstructionTLBMiss, UnknownException) 117a47a12beSStefan Roese STD_EXCEPTION(0x1200, DataTLBMiss, UnknownException) 118a47a12beSStefan Roese STD_EXCEPTION(0x1300, InstructionTLBError, UnknownException) 119a47a12beSStefan Roese STD_EXCEPTION(0x1400, DataTLBError, UnknownException) 120a47a12beSStefan Roese STD_EXCEPTION(0x1500, Reserved5, UnknownException) 121a47a12beSStefan Roese STD_EXCEPTION(0x1600, Reserved6, UnknownException) 122a47a12beSStefan Roese STD_EXCEPTION(0x1700, Reserved7, UnknownException) 123a47a12beSStefan Roese STD_EXCEPTION(0x1800, Reserved8, UnknownException) 124a47a12beSStefan Roese STD_EXCEPTION(0x1900, Reserved9, UnknownException) 125a47a12beSStefan Roese STD_EXCEPTION(0x1a00, ReservedA, UnknownException) 126a47a12beSStefan Roese STD_EXCEPTION(0x1b00, ReservedB, UnknownException) 127a47a12beSStefan Roese STD_EXCEPTION(0x1c00, DataBreakpoint, UnknownException) 128a47a12beSStefan Roese STD_EXCEPTION(0x1d00, InstructionBreakpoint, UnknownException) 129a47a12beSStefan Roese STD_EXCEPTION(0x1e00, PeripheralBreakpoint, UnknownException) 130a47a12beSStefan Roese STD_EXCEPTION(0x1f00, DevPortBreakpoint, UnknownException) 131a47a12beSStefan Roese 132a47a12beSStefan Roese .globl _end_of_vectors 133a47a12beSStefan Roese_end_of_vectors: 134a47a12beSStefan Roese 135a47a12beSStefan Roese . = 0x2000 136a47a12beSStefan Roese 137a47a12beSStefan Roeseboot_cold: 138a47a12beSStefan Roese /* 139a47a12beSStefan Roese * NOTE: Only Cpu 0 will ever come here. Other cores go to an 140a47a12beSStefan Roese * address specified by the BPTR 141a47a12beSStefan Roese */ 142a47a12beSStefan Roese1: 143a47a12beSStefan Roese#ifdef CONFIG_SYS_RAMBOOT 144a47a12beSStefan Roese /* disable everything */ 145a47a12beSStefan Roese li r0, 0 146a47a12beSStefan Roese mtspr HID0, r0 147a47a12beSStefan Roese sync 148a47a12beSStefan Roese mtmsr 0 149a47a12beSStefan Roese#endif 150a47a12beSStefan Roese 151a47a12beSStefan Roese /* Invalidate BATs */ 152a47a12beSStefan Roese bl invalidate_bats 153a47a12beSStefan Roese sync 154a47a12beSStefan Roese /* Invalidate all of TLB before MMU turn on */ 155a47a12beSStefan Roese bl clear_tlbs 156a47a12beSStefan Roese sync 157a47a12beSStefan Roese 158a47a12beSStefan Roese#ifdef CONFIG_SYS_L2 159a47a12beSStefan Roese /* init the L2 cache */ 160a47a12beSStefan Roese lis r3, L2_INIT@h 161a47a12beSStefan Roese ori r3, r3, L2_INIT@l 162a47a12beSStefan Roese mtspr l2cr, r3 163a47a12beSStefan Roese /* invalidate the L2 cache */ 164a47a12beSStefan Roese bl l2cache_invalidate 165a47a12beSStefan Roese sync 166a47a12beSStefan Roese#endif 167a47a12beSStefan Roese 168a47a12beSStefan Roese /* 169a47a12beSStefan Roese * Calculate absolute address in FLASH and jump there 170a47a12beSStefan Roese *------------------------------------------------------*/ 171a47a12beSStefan Roese lis r3, CONFIG_SYS_MONITOR_BASE_EARLY@h 172a47a12beSStefan Roese ori r3, r3, CONFIG_SYS_MONITOR_BASE_EARLY@l 173a47a12beSStefan Roese addi r3, r3, in_flash - _start + EXC_OFF_SYS_RESET 174a47a12beSStefan Roese mtlr r3 175a47a12beSStefan Roese blr 176a47a12beSStefan Roese 177a47a12beSStefan Roesein_flash: 178a47a12beSStefan Roese /* let the C-code set up the rest */ 179a47a12beSStefan Roese /* */ 180a47a12beSStefan Roese /* Be careful to keep code relocatable ! */ 181a47a12beSStefan Roese /*------------------------------------------------------*/ 182a47a12beSStefan Roese /* perform low-level init */ 183a47a12beSStefan Roese 184a47a12beSStefan Roese /* enable extended addressing */ 185a47a12beSStefan Roese bl enable_ext_addr 186a47a12beSStefan Roese 187a47a12beSStefan Roese /* setup the bats */ 188a47a12beSStefan Roese bl early_bats 189a47a12beSStefan Roese 190a47a12beSStefan Roese /* 191a47a12beSStefan Roese * Cache must be enabled here for stack-in-cache trick. 192a47a12beSStefan Roese * This means we need to enable the BATS. 193a47a12beSStefan Roese * Cache should be turned on after BATs, since by default 194a47a12beSStefan Roese * everything is write-through. 195a47a12beSStefan Roese */ 196a47a12beSStefan Roese 197a47a12beSStefan Roese /* enable address translation */ 198a47a12beSStefan Roese mfmsr r5 199a47a12beSStefan Roese ori r5, r5, (MSR_IR | MSR_DR) 200a47a12beSStefan Roese lis r3,addr_trans_enabled@h 201a47a12beSStefan Roese ori r3, r3, addr_trans_enabled@l 202a47a12beSStefan Roese mtspr SPRN_SRR0,r3 203a47a12beSStefan Roese mtspr SPRN_SRR1,r5 204a47a12beSStefan Roese rfi 205a47a12beSStefan Roese 206a47a12beSStefan Roeseaddr_trans_enabled: 207a47a12beSStefan Roese /* enable and invalidate the data cache */ 208a47a12beSStefan Roese/* bl l1dcache_enable */ 209a47a12beSStefan Roese bl dcache_enable 210a47a12beSStefan Roese sync 211a47a12beSStefan Roese 212a47a12beSStefan Roese#if 1 213a47a12beSStefan Roese bl icache_enable 214a47a12beSStefan Roese#endif 215a47a12beSStefan Roese 216a47a12beSStefan Roese#ifdef CONFIG_SYS_INIT_RAM_LOCK 217a47a12beSStefan Roese bl lock_ram_in_cache 218a47a12beSStefan Roese sync 219a47a12beSStefan Roese#endif 220a47a12beSStefan Roese 221a47a12beSStefan Roese#if (CONFIG_SYS_CCSRBAR_DEFAULT != CONFIG_SYS_CCSRBAR) 222a47a12beSStefan Roese bl setup_ccsrbar 223a47a12beSStefan Roese#endif 224a47a12beSStefan Roese 225a47a12beSStefan Roese /* set up the stack pointer in our newly created 226a47a12beSStefan Roese * cache-ram (r1) */ 227a47a12beSStefan Roese lis r1, (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_GBL_DATA_OFFSET)@h 228a47a12beSStefan Roese ori r1, r1, (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_GBL_DATA_OFFSET)@l 229a47a12beSStefan Roese 230a47a12beSStefan Roese li r0, 0 /* Make room for stack frame header and */ 231a47a12beSStefan Roese stwu r0, -4(r1) /* clear final stack frame so that */ 232a47a12beSStefan Roese stwu r0, -4(r1) /* stack backtraces terminate cleanly */ 233a47a12beSStefan Roese 234a47a12beSStefan Roese GET_GOT /* initialize GOT access */ 2358c4734e9SWolfgang Denk 236a47a12beSStefan Roese /* run low-level CPU init code (from Flash) */ 237a47a12beSStefan Roese bl cpu_init_f 238a47a12beSStefan Roese sync 239a47a12beSStefan Roese 240a47a12beSStefan Roese#ifdef RUN_DIAG 241a47a12beSStefan Roese 242a47a12beSStefan Roese /* Load PX_AUX register address in r4 */ 243a47a12beSStefan Roese lis r4, PIXIS_BASE@h 244a47a12beSStefan Roese ori r4, r4, 0x6 245a47a12beSStefan Roese /* Load contents of PX_AUX in r3 bits 24 to 31*/ 246a47a12beSStefan Roese lbz r3, 0(r4) 247a47a12beSStefan Roese 248a47a12beSStefan Roese /* Mask and obtain the bit in r3 */ 249a47a12beSStefan Roese rlwinm. r3, r3, 0, 24, 24 250a47a12beSStefan Roese /* If not zero, jump and continue with u-boot */ 251a47a12beSStefan Roese bne diag_done 252a47a12beSStefan Roese 253a47a12beSStefan Roese /* Load back contents of PX_AUX in r3 bits 24 to 31 */ 254a47a12beSStefan Roese lbz r3, 0(r4) 255a47a12beSStefan Roese /* Set the MSB of the register value */ 256a47a12beSStefan Roese ori r3, r3, 0x80 257a47a12beSStefan Roese /* Write value in r3 back to PX_AUX */ 258a47a12beSStefan Roese stb r3, 0(r4) 259a47a12beSStefan Roese 260a47a12beSStefan Roese /* Get the address to jump to in r3*/ 261a47a12beSStefan Roese lis r3, CONFIG_SYS_DIAG_ADDR@h 262a47a12beSStefan Roese ori r3, r3, CONFIG_SYS_DIAG_ADDR@l 263a47a12beSStefan Roese 264a47a12beSStefan Roese /* Load the LR with the branch address */ 265a47a12beSStefan Roese mtlr r3 266a47a12beSStefan Roese 267a47a12beSStefan Roese /* Branch to diagnostic */ 268a47a12beSStefan Roese blr 269a47a12beSStefan Roese 270a47a12beSStefan Roesediag_done: 271a47a12beSStefan Roese#endif 272a47a12beSStefan Roese 273a47a12beSStefan Roese/* bl l2cache_enable */ 274a47a12beSStefan Roese 275a47a12beSStefan Roese /* run 1st part of board init code (from Flash) */ 276*8bae330fSYork Sun li r3, 0 /* clear boot_flag for calling board_init_f */ 277a47a12beSStefan Roese bl board_init_f 278a47a12beSStefan Roese sync 279a47a12beSStefan Roese 28052ebd9c1SPeter Tyser /* NOTREACHED - board_init_f() does not return */ 281a47a12beSStefan Roese 282a47a12beSStefan Roese .globl invalidate_bats 283a47a12beSStefan Roeseinvalidate_bats: 284a47a12beSStefan Roese 285a47a12beSStefan Roese li r0, 0 286a47a12beSStefan Roese /* invalidate BATs */ 287a47a12beSStefan Roese mtspr IBAT0U, r0 288a47a12beSStefan Roese mtspr IBAT1U, r0 289a47a12beSStefan Roese mtspr IBAT2U, r0 290a47a12beSStefan Roese mtspr IBAT3U, r0 291a47a12beSStefan Roese mtspr IBAT4U, r0 292a47a12beSStefan Roese mtspr IBAT5U, r0 293a47a12beSStefan Roese mtspr IBAT6U, r0 294a47a12beSStefan Roese mtspr IBAT7U, r0 295a47a12beSStefan Roese 296a47a12beSStefan Roese isync 297a47a12beSStefan Roese mtspr DBAT0U, r0 298a47a12beSStefan Roese mtspr DBAT1U, r0 299a47a12beSStefan Roese mtspr DBAT2U, r0 300a47a12beSStefan Roese mtspr DBAT3U, r0 301a47a12beSStefan Roese mtspr DBAT4U, r0 302a47a12beSStefan Roese mtspr DBAT5U, r0 303a47a12beSStefan Roese mtspr DBAT6U, r0 304a47a12beSStefan Roese mtspr DBAT7U, r0 305a47a12beSStefan Roese 306a47a12beSStefan Roese isync 307a47a12beSStefan Roese sync 308a47a12beSStefan Roese blr 309a47a12beSStefan Roese 3101605cc9eSBecky Bruce#define CONFIG_BAT_PAIR(n) \ 3111605cc9eSBecky Bruce lis r4, CONFIG_SYS_IBAT##n##L@h; \ 3121605cc9eSBecky Bruce ori r4, r4, CONFIG_SYS_IBAT##n##L@l; \ 3131605cc9eSBecky Bruce lis r3, CONFIG_SYS_IBAT##n##U@h; \ 3141605cc9eSBecky Bruce ori r3, r3, CONFIG_SYS_IBAT##n##U@l; \ 3151605cc9eSBecky Bruce mtspr IBAT##n##L, r4; \ 3161605cc9eSBecky Bruce mtspr IBAT##n##U, r3; \ 3171605cc9eSBecky Bruce lis r4, CONFIG_SYS_DBAT##n##L@h; \ 3181605cc9eSBecky Bruce ori r4, r4, CONFIG_SYS_DBAT##n##L@l; \ 3191605cc9eSBecky Bruce lis r3, CONFIG_SYS_DBAT##n##U@h; \ 3201605cc9eSBecky Bruce ori r3, r3, CONFIG_SYS_DBAT##n##U@l; \ 3211605cc9eSBecky Bruce mtspr DBAT##n##L, r4; \ 3221605cc9eSBecky Bruce mtspr DBAT##n##U, r3; 3231605cc9eSBecky Bruce 3241605cc9eSBecky Bruce/* 3251605cc9eSBecky Bruce * setup_bats: 3261605cc9eSBecky Bruce * 3271605cc9eSBecky Bruce * Set up the final BAT registers now that setup is done. 3281605cc9eSBecky Bruce * 3291605cc9eSBecky Bruce * Assumes that: 3301605cc9eSBecky Bruce * 1) Address translation is enabled upon entry 3311605cc9eSBecky Bruce * 2) The boot rom is still accessible via 1:1 translation 3321605cc9eSBecky Bruce */ 3331605cc9eSBecky Bruce .globl setup_bats 3341605cc9eSBecky Brucesetup_bats: 3351605cc9eSBecky Bruce mflr r5 3361605cc9eSBecky Bruce sync 3371605cc9eSBecky Bruce 3381605cc9eSBecky Bruce /* 3391605cc9eSBecky Bruce * When we disable address translation, we will get 1:1 (VA==PA) 3401605cc9eSBecky Bruce * translation. The only place we know for sure is safe for that is 3411605cc9eSBecky Bruce * the bootrom where we originally started out. Pop back into there. 3421605cc9eSBecky Bruce */ 3431605cc9eSBecky Bruce lis r4, CONFIG_SYS_MONITOR_BASE_EARLY@h 3441605cc9eSBecky Bruce ori r4, r4, CONFIG_SYS_MONITOR_BASE_EARLY@l 3451605cc9eSBecky Bruce addi r4, r4, trans_disabled - _start + EXC_OFF_SYS_RESET 3461605cc9eSBecky Bruce 3471605cc9eSBecky Bruce /* disable address translation */ 3481605cc9eSBecky Bruce mfmsr r3 3491605cc9eSBecky Bruce rlwinm r3, r3, 0, 28, 25 3501605cc9eSBecky Bruce mtspr SRR0, r4 3511605cc9eSBecky Bruce mtspr SRR1, r3 3521605cc9eSBecky Bruce rfi 3531605cc9eSBecky Bruce 3541605cc9eSBecky Brucetrans_disabled: 3551605cc9eSBecky Bruce#if defined(CONFIG_SYS_DBAT0U) && defined(CONFIG_SYS_DBAT0L) \ 3561605cc9eSBecky Bruce && defined(CONFIG_SYS_IBAT0U) && defined(CONFIG_SYS_IBAT0L) 3571605cc9eSBecky Bruce CONFIG_BAT_PAIR(0) 3581605cc9eSBecky Bruce#endif 3591605cc9eSBecky Bruce CONFIG_BAT_PAIR(1) 3601605cc9eSBecky Bruce CONFIG_BAT_PAIR(2) 3611605cc9eSBecky Bruce CONFIG_BAT_PAIR(3) 3621605cc9eSBecky Bruce CONFIG_BAT_PAIR(4) 3631605cc9eSBecky Bruce CONFIG_BAT_PAIR(5) 3641605cc9eSBecky Bruce CONFIG_BAT_PAIR(6) 3651605cc9eSBecky Bruce CONFIG_BAT_PAIR(7) 3661605cc9eSBecky Bruce 3671605cc9eSBecky Bruce sync 3681605cc9eSBecky Bruce isync 3691605cc9eSBecky Bruce 3701605cc9eSBecky Bruce /* Turn translation back on and return */ 3711605cc9eSBecky Bruce mfmsr r3 3721605cc9eSBecky Bruce ori r3, r3, (MSR_IR | MSR_DR) 3731605cc9eSBecky Bruce mtspr SPRN_SRR0,r5 3741605cc9eSBecky Bruce mtspr SPRN_SRR1,r3 3751605cc9eSBecky Bruce rfi 3761605cc9eSBecky Bruce 377a47a12beSStefan Roese/* 378a47a12beSStefan Roese * early_bats: 379a47a12beSStefan Roese * 380a47a12beSStefan Roese * Set up bats needed early on - this is usually the BAT for the 381a47a12beSStefan Roese * stack-in-cache, the Flash, and CCSR space 382a47a12beSStefan Roese */ 383a47a12beSStefan Roese .globl early_bats 384a47a12beSStefan Roeseearly_bats: 385a47a12beSStefan Roese /* IBAT 3 */ 386a47a12beSStefan Roese lis r4, CONFIG_SYS_IBAT3L@h 387a47a12beSStefan Roese ori r4, r4, CONFIG_SYS_IBAT3L@l 388a47a12beSStefan Roese lis r3, CONFIG_SYS_IBAT3U@h 389a47a12beSStefan Roese ori r3, r3, CONFIG_SYS_IBAT3U@l 390a47a12beSStefan Roese mtspr IBAT3L, r4 391a47a12beSStefan Roese mtspr IBAT3U, r3 392a47a12beSStefan Roese isync 393a47a12beSStefan Roese 394a47a12beSStefan Roese /* DBAT 3 */ 395a47a12beSStefan Roese lis r4, CONFIG_SYS_DBAT3L@h 396a47a12beSStefan Roese ori r4, r4, CONFIG_SYS_DBAT3L@l 397a47a12beSStefan Roese lis r3, CONFIG_SYS_DBAT3U@h 398a47a12beSStefan Roese ori r3, r3, CONFIG_SYS_DBAT3U@l 399a47a12beSStefan Roese mtspr DBAT3L, r4 400a47a12beSStefan Roese mtspr DBAT3U, r3 401a47a12beSStefan Roese isync 402a47a12beSStefan Roese 403a47a12beSStefan Roese /* IBAT 5 */ 404a47a12beSStefan Roese lis r4, CONFIG_SYS_IBAT5L@h 405a47a12beSStefan Roese ori r4, r4, CONFIG_SYS_IBAT5L@l 406a47a12beSStefan Roese lis r3, CONFIG_SYS_IBAT5U@h 407a47a12beSStefan Roese ori r3, r3, CONFIG_SYS_IBAT5U@l 408a47a12beSStefan Roese mtspr IBAT5L, r4 409a47a12beSStefan Roese mtspr IBAT5U, r3 410a47a12beSStefan Roese isync 411a47a12beSStefan Roese 412a47a12beSStefan Roese /* DBAT 5 */ 413a47a12beSStefan Roese lis r4, CONFIG_SYS_DBAT5L@h 414a47a12beSStefan Roese ori r4, r4, CONFIG_SYS_DBAT5L@l 415a47a12beSStefan Roese lis r3, CONFIG_SYS_DBAT5U@h 416a47a12beSStefan Roese ori r3, r3, CONFIG_SYS_DBAT5U@l 417a47a12beSStefan Roese mtspr DBAT5L, r4 418a47a12beSStefan Roese mtspr DBAT5U, r3 419a47a12beSStefan Roese isync 420a47a12beSStefan Roese 421a47a12beSStefan Roese /* IBAT 6 */ 422a47a12beSStefan Roese lis r4, CONFIG_SYS_IBAT6L_EARLY@h 423a47a12beSStefan Roese ori r4, r4, CONFIG_SYS_IBAT6L_EARLY@l 424a47a12beSStefan Roese lis r3, CONFIG_SYS_IBAT6U_EARLY@h 425a47a12beSStefan Roese ori r3, r3, CONFIG_SYS_IBAT6U_EARLY@l 426a47a12beSStefan Roese mtspr IBAT6L, r4 427a47a12beSStefan Roese mtspr IBAT6U, r3 428a47a12beSStefan Roese isync 429a47a12beSStefan Roese 430a47a12beSStefan Roese /* DBAT 6 */ 431a47a12beSStefan Roese lis r4, CONFIG_SYS_DBAT6L_EARLY@h 432a47a12beSStefan Roese ori r4, r4, CONFIG_SYS_DBAT6L_EARLY@l 433a47a12beSStefan Roese lis r3, CONFIG_SYS_DBAT6U_EARLY@h 434a47a12beSStefan Roese ori r3, r3, CONFIG_SYS_DBAT6U_EARLY@l 435a47a12beSStefan Roese mtspr DBAT6L, r4 436a47a12beSStefan Roese mtspr DBAT6U, r3 437a47a12beSStefan Roese isync 438a47a12beSStefan Roese 439a47a12beSStefan Roese#if(CONFIG_SYS_CCSRBAR_DEFAULT != CONFIG_SYS_CCSRBAR) 440a47a12beSStefan Roese /* IBAT 7 */ 441a47a12beSStefan Roese lis r4, CONFIG_SYS_CCSR_DEFAULT_IBATL@h 442a47a12beSStefan Roese ori r4, r4, CONFIG_SYS_CCSR_DEFAULT_IBATL@l 443a47a12beSStefan Roese lis r3, CONFIG_SYS_CCSR_DEFAULT_IBATU@h 444a47a12beSStefan Roese ori r3, r3, CONFIG_SYS_CCSR_DEFAULT_IBATU@l 445a47a12beSStefan Roese mtspr IBAT7L, r4 446a47a12beSStefan Roese mtspr IBAT7U, r3 447a47a12beSStefan Roese isync 448a47a12beSStefan Roese 449a47a12beSStefan Roese /* DBAT 7 */ 450a47a12beSStefan Roese lis r4, CONFIG_SYS_CCSR_DEFAULT_DBATL@h 451a47a12beSStefan Roese ori r4, r4, CONFIG_SYS_CCSR_DEFAULT_DBATL@l 452a47a12beSStefan Roese lis r3, CONFIG_SYS_CCSR_DEFAULT_DBATU@h 453a47a12beSStefan Roese ori r3, r3, CONFIG_SYS_CCSR_DEFAULT_DBATU@l 454a47a12beSStefan Roese mtspr DBAT7L, r4 455a47a12beSStefan Roese mtspr DBAT7U, r3 456a47a12beSStefan Roese isync 457a47a12beSStefan Roese#endif 458a47a12beSStefan Roese blr 459a47a12beSStefan Roese 460a47a12beSStefan Roese .globl clear_tlbs 461a47a12beSStefan Roeseclear_tlbs: 462a47a12beSStefan Roese addis r3, 0, 0x0000 463a47a12beSStefan Roese addis r5, 0, 0x4 464a47a12beSStefan Roese isync 465a47a12beSStefan Roesetlblp: 466a47a12beSStefan Roese tlbie r3 467a47a12beSStefan Roese sync 468a47a12beSStefan Roese addi r3, r3, 0x1000 469a47a12beSStefan Roese cmp 0, 0, r3, r5 470a47a12beSStefan Roese blt tlblp 471a47a12beSStefan Roese blr 472a47a12beSStefan Roese 473a47a12beSStefan Roese .globl disable_addr_trans 474a47a12beSStefan Roesedisable_addr_trans: 475a47a12beSStefan Roese /* disable address translation */ 476a47a12beSStefan Roese mflr r4 477a47a12beSStefan Roese mfmsr r3 478a47a12beSStefan Roese andi. r0, r3, (MSR_IR | MSR_DR) 479a47a12beSStefan Roese beqlr 480a47a12beSStefan Roese andc r3, r3, r0 481a47a12beSStefan Roese mtspr SRR0, r4 482a47a12beSStefan Roese mtspr SRR1, r3 483a47a12beSStefan Roese rfi 484a47a12beSStefan Roese 485a47a12beSStefan Roese/* 486a47a12beSStefan Roese * This code finishes saving the registers to the exception frame 487a47a12beSStefan Roese * and jumps to the appropriate handler for the exception. 488a47a12beSStefan Roese * Register r21 is pointer into trap frame, r1 has new stack pointer. 489a47a12beSStefan Roese */ 490a47a12beSStefan Roese .globl transfer_to_handler 491a47a12beSStefan Roesetransfer_to_handler: 492a47a12beSStefan Roese stw r22,_NIP(r21) 493a47a12beSStefan Roese lis r22,MSR_POW@h 494a47a12beSStefan Roese andc r23,r23,r22 495a47a12beSStefan Roese stw r23,_MSR(r21) 496a47a12beSStefan Roese SAVE_GPR(7, r21) 497a47a12beSStefan Roese SAVE_4GPRS(8, r21) 498a47a12beSStefan Roese SAVE_8GPRS(12, r21) 499a47a12beSStefan Roese SAVE_8GPRS(24, r21) 500a47a12beSStefan Roese mflr r23 501a47a12beSStefan Roese andi. r24,r23,0x3f00 /* get vector offset */ 502a47a12beSStefan Roese stw r24,TRAP(r21) 503a47a12beSStefan Roese li r22,0 504a47a12beSStefan Roese stw r22,RESULT(r21) 505a47a12beSStefan Roese mtspr SPRG2,r22 /* r1 is now kernel sp */ 506a47a12beSStefan Roese lwz r24,0(r23) /* virtual address of handler */ 507a47a12beSStefan Roese lwz r23,4(r23) /* where to go when done */ 508a47a12beSStefan Roese mtspr SRR0,r24 509a47a12beSStefan Roese mtspr SRR1,r20 510a47a12beSStefan Roese mtlr r23 511a47a12beSStefan Roese SYNC 512a47a12beSStefan Roese rfi /* jump to handler, enable MMU */ 513a47a12beSStefan Roese 514a47a12beSStefan Roeseint_return: 515a47a12beSStefan Roese mfmsr r28 /* Disable interrupts */ 516a47a12beSStefan Roese li r4,0 517a47a12beSStefan Roese ori r4,r4,MSR_EE 518a47a12beSStefan Roese andc r28,r28,r4 519a47a12beSStefan Roese SYNC /* Some chip revs need this... */ 520a47a12beSStefan Roese mtmsr r28 521a47a12beSStefan Roese SYNC 522a47a12beSStefan Roese lwz r2,_CTR(r1) 523a47a12beSStefan Roese lwz r0,_LINK(r1) 524a47a12beSStefan Roese mtctr r2 525a47a12beSStefan Roese mtlr r0 526a47a12beSStefan Roese lwz r2,_XER(r1) 527a47a12beSStefan Roese lwz r0,_CCR(r1) 528a47a12beSStefan Roese mtspr XER,r2 529a47a12beSStefan Roese mtcrf 0xFF,r0 530a47a12beSStefan Roese REST_10GPRS(3, r1) 531a47a12beSStefan Roese REST_10GPRS(13, r1) 532a47a12beSStefan Roese REST_8GPRS(23, r1) 533a47a12beSStefan Roese REST_GPR(31, r1) 534a47a12beSStefan Roese lwz r2,_NIP(r1) /* Restore environment */ 535a47a12beSStefan Roese lwz r0,_MSR(r1) 536a47a12beSStefan Roese mtspr SRR0,r2 537a47a12beSStefan Roese mtspr SRR1,r0 538a47a12beSStefan Roese lwz r0,GPR0(r1) 539a47a12beSStefan Roese lwz r2,GPR2(r1) 540a47a12beSStefan Roese lwz r1,GPR1(r1) 541a47a12beSStefan Roese SYNC 542a47a12beSStefan Roese rfi 543a47a12beSStefan Roese 544a47a12beSStefan Roese .globl dc_read 545a47a12beSStefan Roesedc_read: 546a47a12beSStefan Roese blr 547a47a12beSStefan Roese 548a47a12beSStefan Roese 549a47a12beSStefan Roese/* 550a47a12beSStefan Roese * Function: in8 551a47a12beSStefan Roese * Description: Input 8 bits 552a47a12beSStefan Roese */ 553a47a12beSStefan Roese .globl in8 554a47a12beSStefan Roesein8: 555a47a12beSStefan Roese lbz r3,0x0000(r3) 556a47a12beSStefan Roese blr 557a47a12beSStefan Roese 558a47a12beSStefan Roese/* 559a47a12beSStefan Roese * Function: out8 560a47a12beSStefan Roese * Description: Output 8 bits 561a47a12beSStefan Roese */ 562a47a12beSStefan Roese .globl out8 563a47a12beSStefan Roeseout8: 564a47a12beSStefan Roese stb r4,0x0000(r3) 565a47a12beSStefan Roese blr 566a47a12beSStefan Roese 567a47a12beSStefan Roese/* 568a47a12beSStefan Roese * Function: out16 569a47a12beSStefan Roese * Description: Output 16 bits 570a47a12beSStefan Roese */ 571a47a12beSStefan Roese .globl out16 572a47a12beSStefan Roeseout16: 573a47a12beSStefan Roese sth r4,0x0000(r3) 574a47a12beSStefan Roese blr 575a47a12beSStefan Roese 576a47a12beSStefan Roese/* 577a47a12beSStefan Roese * Function: out16r 578a47a12beSStefan Roese * Description: Byte reverse and output 16 bits 579a47a12beSStefan Roese */ 580a47a12beSStefan Roese .globl out16r 581a47a12beSStefan Roeseout16r: 582a47a12beSStefan Roese sthbrx r4,r0,r3 583a47a12beSStefan Roese blr 584a47a12beSStefan Roese 585a47a12beSStefan Roese/* 586a47a12beSStefan Roese * Function: out32 587a47a12beSStefan Roese * Description: Output 32 bits 588a47a12beSStefan Roese */ 589a47a12beSStefan Roese .globl out32 590a47a12beSStefan Roeseout32: 591a47a12beSStefan Roese stw r4,0x0000(r3) 592a47a12beSStefan Roese blr 593a47a12beSStefan Roese 594a47a12beSStefan Roese/* 595a47a12beSStefan Roese * Function: out32r 596a47a12beSStefan Roese * Description: Byte reverse and output 32 bits 597a47a12beSStefan Roese */ 598a47a12beSStefan Roese .globl out32r 599a47a12beSStefan Roeseout32r: 600a47a12beSStefan Roese stwbrx r4,r0,r3 601a47a12beSStefan Roese blr 602a47a12beSStefan Roese 603a47a12beSStefan Roese/* 604a47a12beSStefan Roese * Function: in16 605a47a12beSStefan Roese * Description: Input 16 bits 606a47a12beSStefan Roese */ 607a47a12beSStefan Roese .globl in16 608a47a12beSStefan Roesein16: 609a47a12beSStefan Roese lhz r3,0x0000(r3) 610a47a12beSStefan Roese blr 611a47a12beSStefan Roese 612a47a12beSStefan Roese/* 613a47a12beSStefan Roese * Function: in16r 614a47a12beSStefan Roese * Description: Input 16 bits and byte reverse 615a47a12beSStefan Roese */ 616a47a12beSStefan Roese .globl in16r 617a47a12beSStefan Roesein16r: 618a47a12beSStefan Roese lhbrx r3,r0,r3 619a47a12beSStefan Roese blr 620a47a12beSStefan Roese 621a47a12beSStefan Roese/* 622a47a12beSStefan Roese * Function: in32 623a47a12beSStefan Roese * Description: Input 32 bits 624a47a12beSStefan Roese */ 625a47a12beSStefan Roese .globl in32 626a47a12beSStefan Roesein32: 627a47a12beSStefan Roese lwz 3,0x0000(3) 628a47a12beSStefan Roese blr 629a47a12beSStefan Roese 630a47a12beSStefan Roese/* 631a47a12beSStefan Roese * Function: in32r 632a47a12beSStefan Roese * Description: Input 32 bits and byte reverse 633a47a12beSStefan Roese */ 634a47a12beSStefan Roese .globl in32r 635a47a12beSStefan Roesein32r: 636a47a12beSStefan Roese lwbrx r3,r0,r3 637a47a12beSStefan Roese blr 638a47a12beSStefan Roese 639a47a12beSStefan Roese/* 640a47a12beSStefan Roese * void relocate_code (addr_sp, gd, addr_moni) 641a47a12beSStefan Roese * 642a47a12beSStefan Roese * This "function" does not return, instead it continues in RAM 643a47a12beSStefan Roese * after relocating the monitor code. 644a47a12beSStefan Roese * 645a47a12beSStefan Roese * r3 = dest 646a47a12beSStefan Roese * r4 = src 647a47a12beSStefan Roese * r5 = length in bytes 648a47a12beSStefan Roese * r6 = cachelinesize 649a47a12beSStefan Roese */ 650a47a12beSStefan Roese .globl relocate_code 651a47a12beSStefan Roeserelocate_code: 652a47a12beSStefan Roese 653a47a12beSStefan Roese mr r1, r3 /* Set new stack pointer */ 654a47a12beSStefan Roese mr r9, r4 /* Save copy of Global Data pointer */ 655a47a12beSStefan Roese mr r10, r5 /* Save copy of Destination Address */ 656a47a12beSStefan Roese 657a47a12beSStefan Roese GET_GOT 658a47a12beSStefan Roese mr r3, r5 /* Destination Address */ 659a47a12beSStefan Roese lis r4, CONFIG_SYS_MONITOR_BASE@h /* Source Address */ 660a47a12beSStefan Roese ori r4, r4, CONFIG_SYS_MONITOR_BASE@l 661a47a12beSStefan Roese lwz r5, GOT(__init_end) 662a47a12beSStefan Roese sub r5, r5, r4 663a47a12beSStefan Roese li r6, CONFIG_SYS_CACHELINE_SIZE /* Cache Line Size */ 664a47a12beSStefan Roese 665a47a12beSStefan Roese /* 666a47a12beSStefan Roese * Fix GOT pointer: 667a47a12beSStefan Roese * 668a47a12beSStefan Roese * New GOT-PTR = (old GOT-PTR - CONFIG_SYS_MONITOR_BASE) + Destination Address 669a47a12beSStefan Roese * 670a47a12beSStefan Roese * Offset: 671a47a12beSStefan Roese */ 672a47a12beSStefan Roese sub r15, r10, r4 673a47a12beSStefan Roese 674a47a12beSStefan Roese /* First our own GOT */ 675a47a12beSStefan Roese add r12, r12, r15 676a47a12beSStefan Roese /* then the one used by the C code */ 677a47a12beSStefan Roese add r30, r30, r15 678a47a12beSStefan Roese 679a47a12beSStefan Roese /* 680a47a12beSStefan Roese * Now relocate code 681a47a12beSStefan Roese */ 682a47a12beSStefan Roese cmplw cr1,r3,r4 683a47a12beSStefan Roese addi r0,r5,3 684a47a12beSStefan Roese srwi. r0,r0,2 685a47a12beSStefan Roese beq cr1,4f /* In place copy is not necessary */ 686a47a12beSStefan Roese beq 7f /* Protect against 0 count */ 687a47a12beSStefan Roese mtctr r0 688a47a12beSStefan Roese bge cr1,2f 689a47a12beSStefan Roese 690a47a12beSStefan Roese la r8,-4(r4) 691a47a12beSStefan Roese la r7,-4(r3) 692a47a12beSStefan Roese1: lwzu r0,4(r8) 693a47a12beSStefan Roese stwu r0,4(r7) 694a47a12beSStefan Roese bdnz 1b 695a47a12beSStefan Roese b 4f 696a47a12beSStefan Roese 697a47a12beSStefan Roese2: slwi r0,r0,2 698a47a12beSStefan Roese add r8,r4,r0 699a47a12beSStefan Roese add r7,r3,r0 700a47a12beSStefan Roese3: lwzu r0,-4(r8) 701a47a12beSStefan Roese stwu r0,-4(r7) 702a47a12beSStefan Roese bdnz 3b 703a47a12beSStefan Roese/* 704a47a12beSStefan Roese * Now flush the cache: note that we must start from a cache aligned 705a47a12beSStefan Roese * address. Otherwise we might miss one cache line. 706a47a12beSStefan Roese */ 707a47a12beSStefan Roese4: cmpwi r6,0 708a47a12beSStefan Roese add r5,r3,r5 709a47a12beSStefan Roese beq 7f /* Always flush prefetch queue in any case */ 710a47a12beSStefan Roese subi r0,r6,1 711a47a12beSStefan Roese andc r3,r3,r0 712a47a12beSStefan Roese mr r4,r3 713a47a12beSStefan Roese5: dcbst 0,r4 714a47a12beSStefan Roese add r4,r4,r6 715a47a12beSStefan Roese cmplw r4,r5 716a47a12beSStefan Roese blt 5b 717a47a12beSStefan Roese sync /* Wait for all dcbst to complete on bus */ 718a47a12beSStefan Roese mr r4,r3 719a47a12beSStefan Roese6: icbi 0,r4 720a47a12beSStefan Roese add r4,r4,r6 721a47a12beSStefan Roese cmplw r4,r5 722a47a12beSStefan Roese blt 6b 723a47a12beSStefan Roese7: sync /* Wait for all icbi to complete on bus */ 724a47a12beSStefan Roese isync 725a47a12beSStefan Roese 726a47a12beSStefan Roese/* 727a47a12beSStefan Roese * We are done. Do not return, instead branch to second part of board 728a47a12beSStefan Roese * initialization, now running from RAM. 729a47a12beSStefan Roese */ 730a47a12beSStefan Roese addi r0, r10, in_ram - _start + EXC_OFF_SYS_RESET 731a47a12beSStefan Roese mtlr r0 732a47a12beSStefan Roese blr 733a47a12beSStefan Roese 734a47a12beSStefan Roesein_ram: 735a47a12beSStefan Roese /* 736a47a12beSStefan Roese * Relocation Function, r12 point to got2+0x8000 737a47a12beSStefan Roese * 738a47a12beSStefan Roese * Adjust got2 pointers, no need to check for 0, this code 739a47a12beSStefan Roese * already puts a few entries in the table. 740a47a12beSStefan Roese */ 741a47a12beSStefan Roese li r0,__got2_entries@sectoff@l 742a47a12beSStefan Roese la r3,GOT(_GOT2_TABLE_) 743a47a12beSStefan Roese lwz r11,GOT(_GOT2_TABLE_) 744a47a12beSStefan Roese mtctr r0 745a47a12beSStefan Roese sub r11,r3,r11 746a47a12beSStefan Roese addi r3,r3,-4 747a47a12beSStefan Roese1: lwzu r0,4(r3) 748a47a12beSStefan Roese cmpwi r0,0 749a47a12beSStefan Roese beq- 2f 750a47a12beSStefan Roese add r0,r0,r11 751a47a12beSStefan Roese stw r0,0(r3) 752a47a12beSStefan Roese2: bdnz 1b 753a47a12beSStefan Roese 754a47a12beSStefan Roese /* 755a47a12beSStefan Roese * Now adjust the fixups and the pointers to the fixups 756a47a12beSStefan Roese * in case we need to move ourselves again. 757a47a12beSStefan Roese */ 758a47a12beSStefan Roese li r0,__fixup_entries@sectoff@l 759a47a12beSStefan Roese lwz r3,GOT(_FIXUP_TABLE_) 760a47a12beSStefan Roese cmpwi r0,0 761a47a12beSStefan Roese mtctr r0 762a47a12beSStefan Roese addi r3,r3,-4 763a47a12beSStefan Roese beq 4f 764a47a12beSStefan Roese3: lwzu r4,4(r3) 765a47a12beSStefan Roese lwzux r0,r4,r11 766d1e0b10aSJoakim Tjernlund cmpwi r0,0 767a47a12beSStefan Roese add r0,r0,r11 76834bbf618SJoakim Tjernlund stw r4,0(r3) 769d1e0b10aSJoakim Tjernlund beq- 5f 770a47a12beSStefan Roese stw r0,0(r4) 771d1e0b10aSJoakim Tjernlund5: bdnz 3b 772a47a12beSStefan Roese4: 773a47a12beSStefan Roese/* clear_bss: */ 774a47a12beSStefan Roese /* 775a47a12beSStefan Roese * Now clear BSS segment 776a47a12beSStefan Roese */ 777a47a12beSStefan Roese lwz r3,GOT(__bss_start) 7783929fb0aSSimon Glass lwz r4,GOT(__bss_end) 779a47a12beSStefan Roese 780a47a12beSStefan Roese cmplw 0, r3, r4 781a47a12beSStefan Roese beq 6f 782a47a12beSStefan Roese 783a47a12beSStefan Roese li r0, 0 784a47a12beSStefan Roese5: 785a47a12beSStefan Roese stw r0, 0(r3) 786a47a12beSStefan Roese addi r3, r3, 4 787a47a12beSStefan Roese cmplw 0, r3, r4 788a47a12beSStefan Roese bne 5b 789a47a12beSStefan Roese6: 790a47a12beSStefan Roese mr r3, r9 /* Init Date pointer */ 791a47a12beSStefan Roese mr r4, r10 /* Destination Address */ 792a47a12beSStefan Roese bl board_init_r 793a47a12beSStefan Roese 794a47a12beSStefan Roese /* not reached - end relocate_code */ 795a47a12beSStefan Roese/*-----------------------------------------------------------------------*/ 796a47a12beSStefan Roese 797a47a12beSStefan Roese /* 798a47a12beSStefan Roese * Copy exception vector code to low memory 799a47a12beSStefan Roese * 800a47a12beSStefan Roese * r3: dest_addr 801a47a12beSStefan Roese * r7: source address, r8: end address, r9: target address 802a47a12beSStefan Roese */ 803a47a12beSStefan Roese .globl trap_init 804a47a12beSStefan Roesetrap_init: 805a47a12beSStefan Roese mflr r4 /* save link register */ 806a47a12beSStefan Roese GET_GOT 807a47a12beSStefan Roese lwz r7, GOT(_start) 808a47a12beSStefan Roese lwz r8, GOT(_end_of_vectors) 809a47a12beSStefan Roese 810a47a12beSStefan Roese li r9, 0x100 /* reset vector always at 0x100 */ 811a47a12beSStefan Roese 812a47a12beSStefan Roese cmplw 0, r7, r8 813a47a12beSStefan Roese bgelr /* return if r7>=r8 - just in case */ 814a47a12beSStefan Roese1: 815a47a12beSStefan Roese lwz r0, 0(r7) 816a47a12beSStefan Roese stw r0, 0(r9) 817a47a12beSStefan Roese addi r7, r7, 4 818a47a12beSStefan Roese addi r9, r9, 4 819a47a12beSStefan Roese cmplw 0, r7, r8 820a47a12beSStefan Roese bne 1b 821a47a12beSStefan Roese 822a47a12beSStefan Roese /* 823a47a12beSStefan Roese * relocate `hdlr' and `int_return' entries 824a47a12beSStefan Roese */ 825a47a12beSStefan Roese li r7, .L_MachineCheck - _start + EXC_OFF_SYS_RESET 826a47a12beSStefan Roese li r8, Alignment - _start + EXC_OFF_SYS_RESET 827a47a12beSStefan Roese2: 828a47a12beSStefan Roese bl trap_reloc 829a47a12beSStefan Roese addi r7, r7, 0x100 /* next exception vector */ 830a47a12beSStefan Roese cmplw 0, r7, r8 831a47a12beSStefan Roese blt 2b 832a47a12beSStefan Roese 833a47a12beSStefan Roese li r7, .L_Alignment - _start + EXC_OFF_SYS_RESET 834a47a12beSStefan Roese bl trap_reloc 835a47a12beSStefan Roese 836a47a12beSStefan Roese li r7, .L_ProgramCheck - _start + EXC_OFF_SYS_RESET 837a47a12beSStefan Roese bl trap_reloc 838a47a12beSStefan Roese 839a47a12beSStefan Roese li r7, .L_FPUnavailable - _start + EXC_OFF_SYS_RESET 840a47a12beSStefan Roese li r8, SystemCall - _start + EXC_OFF_SYS_RESET 841a47a12beSStefan Roese3: 842a47a12beSStefan Roese bl trap_reloc 843a47a12beSStefan Roese addi r7, r7, 0x100 /* next exception vector */ 844a47a12beSStefan Roese cmplw 0, r7, r8 845a47a12beSStefan Roese blt 3b 846a47a12beSStefan Roese 847a47a12beSStefan Roese li r7, .L_SingleStep - _start + EXC_OFF_SYS_RESET 848a47a12beSStefan Roese li r8, _end_of_vectors - _start + EXC_OFF_SYS_RESET 849a47a12beSStefan Roese4: 850a47a12beSStefan Roese bl trap_reloc 851a47a12beSStefan Roese addi r7, r7, 0x100 /* next exception vector */ 852a47a12beSStefan Roese cmplw 0, r7, r8 853a47a12beSStefan Roese blt 4b 854a47a12beSStefan Roese 855a47a12beSStefan Roese /* enable execptions from RAM vectors */ 856a47a12beSStefan Roese mfmsr r7 857a47a12beSStefan Roese li r8,MSR_IP 858a47a12beSStefan Roese andc r7,r7,r8 859a47a12beSStefan Roese ori r7,r7,MSR_ME /* Enable Machine Check */ 860a47a12beSStefan Roese mtmsr r7 861a47a12beSStefan Roese 862a47a12beSStefan Roese mtlr r4 /* restore link register */ 863a47a12beSStefan Roese blr 864a47a12beSStefan Roese 865a47a12beSStefan Roese.globl enable_ext_addr 866a47a12beSStefan Roeseenable_ext_addr: 867a47a12beSStefan Roese mfspr r0, HID0 868a47a12beSStefan Roese lis r0, (HID0_HIGH_BAT_EN | HID0_XBSEN | HID0_XAEN)@h 869a47a12beSStefan Roese ori r0, r0, (HID0_HIGH_BAT_EN | HID0_XBSEN | HID0_XAEN)@l 870a47a12beSStefan Roese mtspr HID0, r0 871a47a12beSStefan Roese sync 872a47a12beSStefan Roese isync 873a47a12beSStefan Roese blr 874a47a12beSStefan Roese 875a47a12beSStefan Roese#if (CONFIG_SYS_CCSRBAR_DEFAULT != CONFIG_SYS_CCSRBAR) 876a47a12beSStefan Roese.globl setup_ccsrbar 877a47a12beSStefan Roesesetup_ccsrbar: 878a47a12beSStefan Roese /* Special sequence needed to update CCSRBAR itself */ 879a47a12beSStefan Roese lis r4, CONFIG_SYS_CCSRBAR_DEFAULT@h 880a47a12beSStefan Roese ori r4, r4, CONFIG_SYS_CCSRBAR_DEFAULT@l 881a47a12beSStefan Roese 882a47a12beSStefan Roese lis r5, CONFIG_SYS_CCSRBAR_PHYS_LOW@h 883a47a12beSStefan Roese ori r5, r5, CONFIG_SYS_CCSRBAR_PHYS_LOW@l 884a47a12beSStefan Roese srwi r5,r5,12 885a47a12beSStefan Roese li r6, CONFIG_SYS_CCSRBAR_PHYS_HIGH@l 886a47a12beSStefan Roese rlwimi r5,r6,20,8,11 887a47a12beSStefan Roese stw r5, 0(r4) /* Store physical value of CCSR */ 888a47a12beSStefan Roese isync 889a47a12beSStefan Roese 89014d0a02aSWolfgang Denk lis r5, CONFIG_SYS_TEXT_BASE@h 89114d0a02aSWolfgang Denk ori r5,r5,CONFIG_SYS_TEXT_BASE@l 892a47a12beSStefan Roese lwz r5, 0(r5) 893a47a12beSStefan Roese isync 894a47a12beSStefan Roese 895a47a12beSStefan Roese /* Use VA of CCSR to do read */ 896a47a12beSStefan Roese lis r3, CONFIG_SYS_CCSRBAR@h 897a47a12beSStefan Roese lwz r5, CONFIG_SYS_CCSRBAR@l(r3) 898a47a12beSStefan Roese isync 899a47a12beSStefan Roese 900a47a12beSStefan Roese blr 901a47a12beSStefan Roese#endif 902a47a12beSStefan Roese 903a47a12beSStefan Roese#ifdef CONFIG_SYS_INIT_RAM_LOCK 904a47a12beSStefan Roeselock_ram_in_cache: 905a47a12beSStefan Roese /* Allocate Initial RAM in data cache. 906a47a12beSStefan Roese */ 907a47a12beSStefan Roese lis r3, (CONFIG_SYS_INIT_RAM_ADDR & ~31)@h 908a47a12beSStefan Roese ori r3, r3, (CONFIG_SYS_INIT_RAM_ADDR & ~31)@l 909553f0982SWolfgang Denk li r4, ((CONFIG_SYS_INIT_RAM_SIZE & ~31) + \ 910a47a12beSStefan Roese (CONFIG_SYS_INIT_RAM_ADDR & 31) + 31) / 32 911a47a12beSStefan Roese mtctr r4 912a47a12beSStefan Roese1: 913a47a12beSStefan Roese dcbz r0, r3 914a47a12beSStefan Roese addi r3, r3, 32 915a47a12beSStefan Roese bdnz 1b 916a47a12beSStefan Roese#if 1 917a47a12beSStefan Roese/* Lock the data cache */ 918a47a12beSStefan Roese mfspr r0, HID0 919a47a12beSStefan Roese ori r0, r0, 0x1000 920a47a12beSStefan Roese sync 921a47a12beSStefan Roese mtspr HID0, r0 922a47a12beSStefan Roese sync 923a47a12beSStefan Roese blr 924a47a12beSStefan Roese#endif 925a47a12beSStefan Roese#if 0 926a47a12beSStefan Roese /* Lock the first way of the data cache */ 927a47a12beSStefan Roese mfspr r0, LDSTCR 928a47a12beSStefan Roese ori r0, r0, 0x0080 929a47a12beSStefan Roese#if defined(CONFIG_ALTIVEC) 930a47a12beSStefan Roese dssall 931a47a12beSStefan Roese#endif 932a47a12beSStefan Roese sync 933a47a12beSStefan Roese mtspr LDSTCR, r0 934a47a12beSStefan Roese sync 935a47a12beSStefan Roese isync 936a47a12beSStefan Roese blr 937a47a12beSStefan Roese#endif 938a47a12beSStefan Roese 939a47a12beSStefan Roese.globl unlock_ram_in_cache 940a47a12beSStefan Roeseunlock_ram_in_cache: 941a47a12beSStefan Roese /* invalidate the INIT_RAM section */ 942a47a12beSStefan Roese lis r3, (CONFIG_SYS_INIT_RAM_ADDR & ~31)@h 943a47a12beSStefan Roese ori r3, r3, (CONFIG_SYS_INIT_RAM_ADDR & ~31)@l 944553f0982SWolfgang Denk li r4, ((CONFIG_SYS_INIT_RAM_SIZE & ~31) + \ 945a47a12beSStefan Roese (CONFIG_SYS_INIT_RAM_ADDR & 31) + 31) / 32 946a47a12beSStefan Roese mtctr r4 947a47a12beSStefan Roese1: icbi r0, r3 948a47a12beSStefan Roese addi r3, r3, 32 949a47a12beSStefan Roese bdnz 1b 950a47a12beSStefan Roese sync /* Wait for all icbi to complete on bus */ 951a47a12beSStefan Roese isync 952a47a12beSStefan Roese#if 1 953a47a12beSStefan Roese/* Unlock the data cache and invalidate it */ 954a47a12beSStefan Roese mfspr r0, HID0 955a47a12beSStefan Roese li r3,0x1000 956a47a12beSStefan Roese andc r0,r0,r3 957a47a12beSStefan Roese li r3,0x0400 958a47a12beSStefan Roese or r0,r0,r3 959a47a12beSStefan Roese sync 960a47a12beSStefan Roese mtspr HID0, r0 961a47a12beSStefan Roese sync 962a47a12beSStefan Roese blr 963a47a12beSStefan Roese#endif 964a47a12beSStefan Roese#if 0 965a47a12beSStefan Roese /* Unlock the first way of the data cache */ 966a47a12beSStefan Roese mfspr r0, LDSTCR 967a47a12beSStefan Roese li r3,0x0080 968a47a12beSStefan Roese andc r0,r0,r3 969a47a12beSStefan Roese#ifdef CONFIG_ALTIVEC 970a47a12beSStefan Roese dssall 971a47a12beSStefan Roese#endif 972a47a12beSStefan Roese sync 973a47a12beSStefan Roese mtspr LDSTCR, r0 974a47a12beSStefan Roese sync 975a47a12beSStefan Roese isync 976a47a12beSStefan Roese li r3,0x0400 977a47a12beSStefan Roese or r0,r0,r3 978a47a12beSStefan Roese sync 979a47a12beSStefan Roese mtspr HID0, r0 980a47a12beSStefan Roese sync 981a47a12beSStefan Roese blr 982a47a12beSStefan Roese#endif 983a47a12beSStefan Roese#endif 984