Lines Matching refs:r4
93 li r4,CONFIG_SYS_FSL_ERRATUM_A004510_SVR_REV
94 cmpw r3,r4
98 li r4,CONFIG_SYS_FSL_ERRATUM_A004510_SVR_REV2
99 cmpw r3,r4
112 li r4,0x48
113 rlwimi r3,r4,0,0x1f8
138 and. r4, r3, r2
158 andc r4, r3, r2
161 mtspr SPRN_L2CSR0,r4
255 li r4,CriticalInput@l
256 mtspr IVOR0,r4 /* 0: Critical input */
257 li r4,MachineCheck@l
258 mtspr IVOR1,r4 /* 1: Machine check */
259 li r4,DataStorage@l
260 mtspr IVOR2,r4 /* 2: Data storage */
261 li r4,InstStorage@l
262 mtspr IVOR3,r4 /* 3: Instruction storage */
263 li r4,ExtInterrupt@l
264 mtspr IVOR4,r4 /* 4: External interrupt */
265 li r4,Alignment@l
266 mtspr IVOR5,r4 /* 5: Alignment */
267 li r4,ProgramCheck@l
268 mtspr IVOR6,r4 /* 6: Program check */
269 li r4,FPUnavailable@l
270 mtspr IVOR7,r4 /* 7: floating point unavailable */
271 li r4,SystemCall@l
272 mtspr IVOR8,r4 /* 8: System call */
274 li r4,Decrementer@l
275 mtspr IVOR10,r4 /* 10: Decrementer */
276 li r4,IntervalTimer@l
277 mtspr IVOR11,r4 /* 11: Interval timer */
278 li r4,WatchdogTimer@l
279 mtspr IVOR12,r4 /* 12: Watchdog timer */
280 li r4,DataTLBError@l
281 mtspr IVOR13,r4 /* 13: Data TLB error */
282 li r4,InstructionTLBError@l
283 mtspr IVOR14,r4 /* 14: Instruction TLB error */
284 li r4,DebugBreakpoint@l
285 mtspr IVOR15,r4 /* 15: Debug */
365 lis r4,CONFIG_SYS_LBCR_ADDR@h
366 ori r4,r4,CONFIG_SYS_LBCR_ADDR@l
370 stw r5,0(r4)
374 lis r4,CONFIG_SYS_LBC_ADDR@h
375 ori r4,r4,CONFIG_SYS_LBC_ADDR@l
376 tlbivax 0,r4
449 mfspr r4, SPRN_TLB1CFG
450 rlwinm r4, r4, 0, TLBnCFG_NENTRY_MASK
467 2: cmpw r3, r4
717 li r4, 33 /* stash id */
718 stw r4, 4(r3)
719 lis r4, (L2CSR0_L2FI|L2CSR0_L2LFC)@h
720 ori r4, r4, (L2CSR0_L2FI|L2CSR0_L2LFC)@l
722 stw r4, 0(r3) /* invalidate L2 */
728 and. r1, r0, r4
732 lis r4, (L2CSR0_L2PE)@h
733 ori r4, r4, (L2CSR0_L2PE)@l
735 stw r4, 0(r3) /* enable L2 parity/ECC error checking */
741 and. r1, r0, r4
744 lis r4, (L2CSR0_L2E|L2CSR0_L2PE)@h
745 ori r4, r4, (L2CSR0_L2REP_MODE)@l
747 stw r4, 0(r3) /* enable L2 */
753 and. r1, r0, r4
833 lis r4, CONFIG_SYS_CCSRBAR_PHYS_HIGH@h
834 ori r4, r4, CONFIG_SYS_CCSRBAR_PHYS_HIGH@l
839 mtspr MAS7, r4
869 li r4, 0
874 mtspr MAS7, r4
883 addis r4, r7, CTBENR@ha
884 stw r3, CTBENR@l(r4)
885 lwz r3, CTBENR@l(r4)
891 lis r4, \value@h
893 ori r4, r4, \value@l
899 lis r4, \value@h
901 ori r4, r4, \value@l
922 mfspr r4, MAS2
923 rlwimi r4, r15, 0, MAS2_I
924 rlwimi r4, r15, 0, MAS2_G
925 mtspr MAS2, r4
939 mfspr r4,SPRN_L1CSR1
940 and. r4,r4,r3
950 mfspr r4,SPRN_L1CSR1
951 and. r4,r4,r3
1024 stw r4, 0(r3)
1196 lis r4,(CONFIG_SYS_INIT_RAM_ADDR)@h
1197 ori r4,r4,(CONFIG_SYS_INIT_RAM_SIZE)@l
1201 1: subi r4,r4,4
1202 stw r0,0(r4)
1203 cmplw r4,r3
1207 lis r4,(CONFIG_SYS_INIT_RAM_ADDR)@h
1208 ori r4,r4,(CONFIG_SYS_GBL_DATA_OFFSET)@l
1211 stw r3,GD_MALLOC_BASE(r4)
1260 mfspr r4,DAR
1261 stw r4,_DAR(r21)
1317 li r4,0
1318 ori r4,r4,MSR_EE
1319 andc r28,r28,r4
1375 mfspr r4,L1CSR1
1376 ori r4,r4,(L1CSR1_CPE | L1CSR1_ICE)@l
1377 oris r4,r4,(L1CSR1_CPE | L1CSR1_ICE)@h
1378 mtspr L1CSR1,r4
1416 lis r4,0
1417 ori r4,r4,L1CSR0_DCE
1418 andc r3,r3,r4
1444 stb r4,0x0000(r3)
1454 sth r4,0x0000(r3)
1464 sthbrx r4,r0,r3
1474 stw r4,0x0000(r3)
1484 stwbrx r4,r0,r3
1533 mtspr MAS1,r4
1563 mr r9,r4 /* Save copy of Init Data pointer */
1569 lis r4,CONFIG_SYS_MONITOR_BASE@h /* Source Address */
1570 ori r4,r4,CONFIG_SYS_MONITOR_BASE@l
1572 sub r5,r5,r4
1582 sub r15,r10,r4
1593 cmplw cr1,r3,r4
1601 la r8,-4(r4)
1609 add r8,r4,r0
1624 mr r4,r3
1625 5: dcbst 0,r4
1626 add r4,r4,r6
1627 cmplw r4,r5
1630 mr r4,r3
1631 6: icbi 0,r4
1632 add r4,r4,r6
1633 cmplw r4,r5
1691 3: lwzu r4,4(r3)
1692 lwzux r0,r4,r11
1695 stw r4,0(r3)
1697 stw r0,0(r4)
1705 lwz r4,GOT(__bss_end)
1707 cmplw 0,r3,r4
1714 cmplw 0,r3,r4
1719 mr r4,r10 /* Destination Address */
1738 lwz r4,CriticalInput@got(r12)
1739 mtspr IVOR0,r4 /* 0: Critical input */
1740 lwz r4,MachineCheck@got(r12)
1741 mtspr IVOR1,r4 /* 1: Machine check */
1742 lwz r4,DataStorage@got(r12)
1743 mtspr IVOR2,r4 /* 2: Data storage */
1744 lwz r4,InstStorage@got(r12)
1745 mtspr IVOR3,r4 /* 3: Instruction storage */
1746 lwz r4,ExtInterrupt@got(r12)
1747 mtspr IVOR4,r4 /* 4: External interrupt */
1748 lwz r4,Alignment@got(r12)
1749 mtspr IVOR5,r4 /* 5: Alignment */
1750 lwz r4,ProgramCheck@got(r12)
1751 mtspr IVOR6,r4 /* 6: Program check */
1752 lwz r4,FPUnavailable@got(r12)
1753 mtspr IVOR7,r4 /* 7: floating point unavailable */
1754 lwz r4,SystemCall@got(r12)
1755 mtspr IVOR8,r4 /* 8: System call */
1757 lwz r4,Decrementer@got(r12)
1758 mtspr IVOR10,r4 /* 10: Decrementer */
1759 lwz r4,IntervalTimer@got(r12)
1760 mtspr IVOR11,r4 /* 11: Interval timer */
1761 lwz r4,WatchdogTimer@got(r12)
1762 mtspr IVOR12,r4 /* 12: Watchdog timer */
1763 lwz r4,DataTLBError@got(r12)
1764 mtspr IVOR13,r4 /* 13: Data TLB error */
1765 lwz r4,InstructionTLBError@got(r12)
1766 mtspr IVOR14,r4 /* 14: Instruction TLB error */
1767 lwz r4,DebugBreakpoint@got(r12)
1768 mtspr IVOR15,r4 /* 15: Debug */
1778 mfspr r4,L1CFG0
1779 andi. r4,r4,0x1ff
1780 slwi r4,r4,(10 - 1 - L1_CACHE_SHIFT)
1781 mtctr r4
1814 li r4,32
1818 slw r5,r4,r5 /* r5 = cache block size */
1832 lis r4,0
1835 1: lwz r3,0(r4) /* Load... */
1836 add r4,r4,r5
1840 lis r4,0
1843 1: dcbf 0,r4 /* ...and flush. */
1844 add r4,r4,r5