1a47a12beSStefan Roese/* 2a47a12beSStefan Roese * Copyright (C) 2002 Wolfgang Denk <wd@denx.de> 3a47a12beSStefan Roese * 4*1a459660SWolfgang Denk * SPDX-License-Identifier: GPL-2.0+ 5a47a12beSStefan Roese */ 6a47a12beSStefan Roese 7a47a12beSStefan Roese#include <config.h> 8a47a12beSStefan Roese 9a47a12beSStefan Roese#include <post.h> 10a47a12beSStefan Roese#include <ppc_asm.tmpl> 11a47a12beSStefan Roese#include <ppc_defs.h> 12a47a12beSStefan Roese#include <asm/cache.h> 13a47a12beSStefan Roese 14a47a12beSStefan Roese#if CONFIG_POST & CONFIG_SYS_POST_CPU 15a47a12beSStefan Roese 16a47a12beSStefan Roese/* void cpu_post_exec_02 (ulong *code, ulong op1, ulong op2); */ 17a47a12beSStefan Roese .global cpu_post_exec_02 18a47a12beSStefan Roesecpu_post_exec_02: 19a47a12beSStefan Roese isync 20a47a12beSStefan Roese mflr r0 21a47a12beSStefan Roese stwu r0, -4(r1) 22a47a12beSStefan Roese 23a47a12beSStefan Roese subi r1, r1, 104 24a47a12beSStefan Roese stmw r6, 0(r1) 25a47a12beSStefan Roese 26a47a12beSStefan Roese mtlr r3 27a47a12beSStefan Roese mr r3, r4 28a47a12beSStefan Roese mr r4, r5 29a47a12beSStefan Roese blrl 30a47a12beSStefan Roese 31a47a12beSStefan Roese lmw r6, 0(r1) 32a47a12beSStefan Roese addi r1, r1, 104 33a47a12beSStefan Roese 34a47a12beSStefan Roese lwz r0, 0(r1) 35a47a12beSStefan Roese addi r1, r1, 4 36a47a12beSStefan Roese mtlr r0 37a47a12beSStefan Roese blr 38a47a12beSStefan Roese 39a47a12beSStefan Roese/* void cpu_post_exec_04 (ulong *code, ulong op1, ulong op2, ulong op3, ulong op4); */ 40a47a12beSStefan Roese .global cpu_post_exec_04 41a47a12beSStefan Roesecpu_post_exec_04: 42a47a12beSStefan Roese isync 43a47a12beSStefan Roese mflr r0 44a47a12beSStefan Roese stwu r0, -4(r1) 45a47a12beSStefan Roese 46a47a12beSStefan Roese subi r1, r1, 96 47a47a12beSStefan Roese stmw r8, 0(r1) 48a47a12beSStefan Roese 49a47a12beSStefan Roese mtlr r3 50a47a12beSStefan Roese mr r3, r4 51a47a12beSStefan Roese mr r4, r5 52a47a12beSStefan Roese mr r5, r6 53a47a12beSStefan Roese mtxer r7 54a47a12beSStefan Roese blrl 55a47a12beSStefan Roese 56a47a12beSStefan Roese lmw r8, 0(r1) 57a47a12beSStefan Roese addi r1, r1, 96 58a47a12beSStefan Roese 59a47a12beSStefan Roese lwz r0, 0(r1) 60a47a12beSStefan Roese addi r1, r1, 4 61a47a12beSStefan Roese mtlr r0 62a47a12beSStefan Roese blr 63a47a12beSStefan Roese 64a47a12beSStefan Roese/* void cpu_post_exec_12 (ulong *code, ulong *res, ulong op1, ulong op2); */ 65a47a12beSStefan Roese .global cpu_post_exec_12 66a47a12beSStefan Roesecpu_post_exec_12: 67a47a12beSStefan Roese isync 68a47a12beSStefan Roese mflr r0 69a47a12beSStefan Roese stwu r0, -4(r1) 70a47a12beSStefan Roese stwu r4, -4(r1) 71a47a12beSStefan Roese 72a47a12beSStefan Roese mtlr r3 73a47a12beSStefan Roese mr r3, r5 74a47a12beSStefan Roese mr r4, r6 75a47a12beSStefan Roese blrl 76a47a12beSStefan Roese 77a47a12beSStefan Roese lwz r4, 0(r1) 78a47a12beSStefan Roese stw r3, 0(r4) 79a47a12beSStefan Roese 80a47a12beSStefan Roese lwz r0, 4(r1) 81a47a12beSStefan Roese addi r1, r1, 8 82a47a12beSStefan Roese mtlr r0 83a47a12beSStefan Roese blr 84a47a12beSStefan Roese 85a47a12beSStefan Roese/* void cpu_post_exec_11 (ulong *code, ulong *res, ulong op1); */ 86a47a12beSStefan Roese .global cpu_post_exec_11 87a47a12beSStefan Roesecpu_post_exec_11: 88a47a12beSStefan Roese isync 89a47a12beSStefan Roese mflr r0 90a47a12beSStefan Roese stwu r0, -4(r1) 91a47a12beSStefan Roese stwu r4, -4(r1) 92a47a12beSStefan Roese 93a47a12beSStefan Roese mtlr r3 94a47a12beSStefan Roese mr r3, r5 95a47a12beSStefan Roese blrl 96a47a12beSStefan Roese 97a47a12beSStefan Roese lwz r4, 0(r1) 98a47a12beSStefan Roese stw r3, 0(r4) 99a47a12beSStefan Roese 100a47a12beSStefan Roese lwz r0, 4(r1) 101a47a12beSStefan Roese addi r1, r1, 8 102a47a12beSStefan Roese mtlr r0 103a47a12beSStefan Roese blr 104a47a12beSStefan Roese 105a47a12beSStefan Roese/* void cpu_post_exec_21 (ulong *code, ulong *cr, ulong *res, ulong op1); */ 106a47a12beSStefan Roese .global cpu_post_exec_21 107a47a12beSStefan Roesecpu_post_exec_21: 108a47a12beSStefan Roese isync 109a47a12beSStefan Roese mflr r0 110a47a12beSStefan Roese stwu r0, -4(r1) 111a47a12beSStefan Roese stwu r4, -4(r1) 112a47a12beSStefan Roese stwu r5, -4(r1) 113a47a12beSStefan Roese 114a47a12beSStefan Roese li r0, 0 115a47a12beSStefan Roese mtxer r0 116a47a12beSStefan Roese lwz r0, 0(r4) 117a47a12beSStefan Roese mtcr r0 118a47a12beSStefan Roese 119a47a12beSStefan Roese mtlr r3 120a47a12beSStefan Roese mr r3, r6 121a47a12beSStefan Roese blrl 122a47a12beSStefan Roese 123a47a12beSStefan Roese mfcr r0 124a47a12beSStefan Roese lwz r4, 4(r1) 125a47a12beSStefan Roese stw r0, 0(r4) 126a47a12beSStefan Roese lwz r4, 0(r1) 127a47a12beSStefan Roese stw r3, 0(r4) 128a47a12beSStefan Roese 129a47a12beSStefan Roese lwz r0, 8(r1) 130a47a12beSStefan Roese addi r1, r1, 12 131a47a12beSStefan Roese mtlr r0 132a47a12beSStefan Roese blr 133a47a12beSStefan Roese 134a47a12beSStefan Roese/* void cpu_post_exec_22 (ulong *code, ulong *cr, ulong *res, ulong op1, 135a47a12beSStefan Roese ulong op2); */ 136a47a12beSStefan Roese .global cpu_post_exec_22 137a47a12beSStefan Roesecpu_post_exec_22: 138a47a12beSStefan Roese isync 139a47a12beSStefan Roese mflr r0 140a47a12beSStefan Roese stwu r0, -4(r1) 141a47a12beSStefan Roese stwu r4, -4(r1) 142a47a12beSStefan Roese stwu r5, -4(r1) 143a47a12beSStefan Roese 144a47a12beSStefan Roese li r0, 0 145a47a12beSStefan Roese mtxer r0 146a47a12beSStefan Roese lwz r0, 0(r4) 147a47a12beSStefan Roese mtcr r0 148a47a12beSStefan Roese 149a47a12beSStefan Roese mtlr r3 150a47a12beSStefan Roese mr r3, r6 151a47a12beSStefan Roese mr r4, r7 152a47a12beSStefan Roese blrl 153a47a12beSStefan Roese 154a47a12beSStefan Roese mfcr r0 155a47a12beSStefan Roese lwz r4, 4(r1) 156a47a12beSStefan Roese stw r0, 0(r4) 157a47a12beSStefan Roese lwz r4, 0(r1) 158a47a12beSStefan Roese stw r3, 0(r4) 159a47a12beSStefan Roese 160a47a12beSStefan Roese lwz r0, 8(r1) 161a47a12beSStefan Roese addi r1, r1, 12 162a47a12beSStefan Roese mtlr r0 163a47a12beSStefan Roese blr 164a47a12beSStefan Roese 165a47a12beSStefan Roese/* void cpu_post_exec_12w (ulong *code, ulong *op1, ulong op2, ulong op3); */ 166a47a12beSStefan Roese .global cpu_post_exec_12w 167a47a12beSStefan Roesecpu_post_exec_12w: 168a47a12beSStefan Roese isync 169a47a12beSStefan Roese mflr r0 170a47a12beSStefan Roese stwu r0, -4(r1) 171a47a12beSStefan Roese stwu r4, -4(r1) 172a47a12beSStefan Roese 173a47a12beSStefan Roese mtlr r3 174a47a12beSStefan Roese lwz r3, 0(r4) 175a47a12beSStefan Roese mr r4, r5 176a47a12beSStefan Roese mr r5, r6 177a47a12beSStefan Roese blrl 178a47a12beSStefan Roese 179a47a12beSStefan Roese lwz r4, 0(r1) 180a47a12beSStefan Roese stw r3, 0(r4) 181a47a12beSStefan Roese 182a47a12beSStefan Roese lwz r0, 4(r1) 183a47a12beSStefan Roese addi r1, r1, 8 184a47a12beSStefan Roese mtlr r0 185a47a12beSStefan Roese blr 186a47a12beSStefan Roese 187a47a12beSStefan Roese/* void cpu_post_exec_11w (ulong *code, ulong *op1, ulong op2); */ 188a47a12beSStefan Roese .global cpu_post_exec_11w 189a47a12beSStefan Roesecpu_post_exec_11w: 190a47a12beSStefan Roese isync 191a47a12beSStefan Roese mflr r0 192a47a12beSStefan Roese stwu r0, -4(r1) 193a47a12beSStefan Roese stwu r4, -4(r1) 194a47a12beSStefan Roese 195a47a12beSStefan Roese mtlr r3 196a47a12beSStefan Roese lwz r3, 0(r4) 197a47a12beSStefan Roese mr r4, r5 198a47a12beSStefan Roese blrl 199a47a12beSStefan Roese 200a47a12beSStefan Roese lwz r4, 0(r1) 201a47a12beSStefan Roese stw r3, 0(r4) 202a47a12beSStefan Roese 203a47a12beSStefan Roese lwz r0, 4(r1) 204a47a12beSStefan Roese addi r1, r1, 8 205a47a12beSStefan Roese mtlr r0 206a47a12beSStefan Roese blr 207a47a12beSStefan Roese 208a47a12beSStefan Roese/* void cpu_post_exec_22w (ulong *code, ulong *op1, ulong op2, ulong *op3); */ 209a47a12beSStefan Roese .global cpu_post_exec_22w 210a47a12beSStefan Roesecpu_post_exec_22w: 211a47a12beSStefan Roese isync 212a47a12beSStefan Roese mflr r0 213a47a12beSStefan Roese stwu r0, -4(r1) 214a47a12beSStefan Roese stwu r4, -4(r1) 215a47a12beSStefan Roese stwu r6, -4(r1) 216a47a12beSStefan Roese 217a47a12beSStefan Roese mtlr r3 218a47a12beSStefan Roese lwz r3, 0(r4) 219a47a12beSStefan Roese mr r4, r5 220a47a12beSStefan Roese blrl 221a47a12beSStefan Roese 222a47a12beSStefan Roese lwz r4, 4(r1) 223a47a12beSStefan Roese stw r3, 0(r4) 224a47a12beSStefan Roese lwz r4, 0(r1) 225a47a12beSStefan Roese stw r5, 0(r4) 226a47a12beSStefan Roese 227a47a12beSStefan Roese lwz r0, 8(r1) 228a47a12beSStefan Roese addi r1, r1, 12 229a47a12beSStefan Roese mtlr r0 230a47a12beSStefan Roese blr 231a47a12beSStefan Roese 232a47a12beSStefan Roese/* void cpu_post_exec_21w (ulong *code, ulong *op1, ulong *op2); */ 233a47a12beSStefan Roese .global cpu_post_exec_21w 234a47a12beSStefan Roesecpu_post_exec_21w: 235a47a12beSStefan Roese isync 236a47a12beSStefan Roese mflr r0 237a47a12beSStefan Roese stwu r0, -4(r1) 238a47a12beSStefan Roese stwu r4, -4(r1) 239a47a12beSStefan Roese stwu r5, -4(r1) 240a47a12beSStefan Roese 241a47a12beSStefan Roese mtlr r3 242a47a12beSStefan Roese lwz r3, 0(r4) 243a47a12beSStefan Roese blrl 244a47a12beSStefan Roese 245a47a12beSStefan Roese lwz r5, 4(r1) 246a47a12beSStefan Roese stw r3, 0(r5) 247a47a12beSStefan Roese lwz r5, 0(r1) 248a47a12beSStefan Roese stw r4, 0(r5) 249a47a12beSStefan Roese 250a47a12beSStefan Roese lwz r0, 8(r1) 251a47a12beSStefan Roese addi r1, r1, 12 252a47a12beSStefan Roese mtlr r0 253a47a12beSStefan Roese blr 254a47a12beSStefan Roese 255a47a12beSStefan Roese/* void cpu_post_exec_21x (ulong *code, ulong *op1, ulong *op2, ulong op3); */ 256a47a12beSStefan Roese .global cpu_post_exec_21x 257a47a12beSStefan Roesecpu_post_exec_21x: 258a47a12beSStefan Roese isync 259a47a12beSStefan Roese mflr r0 260a47a12beSStefan Roese stwu r0, -4(r1) 261a47a12beSStefan Roese stwu r4, -4(r1) 262a47a12beSStefan Roese stwu r5, -4(r1) 263a47a12beSStefan Roese 264a47a12beSStefan Roese mtlr r3 265a47a12beSStefan Roese mr r3, r6 266a47a12beSStefan Roese blrl 267a47a12beSStefan Roese 268a47a12beSStefan Roese lwz r5, 4(r1) 269a47a12beSStefan Roese stw r3, 0(r5) 270a47a12beSStefan Roese lwz r5, 0(r1) 271a47a12beSStefan Roese stw r4, 0(r5) 272a47a12beSStefan Roese 273a47a12beSStefan Roese lwz r0, 8(r1) 274a47a12beSStefan Roese addi r1, r1, 12 275a47a12beSStefan Roese mtlr r0 276a47a12beSStefan Roese blr 277a47a12beSStefan Roese 278a47a12beSStefan Roese/* void cpu_post_exec_31 (ulong *code, ulong *ctr, ulong *lr, ulong *jump, 279a47a12beSStefan Roese ulong cr); */ 280a47a12beSStefan Roese .global cpu_post_exec_31 281a47a12beSStefan Roesecpu_post_exec_31: 282a47a12beSStefan Roese isync 283a47a12beSStefan Roese mflr r0 284a47a12beSStefan Roese stwu r0, -4(r1) 285a47a12beSStefan Roese stwu r4, -4(r1) 286a47a12beSStefan Roese stwu r5, -4(r1) 287a47a12beSStefan Roese stwu r6, -4(r1) 288a47a12beSStefan Roese 289a47a12beSStefan Roese mtlr r3 290a47a12beSStefan Roese lwz r3, 0(r4) 291a47a12beSStefan Roese lwz r4, 0(r5) 292a47a12beSStefan Roese mr r6, r7 293a47a12beSStefan Roese 294a47a12beSStefan Roese mfcr r7 295a47a12beSStefan Roese blrl 296a47a12beSStefan Roese mtcr r7 297a47a12beSStefan Roese 298a47a12beSStefan Roese lwz r7, 8(r1) 299a47a12beSStefan Roese stw r3, 0(r7) 300a47a12beSStefan Roese lwz r7, 4(r1) 301a47a12beSStefan Roese stw r4, 0(r7) 302a47a12beSStefan Roese lwz r7, 0(r1) 303a47a12beSStefan Roese stw r5, 0(r7) 304a47a12beSStefan Roese 305a47a12beSStefan Roese lwz r0, 12(r1) 306a47a12beSStefan Roese addi r1, r1, 16 307a47a12beSStefan Roese mtlr r0 308a47a12beSStefan Roese blr 309a47a12beSStefan Roese 310a47a12beSStefan Roese/* int cpu_post_complex_1_asm (int a1, int a2, int a3, int a4, int n); */ 311a47a12beSStefan Roese .global cpu_post_complex_1_asm 312a47a12beSStefan Roesecpu_post_complex_1_asm: 313a47a12beSStefan Roese li r9,0 314a47a12beSStefan Roese cmpw r9,r7 315a47a12beSStefan Roese bge cpu_post_complex_1_done 316a47a12beSStefan Roese mtctr r7 317a47a12beSStefan Roesecpu_post_complex_1_loop: 318a47a12beSStefan Roese mullw r0,r3,r4 319a47a12beSStefan Roese subf r0,r5,r0 320a47a12beSStefan Roese divw r0,r0,r6 321a47a12beSStefan Roese add r9,r9,r0 322a47a12beSStefan Roese bdnz cpu_post_complex_1_loop 323a47a12beSStefan Roesecpu_post_complex_1_done: 324a47a12beSStefan Roese mr r3,r9 325a47a12beSStefan Roese blr 326a47a12beSStefan Roese 327a47a12beSStefan Roese/* int cpu_post_complex_2_asm (int x, int n); */ 328a47a12beSStefan Roese .global cpu_post_complex_2_asm 329a47a12beSStefan Roesecpu_post_complex_2_asm: 330a47a12beSStefan Roese mr. r0,r4 331a47a12beSStefan Roese mtctr r0 332a47a12beSStefan Roese mr r0,r3 333a47a12beSStefan Roese li r3,1 334a47a12beSStefan Roese li r4,1 335a47a12beSStefan Roese blelr 336a47a12beSStefan Roesecpu_post_complex_2_loop: 337a47a12beSStefan Roese mullw r3,r3,r0 338a47a12beSStefan Roese add r3,r3,r4 339a47a12beSStefan Roese bdnz cpu_post_complex_2_loop 340a47a12beSStefan Roeseblr 341a47a12beSStefan Roese 342a47a12beSStefan Roese#endif 343