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Searched refs:pin (Results 1 – 25 of 279) sorted by relevance

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/rk3399_rockchip-uboot/board/sunxi/
H A Dgmac.c11 int pin; in eth_init_board() local
36 for (pin = SUNXI_GPA(0); pin <= SUNXI_GPA(16); pin++) { in eth_init_board()
39 if (pin == SUNXI_GPA(9) || pin == SUNXI_GPA(14)) in eth_init_board()
42 sunxi_gpio_set_cfgpin(pin, SUN7I_GPA_GMAC); in eth_init_board()
43 sunxi_gpio_set_drv(pin, 3); in eth_init_board()
47 for (pin = SUNXI_GPA(0); pin <= SUNXI_GPA(3); pin++) { in eth_init_board()
48 sunxi_gpio_set_cfgpin(pin, SUN6I_GPA_GMAC); in eth_init_board()
49 sunxi_gpio_set_drv(pin, 3); in eth_init_board()
51 for (pin = SUNXI_GPA(9); pin <= SUNXI_GPA(14); pin++) { in eth_init_board()
52 sunxi_gpio_set_cfgpin(pin, SUN6I_GPA_GMAC); in eth_init_board()
[all …]
H A Dboard.c248 unsigned int pin; in nand_pinmux_setup() local
250 for (pin = SUNXI_GPC(0); pin <= SUNXI_GPC(19); pin++) in nand_pinmux_setup()
251 sunxi_gpio_set_cfgpin(pin, SUNXI_GPC_NAND); in nand_pinmux_setup()
254 for (pin = SUNXI_GPC(20); pin <= SUNXI_GPC(22); pin++) in nand_pinmux_setup()
255 sunxi_gpio_set_cfgpin(pin, SUNXI_GPC_NAND); in nand_pinmux_setup()
291 unsigned int pin; in mmc_pinmux_setup() local
297 for (pin = SUNXI_GPF(0); pin <= SUNXI_GPF(5); pin++) { in mmc_pinmux_setup()
298 sunxi_gpio_set_cfgpin(pin, SUNXI_GPF_SDC0); in mmc_pinmux_setup()
299 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP); in mmc_pinmux_setup()
300 sunxi_gpio_set_drv(pin, 2); in mmc_pinmux_setup()
[all …]
/rk3399_rockchip-uboot/drivers/gpio/
H A Dkw_gpio.c25 void __set_direction(unsigned pin, int input) in __set_direction() argument
29 u = readl(GPIO_IO_CONF(pin)); in __set_direction()
31 u |= 1 << (pin & 31); in __set_direction()
33 u &= ~(1 << (pin & 31)); in __set_direction()
34 writel(u, GPIO_IO_CONF(pin)); in __set_direction()
36 u = readl(GPIO_IO_CONF(pin)); in __set_direction()
39 static void __set_level(unsigned pin, int high) in __set_level() argument
43 u = readl(GPIO_OUT(pin)); in __set_level()
45 u |= 1 << (pin & 31); in __set_level()
47 u &= ~(1 << (pin & 31)); in __set_level()
[all …]
H A Dat91_gpio.c59 int at91_set_pio_pullup(unsigned port, unsigned pin, int use_pullup) in at91_set_pio_pullup() argument
63 if (at91_port && (pin < GPIO_PER_BANK)) in at91_set_pio_pullup()
64 at91_set_port_pullup(at91_port, pin, use_pullup); in at91_set_pio_pullup()
72 int at91_set_pio_periph(unsigned port, unsigned pin, int use_pullup) in at91_set_pio_periph() argument
77 if (at91_port && (pin < GPIO_PER_BANK)) { in at91_set_pio_periph()
78 mask = 1 << pin; in at91_set_pio_periph()
80 at91_set_pio_pullup(port, pin, use_pullup); in at91_set_pio_periph()
90 int at91_set_a_periph(unsigned port, unsigned pin, int use_pullup) in at91_set_a_periph() argument
95 if (at91_port && (pin < GPIO_PER_BANK)) { in at91_set_a_periph()
96 mask = 1 << pin; in at91_set_a_periph()
[all …]
H A Daxp_gpio.c20 static int axp_gpio_set_value(struct udevice *dev, unsigned pin, int val);
22 static u8 axp_get_gpio_ctrl_reg(unsigned pin) in axp_get_gpio_ctrl_reg() argument
24 switch (pin) { in axp_get_gpio_ctrl_reg()
37 static int axp_gpio_direction_input(struct udevice *dev, unsigned pin) in axp_gpio_direction_input() argument
41 switch (pin) { in axp_gpio_direction_input()
47 reg = axp_get_gpio_ctrl_reg(pin); in axp_gpio_direction_input()
55 static int axp_gpio_direction_output(struct udevice *dev, unsigned pin, in axp_gpio_direction_output() argument
61 switch (pin) { in axp_gpio_direction_output()
70 return axp_gpio_set_value(dev, pin, val); in axp_gpio_direction_output()
73 reg = axp_get_gpio_ctrl_reg(pin); in axp_gpio_direction_output()
[all …]
/rk3399_rockchip-uboot/arch/arm/mach-kirkwood/include/mach/
H A Dgpio.h19 #define GPIO_OFF(pin) (((pin) >> 5) ? 0x0040 : 0x0000) argument
20 #define GPIO_OUT(pin) (MVEBU_GPIO0_BASE + GPIO_OFF(pin) + 0x00) argument
21 #define GPIO_IO_CONF(pin) (MVEBU_GPIO0_BASE + GPIO_OFF(pin) + 0x04) argument
22 #define GPIO_BLINK_EN(pin) (MVEBU_GPIO0_BASE + GPIO_OFF(pin) + 0x08) argument
23 #define GPIO_IN_POL(pin) (MVEBU_GPIO0_BASE + GPIO_OFF(pin) + 0x0c) argument
24 #define GPIO_DATA_IN(pin) (MVEBU_GPIO0_BASE + GPIO_OFF(pin) + 0x10) argument
25 #define GPIO_EDGE_CAUSE(pin) (MVEBU_GPIO0_BASE + GPIO_OFF(pin) + 0x14) argument
26 #define GPIO_EDGE_MASK(pin) (MVEBU_GPIO0_BASE + GPIO_OFF(pin) + 0x18) argument
27 #define GPIO_LEVEL_MASK(pin) (MVEBU_GPIO0_BASE + GPIO_OFF(pin) + 0x1c) argument
33 void kw_gpio_set_valid(unsigned pin, int mode);
[all …]
/rk3399_rockchip-uboot/arch/arm/dts/
H A Dsama5d3_lcd.dtsi61 <AT91_PIOA 0 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD0 pin */
62 AT91_PIOA 1 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD1 pin */
63 AT91_PIOA 2 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD2 pin */
64 AT91_PIOA 3 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD3 pin */
65 AT91_PIOA 4 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD4 pin */
66 AT91_PIOA 5 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD5 pin */
67 AT91_PIOA 6 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD6 pin */
68 AT91_PIOA 7 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD7 pin */
69 AT91_PIOA 8 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD8 pin */
70 AT91_PIOA 9 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD9 pin */
[all …]
H A Dat91sam9x5_lcd.dtsi42 <AT91_PIOC 0 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD0 pin */
43 AT91_PIOC 1 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD1 pin */
44 AT91_PIOC 2 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD2 pin */
45 AT91_PIOC 3 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD3 pin */
46 AT91_PIOC 4 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD4 pin */
47 AT91_PIOC 5 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD5 pin */
48 AT91_PIOC 6 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD6 pin */
49 AT91_PIOC 7 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD7 pin */
50 AT91_PIOC 8 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD8 pin */
51 AT91_PIOC 9 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD9 pin */
[all …]
/rk3399_rockchip-uboot/arch/arm/cpu/arm920t/imx/
H A Dgeneric.c21 unsigned int pin = gpio_mode & GPIO_PIN_MASK; in imx_gpio_mode() local
28 PUEN(port) |= (1<<pin); in imx_gpio_mode()
30 PUEN(port) &= ~(1<<pin); in imx_gpio_mode()
34 DDIR(port) |= 1<<pin; in imx_gpio_mode()
36 DDIR(port) &= ~(1<<pin); in imx_gpio_mode()
40 GPR(port) |= (1<<pin); in imx_gpio_mode()
42 GPR(port) &= ~(1<<pin); in imx_gpio_mode()
46 GIUS(port) |= (1<<pin); in imx_gpio_mode()
48 GIUS(port) &= ~(1<<pin); in imx_gpio_mode()
54 if(pin<16) { in imx_gpio_mode()
[all …]
/rk3399_rockchip-uboot/drivers/pinctrl/rockchip/
H A Dpinctrl-rk3308.c19 .pin = 19,
26 .pin = 22,
33 .pin = 26,
40 .pin = 23,
47 .pin = 12,
54 .pin = 3,
61 .pin = 4,
68 .pin = 13,
75 .pin = 14,
82 .pin = 4,
[all …]
H A Dpinctrl-rockchip-core.c21 static int rockchip_verify_config(struct udevice *dev, u32 bank, u32 pin) in rockchip_verify_config() argument
31 if (pin >= MAX_ROCKCHIP_GPIO_PER_BANK) { in rockchip_verify_config()
32 debug("pin conf pin %d >= %d\n", pin, in rockchip_verify_config()
40 void rockchip_get_recalced_mux(struct rockchip_pin_bank *bank, int pin, in rockchip_get_recalced_mux() argument
51 data->pin == pin) in rockchip_get_recalced_mux()
64 rockchip_get_mux_route(struct rockchip_pin_bank *bank, int pin, in rockchip_get_mux_route() argument
75 data->pin == pin && data->func == mux) in rockchip_get_mux_route()
88 int rockchip_get_mux_data(int mux_type, int pin, u8 *bit, int *mask) in rockchip_get_mux_data() argument
93 if ((pin % 8) >= 4) in rockchip_get_mux_data()
95 *bit = (pin % 4) * 4; in rockchip_get_mux_data()
[all …]
H A Dpinctrl-rk3128.c17 .pin = 20,
23 .pin = 21,
29 .pin = 22,
35 .pin = 23,
41 .pin = 24,
52 .pin = 10,
59 .pin = 27,
66 .pin = 13,
73 .pin = 5,
80 .pin = 14,
[all …]
H A Dpinctrl-rk3328.c18 .pin = 15,
25 .pin = 23,
32 .pin = 9,
39 .pin = 10,
46 .pin = 11,
53 .pin = 12,
60 .pin = 13,
67 .pin = 14,
74 .pin = 15,
85 .pin = 1,
[all …]
H A Dpinctrl-rk322x.c18 .pin = 26,
25 .pin = 21,
32 .pin = 27,
39 .pin = 30,
46 .pin = 28,
53 .pin = 12,
60 .pin = 26,
67 .pin = 11,
74 .pin = 1,
81 .pin = 2,
[all …]
/rk3399_rockchip-uboot/board/micronas/vct/
H A Dgpio.c17 #define GPIO_MODULE(pin) ((pin) >> 5) argument
23 #define MASK(pin) (1 << ((pin) & 0x1F)) argument
40 int vct_gpio_dir(int pin, int dir) in vct_gpio_dir() argument
44 gpio_base = BASE_ADDR(GPIO_MODULE(pin)); in vct_gpio_dir()
47 clrsetbits(GPIO_SWPORTA_DDR(gpio_base), MASK(pin), 0); in vct_gpio_dir()
49 clrsetbits(GPIO_SWPORTA_DDR(gpio_base), 0, MASK(pin)); in vct_gpio_dir()
54 void vct_gpio_set(int pin, int val) in vct_gpio_set() argument
58 gpio_base = BASE_ADDR(GPIO_MODULE(pin)); in vct_gpio_set()
61 clrsetbits(GPIO_SWPORTA_DR(gpio_base), MASK(pin), 0); in vct_gpio_set()
63 clrsetbits(GPIO_SWPORTA_DR(gpio_base), 0, MASK(pin)); in vct_gpio_set()
[all …]
H A Dtop.c27 static TOP_PINMUX_t top_read_pin(int pin) in top_read_pin() argument
31 switch (pin) { in top_read_pin()
58 ((pin - 10) * 4)); in top_read_pin()
61 reg.reg = reg_read(TOP_BASE + (pin * 4)); in top_read_pin()
68 static void top_write_pin(int pin, TOP_PINMUX_t reg) in top_write_pin() argument
71 switch (pin) { in top_write_pin()
92 ((pin - 10) * 4), reg.reg); in top_write_pin()
95 reg_write(TOP_BASE + (pin * 4), reg.reg); in top_write_pin()
100 int top_set_pin(int pin, int func) in top_set_pin() argument
105 if ((pin < 0) || (pin > 170) || (func < 0) || (func > 3)) in top_set_pin()
[all …]
/rk3399_rockchip-uboot/board/LaCie/common/
H A Dcpld-gpio-bus.c20 int pin; in cpld_gpio_bus_set_addr() local
22 for (pin = 0; pin < bus->num_addr; pin++) in cpld_gpio_bus_set_addr()
23 kw_gpio_set_value(bus->addr[pin], (addr >> pin) & 1); in cpld_gpio_bus_set_addr()
28 int pin; in cpld_gpio_bus_set_data() local
30 for (pin = 0; pin < bus->num_data; pin++) in cpld_gpio_bus_set_data()
31 kw_gpio_set_value(bus->data[pin], (data >> pin) & 1); in cpld_gpio_bus_set_data()
/rk3399_rockchip-uboot/arch/arm/mach-tegra/
H A Dpinmux-common.c13 #define pmux_pingrp_isvalid(pin) (((pin) >= 0) && ((pin) < PMUX_PINGRP_COUNT)) argument
96 #define REG(pin) _R(0x3000 + ((pin) * 4)) argument
98 #define MUX_REG(pin) REG(pin) argument
99 #define MUX_SHIFT(pin) 0 argument
101 #define PULL_REG(pin) REG(pin) argument
102 #define PULL_SHIFT(pin) 2 argument
104 #define TRI_REG(pin) REG(pin) argument
105 #define TRI_SHIFT(pin) 4 argument
158 void pinmux_set_func(enum pmux_pingrp pin, enum pmux_func func) in pinmux_set_func() argument
160 u32 *reg = MUX_REG(pin); in pinmux_set_func()
[all …]
/rk3399_rockchip-uboot/arch/powerpc/include/asm/
H A Diopin_8xx.h21 u_char pin:5; /* port pin (0-31) */ member
37 setbits_be16(datp, 1 << (15 - iopin->pin)); in iopin_set_high()
41 setbits_be32(datp, 1 << (31 - iopin->pin)); in iopin_set_high()
45 setbits_be16(datp, 1 << (15 - iopin->pin)); in iopin_set_high()
49 setbits_be16(datp, 1 << (15 - iopin->pin)); in iopin_set_high()
60 clrbits_be16(datp, 1 << (15 - iopin->pin)); in iopin_set_low()
64 clrbits_be32(datp, 1 << (31 - iopin->pin)); in iopin_set_low()
68 clrbits_be16(datp, 1 << (15 - iopin->pin)); in iopin_set_low()
72 clrbits_be16(datp, 1 << (15 - iopin->pin)); in iopin_set_low()
83 return (in_be16(datp) >> (15 - iopin->pin)) & 1; in iopin_is_high()
[all …]
/rk3399_rockchip-uboot/arch/arm/mach-sunxi/
H A Dpinmux.c21 void sunxi_gpio_set_cfgpin(u32 pin, u32 val) in sunxi_gpio_set_cfgpin() argument
23 u32 bank = GPIO_BANK(pin); in sunxi_gpio_set_cfgpin()
26 sunxi_gpio_set_cfgbank(pio, pin, val); in sunxi_gpio_set_cfgpin()
41 int sunxi_gpio_get_cfgpin(u32 pin) in sunxi_gpio_get_cfgpin() argument
43 u32 bank = GPIO_BANK(pin); in sunxi_gpio_get_cfgpin()
46 return sunxi_gpio_get_cfgbank(pio, pin); in sunxi_gpio_get_cfgpin()
49 int sunxi_gpio_set_drv(u32 pin, u32 val) in sunxi_gpio_set_drv() argument
51 u32 bank = GPIO_BANK(pin); in sunxi_gpio_set_drv()
52 u32 index = GPIO_DRV_INDEX(pin); in sunxi_gpio_set_drv()
53 u32 offset = GPIO_DRV_OFFSET(pin); in sunxi_gpio_set_drv()
[all …]
/rk3399_rockchip-uboot/arch/arm/include/asm/arch-sunxi/
H A Dgpio.h81 #define GPIO_BANK(pin) ((pin) >> 5) argument
82 #define GPIO_NUM(pin) ((pin) & 0x1f) argument
84 #define GPIO_CFG_INDEX(pin) (((pin) & 0x1f) >> 3) argument
85 #define GPIO_CFG_OFFSET(pin) ((((pin) & 0x1f) & 0x7) << 2) argument
87 #define GPIO_DRV_INDEX(pin) (((pin) & 0x1f) >> 4) argument
88 #define GPIO_DRV_OFFSET(pin) ((((pin) & 0x1f) & 0xf) << 1) argument
90 #define GPIO_PULL_INDEX(pin) (((pin) & 0x1f) >> 4) argument
91 #define GPIO_PULL_OFFSET(pin) ((((pin) & 0x1f) & 0xf) << 1) argument
228 void sunxi_gpio_set_cfgpin(u32 pin, u32 val);
230 int sunxi_gpio_get_cfgpin(u32 pin);
[all …]
/rk3399_rockchip-uboot/arch/arm/mach-at91/include/mach/
H A Dat91_pio.h131 int at91_set_a_periph(unsigned port, unsigned pin, int use_pullup);
132 int at91_set_b_periph(unsigned port, unsigned pin, int use_pullup);
133 int at91_set_pio_input(unsigned port, unsigned pin, int use_pullup);
134 int at91_set_pio_multi_drive(unsigned port, unsigned pin, int is_on);
135 int at91_set_pio_output(unsigned port, unsigned pin, int value);
136 int at91_set_pio_periph(unsigned port, unsigned pin, int use_pullup);
137 int at91_set_pio_pullup(unsigned port, unsigned pin, int use_pullup);
138 int at91_set_pio_deglitch(unsigned port, unsigned pin, int is_on);
139 int at91_set_pio_value(unsigned port, unsigned pin, int value);
140 int at91_get_pio_value(unsigned port, unsigned pin);
[all …]
/rk3399_rockchip-uboot/drivers/misc/
H A Dali512x.c329 void ali512x_cio_function(int pin, int special, int inv, int input) in ali512x_cio_function() argument
335 if (pin >= 10 && pin <= 17) { in ali512x_cio_function()
336 addr = 0xe0+(pin&7); in ali512x_cio_function()
337 } else if (pin >= 20 && pin <= 25) { in ali512x_cio_function()
338 addr = 0xe8+(pin&7); in ali512x_cio_function()
339 } else if (pin >= 30 && pin <= 37) { in ali512x_cio_function()
340 addr = 0xf5+(pin&7); in ali512x_cio_function()
367 void ali512x_cio_out(int pin, int value) in ali512x_cio_out() argument
373 reg = pin/10; in ali512x_cio_out()
374 bit = 1 << (pin%10); in ali512x_cio_out()
[all …]
/rk3399_rockchip-uboot/doc/device-tree-bindings/pinctrl/
H A Dpinctrl-bindings.txt3 Hardware modules that control pin multiplexing or configuration parameters
4 such as pull-up/down, tri-state, drive-strength etc are designated as pin
5 controllers. Each pin controller must be represented as a node in device tree,
8 Hardware modules whose signals are affected by pin configuration are
12 For a client device to operate correctly, certain pin controllers must
13 set up certain specific pin configurations. Some client devices need a
14 single static pin configuration, e.g. set up during initialization. Others
21 for client device device tree nodes to map those state names to the pin
24 Note that pin controllers themselves may also be client devices of themselves.
25 For example, a pin controller may set up its own "active" state when the
[all …]
/rk3399_rockchip-uboot/drivers/pinctrl/
H A Dpinctrl-rockchip.c307 .pin = PIN, \
333 u8 pin; member
350 u8 pin; member
401 static int rockchip_verify_config(struct udevice *dev, u32 bank, u32 pin) in rockchip_verify_config() argument
411 if (pin >= MAX_ROCKCHIP_GPIO_PER_BANK) { in rockchip_verify_config()
412 debug("pin conf pin %d >= %d\n", pin, in rockchip_verify_config()
423 .pin = 0,
429 .pin = 1,
435 .pin = 2,
441 .pin = 3,
[all …]

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