1318c0b90SJean-Christophe PLAGNIOL-VILLARD /*
2318c0b90SJean-Christophe PLAGNIOL-VILLARD * (C) Copyright 2002
3fa82f871SAlbert ARIBAUD * Daniel Engström, Omicron Ceti AB <daniel@omicron.se>.
4318c0b90SJean-Christophe PLAGNIOL-VILLARD *
5*1a459660SWolfgang Denk * SPDX-License-Identifier: GPL-2.0+
6318c0b90SJean-Christophe PLAGNIOL-VILLARD */
7318c0b90SJean-Christophe PLAGNIOL-VILLARD
8318c0b90SJean-Christophe PLAGNIOL-VILLARD /*
9318c0b90SJean-Christophe PLAGNIOL-VILLARD * Based on sc520cdp.c from rolo 1.6:
10318c0b90SJean-Christophe PLAGNIOL-VILLARD *----------------------------------------------------------------------
11318c0b90SJean-Christophe PLAGNIOL-VILLARD * (C) Copyright 2000
12318c0b90SJean-Christophe PLAGNIOL-VILLARD * Sysgo Real-Time Solutions GmbH
13318c0b90SJean-Christophe PLAGNIOL-VILLARD * Klein-Winternheim, Germany
14318c0b90SJean-Christophe PLAGNIOL-VILLARD *----------------------------------------------------------------------
15318c0b90SJean-Christophe PLAGNIOL-VILLARD */
16318c0b90SJean-Christophe PLAGNIOL-VILLARD
17318c0b90SJean-Christophe PLAGNIOL-VILLARD #include <config.h>
18318c0b90SJean-Christophe PLAGNIOL-VILLARD
19318c0b90SJean-Christophe PLAGNIOL-VILLARD #include <common.h>
20318c0b90SJean-Christophe PLAGNIOL-VILLARD #include <asm/io.h>
21ece444b4SGraeme Russ #include <ali512x.h>
22318c0b90SJean-Christophe PLAGNIOL-VILLARD
23318c0b90SJean-Christophe PLAGNIOL-VILLARD
24318c0b90SJean-Christophe PLAGNIOL-VILLARD /* ALI M5123 Logical device numbers:
25318c0b90SJean-Christophe PLAGNIOL-VILLARD * 0 FDC
26318c0b90SJean-Christophe PLAGNIOL-VILLARD * 1 unused?
27318c0b90SJean-Christophe PLAGNIOL-VILLARD * 2 unused?
28318c0b90SJean-Christophe PLAGNIOL-VILLARD * 3 lpt
29318c0b90SJean-Christophe PLAGNIOL-VILLARD * 4 UART1
30318c0b90SJean-Christophe PLAGNIOL-VILLARD * 5 UART2
31318c0b90SJean-Christophe PLAGNIOL-VILLARD * 6 RTC
32318c0b90SJean-Christophe PLAGNIOL-VILLARD * 7 mouse/kbd
33318c0b90SJean-Christophe PLAGNIOL-VILLARD * 8 CIO
34318c0b90SJean-Christophe PLAGNIOL-VILLARD */
35318c0b90SJean-Christophe PLAGNIOL-VILLARD
36318c0b90SJean-Christophe PLAGNIOL-VILLARD /*
37318c0b90SJean-Christophe PLAGNIOL-VILLARD ************************************************************
38318c0b90SJean-Christophe PLAGNIOL-VILLARD * Some access primitives for the ALi chip: *
39318c0b90SJean-Christophe PLAGNIOL-VILLARD ************************************************************
40318c0b90SJean-Christophe PLAGNIOL-VILLARD */
41318c0b90SJean-Christophe PLAGNIOL-VILLARD
ali_write(u8 index,u8 value)42318c0b90SJean-Christophe PLAGNIOL-VILLARD static void ali_write(u8 index, u8 value)
43318c0b90SJean-Christophe PLAGNIOL-VILLARD {
44318c0b90SJean-Christophe PLAGNIOL-VILLARD /* write an arbirary register */
45318c0b90SJean-Christophe PLAGNIOL-VILLARD outb(index, ALI_INDEX);
46318c0b90SJean-Christophe PLAGNIOL-VILLARD outb(value, ALI_DATA);
47318c0b90SJean-Christophe PLAGNIOL-VILLARD }
48318c0b90SJean-Christophe PLAGNIOL-VILLARD
49318c0b90SJean-Christophe PLAGNIOL-VILLARD #if 0
50318c0b90SJean-Christophe PLAGNIOL-VILLARD static int ali_read(u8 index)
51318c0b90SJean-Christophe PLAGNIOL-VILLARD {
52318c0b90SJean-Christophe PLAGNIOL-VILLARD outb(index, ALI_INDEX);
53318c0b90SJean-Christophe PLAGNIOL-VILLARD return inb(ALI_DATA);
54318c0b90SJean-Christophe PLAGNIOL-VILLARD }
55318c0b90SJean-Christophe PLAGNIOL-VILLARD #endif
56318c0b90SJean-Christophe PLAGNIOL-VILLARD
57318c0b90SJean-Christophe PLAGNIOL-VILLARD #define ALI_OPEN() \
58318c0b90SJean-Christophe PLAGNIOL-VILLARD outb(0x51, ALI_INDEX); \
59318c0b90SJean-Christophe PLAGNIOL-VILLARD outb(0x23, ALI_INDEX)
60318c0b90SJean-Christophe PLAGNIOL-VILLARD
61318c0b90SJean-Christophe PLAGNIOL-VILLARD
62318c0b90SJean-Christophe PLAGNIOL-VILLARD #define ALI_CLOSE() \
63318c0b90SJean-Christophe PLAGNIOL-VILLARD outb(0xbb, ALI_INDEX)
64318c0b90SJean-Christophe PLAGNIOL-VILLARD
65318c0b90SJean-Christophe PLAGNIOL-VILLARD /* Select a logical device */
66318c0b90SJean-Christophe PLAGNIOL-VILLARD #define ALI_SELDEV(dev) \
67318c0b90SJean-Christophe PLAGNIOL-VILLARD ali_write(0x07, dev)
68318c0b90SJean-Christophe PLAGNIOL-VILLARD
69318c0b90SJean-Christophe PLAGNIOL-VILLARD
ali512x_init(void)70318c0b90SJean-Christophe PLAGNIOL-VILLARD void ali512x_init(void)
71318c0b90SJean-Christophe PLAGNIOL-VILLARD {
72318c0b90SJean-Christophe PLAGNIOL-VILLARD ALI_OPEN();
73318c0b90SJean-Christophe PLAGNIOL-VILLARD
74318c0b90SJean-Christophe PLAGNIOL-VILLARD ali_write(0x02, 0x01); /* soft reset */
75318c0b90SJean-Christophe PLAGNIOL-VILLARD ali_write(0x03, 0x03); /* disable access to CIOs */
76318c0b90SJean-Christophe PLAGNIOL-VILLARD ali_write(0x22, 0x00); /* disable direct powerdown */
77318c0b90SJean-Christophe PLAGNIOL-VILLARD ali_write(0x23, 0x00); /* disable auto powerdown */
78318c0b90SJean-Christophe PLAGNIOL-VILLARD ali_write(0x24, 0x00); /* IR 8 is active hi, pin26 is PDIR */
79318c0b90SJean-Christophe PLAGNIOL-VILLARD
80318c0b90SJean-Christophe PLAGNIOL-VILLARD ALI_CLOSE();
81318c0b90SJean-Christophe PLAGNIOL-VILLARD }
82318c0b90SJean-Christophe PLAGNIOL-VILLARD
ali512x_set_fdc(int enabled,u16 io,u8 irq,u8 dma_channel)83318c0b90SJean-Christophe PLAGNIOL-VILLARD void ali512x_set_fdc(int enabled, u16 io, u8 irq, u8 dma_channel)
84318c0b90SJean-Christophe PLAGNIOL-VILLARD {
85318c0b90SJean-Christophe PLAGNIOL-VILLARD ALI_OPEN();
86318c0b90SJean-Christophe PLAGNIOL-VILLARD ALI_SELDEV(0);
87318c0b90SJean-Christophe PLAGNIOL-VILLARD
88318c0b90SJean-Christophe PLAGNIOL-VILLARD ali_write(0x30, enabled?1:0);
89318c0b90SJean-Christophe PLAGNIOL-VILLARD if (enabled) {
90318c0b90SJean-Christophe PLAGNIOL-VILLARD ali_write(0x60, io >> 8);
91318c0b90SJean-Christophe PLAGNIOL-VILLARD ali_write(0x61, io & 0xff);
92318c0b90SJean-Christophe PLAGNIOL-VILLARD ali_write(0x70, irq);
93318c0b90SJean-Christophe PLAGNIOL-VILLARD ali_write(0x74, dma_channel);
94318c0b90SJean-Christophe PLAGNIOL-VILLARD
95318c0b90SJean-Christophe PLAGNIOL-VILLARD /* AT mode, no drive swap */
96318c0b90SJean-Christophe PLAGNIOL-VILLARD ali_write(0xf0, 0x08);
97318c0b90SJean-Christophe PLAGNIOL-VILLARD ali_write(0xf1, 0x00);
98318c0b90SJean-Christophe PLAGNIOL-VILLARD ali_write(0xf2, 0xff);
99318c0b90SJean-Christophe PLAGNIOL-VILLARD ali_write(0xf4, 0x00);
100318c0b90SJean-Christophe PLAGNIOL-VILLARD }
101318c0b90SJean-Christophe PLAGNIOL-VILLARD ALI_CLOSE();
102318c0b90SJean-Christophe PLAGNIOL-VILLARD }
103318c0b90SJean-Christophe PLAGNIOL-VILLARD
104318c0b90SJean-Christophe PLAGNIOL-VILLARD
ali512x_set_pp(int enabled,u16 io,u8 irq,u8 dma_channel)105318c0b90SJean-Christophe PLAGNIOL-VILLARD void ali512x_set_pp(int enabled, u16 io, u8 irq, u8 dma_channel)
106318c0b90SJean-Christophe PLAGNIOL-VILLARD {
107318c0b90SJean-Christophe PLAGNIOL-VILLARD ALI_OPEN();
108318c0b90SJean-Christophe PLAGNIOL-VILLARD ALI_SELDEV(3);
109318c0b90SJean-Christophe PLAGNIOL-VILLARD
110318c0b90SJean-Christophe PLAGNIOL-VILLARD ali_write(0x30, enabled?1:0);
111318c0b90SJean-Christophe PLAGNIOL-VILLARD if (enabled) {
112318c0b90SJean-Christophe PLAGNIOL-VILLARD ali_write(0x60, io >> 8);
113318c0b90SJean-Christophe PLAGNIOL-VILLARD ali_write(0x61, io & 0xff);
114318c0b90SJean-Christophe PLAGNIOL-VILLARD ali_write(0x70, irq);
115318c0b90SJean-Christophe PLAGNIOL-VILLARD ali_write(0x74, dma_channel);
116318c0b90SJean-Christophe PLAGNIOL-VILLARD
117318c0b90SJean-Christophe PLAGNIOL-VILLARD /* mode: EPP 1.9, ECP FIFO threshold = 7, IRQ active low */
118318c0b90SJean-Christophe PLAGNIOL-VILLARD ali_write(0xf0, 0xbc);
119318c0b90SJean-Christophe PLAGNIOL-VILLARD /* 12 MHz, Burst DMA in ECP */
120318c0b90SJean-Christophe PLAGNIOL-VILLARD ali_write(0xf1, 0x05);
121318c0b90SJean-Christophe PLAGNIOL-VILLARD }
122318c0b90SJean-Christophe PLAGNIOL-VILLARD ALI_CLOSE();
123318c0b90SJean-Christophe PLAGNIOL-VILLARD
124318c0b90SJean-Christophe PLAGNIOL-VILLARD }
125318c0b90SJean-Christophe PLAGNIOL-VILLARD
ali512x_set_uart(int enabled,int index,u16 io,u8 irq)126318c0b90SJean-Christophe PLAGNIOL-VILLARD void ali512x_set_uart(int enabled, int index, u16 io, u8 irq)
127318c0b90SJean-Christophe PLAGNIOL-VILLARD {
128318c0b90SJean-Christophe PLAGNIOL-VILLARD ALI_OPEN();
129318c0b90SJean-Christophe PLAGNIOL-VILLARD ALI_SELDEV(index?5:4);
130318c0b90SJean-Christophe PLAGNIOL-VILLARD
131318c0b90SJean-Christophe PLAGNIOL-VILLARD ali_write(0x30, enabled?1:0);
132318c0b90SJean-Christophe PLAGNIOL-VILLARD if (enabled) {
133318c0b90SJean-Christophe PLAGNIOL-VILLARD ali_write(0x60, io >> 8);
134318c0b90SJean-Christophe PLAGNIOL-VILLARD ali_write(0x61, io & 0xff);
135318c0b90SJean-Christophe PLAGNIOL-VILLARD ali_write(0x70, irq);
136318c0b90SJean-Christophe PLAGNIOL-VILLARD
137318c0b90SJean-Christophe PLAGNIOL-VILLARD ali_write(0xf0, 0x00);
138318c0b90SJean-Christophe PLAGNIOL-VILLARD ali_write(0xf1, 0x00);
139318c0b90SJean-Christophe PLAGNIOL-VILLARD
140318c0b90SJean-Christophe PLAGNIOL-VILLARD /* huh? write 0xf2 twice - a typo in rolo
141318c0b90SJean-Christophe PLAGNIOL-VILLARD * or some secret ali errata? Who knows?
142318c0b90SJean-Christophe PLAGNIOL-VILLARD */
143318c0b90SJean-Christophe PLAGNIOL-VILLARD if (index) {
144318c0b90SJean-Christophe PLAGNIOL-VILLARD ali_write(0xf2, 0x00);
145318c0b90SJean-Christophe PLAGNIOL-VILLARD }
146318c0b90SJean-Christophe PLAGNIOL-VILLARD ali_write(0xf2, 0x0c);
147318c0b90SJean-Christophe PLAGNIOL-VILLARD }
148318c0b90SJean-Christophe PLAGNIOL-VILLARD ALI_CLOSE();
149318c0b90SJean-Christophe PLAGNIOL-VILLARD
150318c0b90SJean-Christophe PLAGNIOL-VILLARD }
151318c0b90SJean-Christophe PLAGNIOL-VILLARD
ali512x_set_uart2_irda(int enabled)152318c0b90SJean-Christophe PLAGNIOL-VILLARD void ali512x_set_uart2_irda(int enabled)
153318c0b90SJean-Christophe PLAGNIOL-VILLARD {
154318c0b90SJean-Christophe PLAGNIOL-VILLARD ALI_OPEN();
155318c0b90SJean-Christophe PLAGNIOL-VILLARD ALI_SELDEV(5);
156318c0b90SJean-Christophe PLAGNIOL-VILLARD
157318c0b90SJean-Christophe PLAGNIOL-VILLARD ali_write(0xf1, enabled?0x48:0x00); /* fullduplex IrDa */
158318c0b90SJean-Christophe PLAGNIOL-VILLARD ALI_CLOSE();
159318c0b90SJean-Christophe PLAGNIOL-VILLARD
160318c0b90SJean-Christophe PLAGNIOL-VILLARD }
161318c0b90SJean-Christophe PLAGNIOL-VILLARD
ali512x_set_rtc(int enabled,u16 io,u8 irq)162318c0b90SJean-Christophe PLAGNIOL-VILLARD void ali512x_set_rtc(int enabled, u16 io, u8 irq)
163318c0b90SJean-Christophe PLAGNIOL-VILLARD {
164318c0b90SJean-Christophe PLAGNIOL-VILLARD ALI_OPEN();
165318c0b90SJean-Christophe PLAGNIOL-VILLARD ALI_SELDEV(6);
166318c0b90SJean-Christophe PLAGNIOL-VILLARD
167318c0b90SJean-Christophe PLAGNIOL-VILLARD ali_write(0x30, enabled?1:0);
168318c0b90SJean-Christophe PLAGNIOL-VILLARD if (enabled) {
169318c0b90SJean-Christophe PLAGNIOL-VILLARD ali_write(0x60, io >> 8);
170318c0b90SJean-Christophe PLAGNIOL-VILLARD ali_write(0x61, io & 0xff);
171318c0b90SJean-Christophe PLAGNIOL-VILLARD ali_write(0x70, irq);
172318c0b90SJean-Christophe PLAGNIOL-VILLARD
173318c0b90SJean-Christophe PLAGNIOL-VILLARD ali_write(0xf0, 0x00);
174318c0b90SJean-Christophe PLAGNIOL-VILLARD }
175318c0b90SJean-Christophe PLAGNIOL-VILLARD ALI_CLOSE();
176318c0b90SJean-Christophe PLAGNIOL-VILLARD }
177318c0b90SJean-Christophe PLAGNIOL-VILLARD
ali512x_set_kbc(int enabled,u8 kbc_irq,u8 mouse_irq)178318c0b90SJean-Christophe PLAGNIOL-VILLARD void ali512x_set_kbc(int enabled, u8 kbc_irq, u8 mouse_irq)
179318c0b90SJean-Christophe PLAGNIOL-VILLARD {
180318c0b90SJean-Christophe PLAGNIOL-VILLARD ALI_OPEN();
181318c0b90SJean-Christophe PLAGNIOL-VILLARD ALI_SELDEV(7);
182318c0b90SJean-Christophe PLAGNIOL-VILLARD
183318c0b90SJean-Christophe PLAGNIOL-VILLARD ali_write(0x30, enabled?1:0);
184318c0b90SJean-Christophe PLAGNIOL-VILLARD if (enabled) {
185318c0b90SJean-Christophe PLAGNIOL-VILLARD ali_write(0x70, kbc_irq);
186318c0b90SJean-Christophe PLAGNIOL-VILLARD ali_write(0x72, mouse_irq);
187318c0b90SJean-Christophe PLAGNIOL-VILLARD
188318c0b90SJean-Christophe PLAGNIOL-VILLARD ali_write(0xf0, 0x00);
189318c0b90SJean-Christophe PLAGNIOL-VILLARD }
190318c0b90SJean-Christophe PLAGNIOL-VILLARD ALI_CLOSE();
191318c0b90SJean-Christophe PLAGNIOL-VILLARD }
192318c0b90SJean-Christophe PLAGNIOL-VILLARD
193318c0b90SJean-Christophe PLAGNIOL-VILLARD
194318c0b90SJean-Christophe PLAGNIOL-VILLARD /* Common I/O
195318c0b90SJean-Christophe PLAGNIOL-VILLARD *
196318c0b90SJean-Christophe PLAGNIOL-VILLARD * (This descripotsion is base on several incompete sources
197318c0b90SJean-Christophe PLAGNIOL-VILLARD * since I have not been able to obtain any datasheet for the device
198318c0b90SJean-Christophe PLAGNIOL-VILLARD * there may be some mis-understandings burried in here.
199318c0b90SJean-Christophe PLAGNIOL-VILLARD * -- Daniel daniel@omicron.se)
200318c0b90SJean-Christophe PLAGNIOL-VILLARD *
201318c0b90SJean-Christophe PLAGNIOL-VILLARD * There are 22 CIO pins numbered
202318c0b90SJean-Christophe PLAGNIOL-VILLARD * 10-17
203318c0b90SJean-Christophe PLAGNIOL-VILLARD * 20-25
204318c0b90SJean-Christophe PLAGNIOL-VILLARD * 30-37
205318c0b90SJean-Christophe PLAGNIOL-VILLARD *
206318c0b90SJean-Christophe PLAGNIOL-VILLARD * 20-24 are dedicated CIO pins, the other 17 are muliplexed with
207318c0b90SJean-Christophe PLAGNIOL-VILLARD * other functions.
208318c0b90SJean-Christophe PLAGNIOL-VILLARD *
209318c0b90SJean-Christophe PLAGNIOL-VILLARD * Secondary
210318c0b90SJean-Christophe PLAGNIOL-VILLARD * CIO Pin Function Decription
211318c0b90SJean-Christophe PLAGNIOL-VILLARD * =======================================================
212318c0b90SJean-Christophe PLAGNIOL-VILLARD * CIO10 IRQIN1 Interrupt input 1?
213318c0b90SJean-Christophe PLAGNIOL-VILLARD * CIO11 IRQIN2 Interrupt input 2?
214318c0b90SJean-Christophe PLAGNIOL-VILLARD * CIO12 IRRX IrDa Receive
215318c0b90SJean-Christophe PLAGNIOL-VILLARD * CIO13 IRTX IrDa Transmit
216318c0b90SJean-Christophe PLAGNIOL-VILLARD * CIO14 P21 KBC P21 fucntion
217318c0b90SJean-Christophe PLAGNIOL-VILLARD * CIO15 P20 KBC P21 fucntion
218318c0b90SJean-Christophe PLAGNIOL-VILLARD * CIO16 I2C_CLK I2C Clock
219318c0b90SJean-Christophe PLAGNIOL-VILLARD * CIO17 I2C_DAT I2C Data
220318c0b90SJean-Christophe PLAGNIOL-VILLARD *
221318c0b90SJean-Christophe PLAGNIOL-VILLARD * CIO20 -
222318c0b90SJean-Christophe PLAGNIOL-VILLARD * CIO21 -
223318c0b90SJean-Christophe PLAGNIOL-VILLARD * CIO22 -
224318c0b90SJean-Christophe PLAGNIOL-VILLARD * CIO23 -
225318c0b90SJean-Christophe PLAGNIOL-VILLARD * CIO24 -
226318c0b90SJean-Christophe PLAGNIOL-VILLARD * CIO25 LOCK Keylock
227318c0b90SJean-Christophe PLAGNIOL-VILLARD *
228318c0b90SJean-Christophe PLAGNIOL-VILLARD * CIO30 KBC_CLK Keybaord Clock
229318c0b90SJean-Christophe PLAGNIOL-VILLARD * CIO31 CS0J General Chip Select decoder CS0J
230318c0b90SJean-Christophe PLAGNIOL-VILLARD * CIO32 CS1J General Chip Select decoder CS1J
231318c0b90SJean-Christophe PLAGNIOL-VILLARD * CIO33 ALT_KCLK Alternative Keyboard Clock
232318c0b90SJean-Christophe PLAGNIOL-VILLARD * CIO34 ALT_KDAT Alternative Keyboard Data
233318c0b90SJean-Christophe PLAGNIOL-VILLARD * CIO35 ALT_MCLK Alternative Mouse Clock
234318c0b90SJean-Christophe PLAGNIOL-VILLARD * CIO36 ALT_MDAT Alternative Mouse Data
235318c0b90SJean-Christophe PLAGNIOL-VILLARD * CIO37 ALT_KBC Alternative KBC select
236318c0b90SJean-Christophe PLAGNIOL-VILLARD *
237318c0b90SJean-Christophe PLAGNIOL-VILLARD * The CIO use an indirect address scheme.
238318c0b90SJean-Christophe PLAGNIOL-VILLARD *
239318c0b90SJean-Christophe PLAGNIOL-VILLARD * Reigster 3 in the SIO is used to select the index and data
240318c0b90SJean-Christophe PLAGNIOL-VILLARD * port addresses where the CIO I/O registers show up.
241318c0b90SJean-Christophe PLAGNIOL-VILLARD * The function selection registers are accessible under
242318c0b90SJean-Christophe PLAGNIOL-VILLARD * function SIO 8.
243318c0b90SJean-Christophe PLAGNIOL-VILLARD *
244318c0b90SJean-Christophe PLAGNIOL-VILLARD * SIO reigster 3 (CIO Address Selection) bit definitions:
245318c0b90SJean-Christophe PLAGNIOL-VILLARD * bit 7 CIO index and data registers enabled
246318c0b90SJean-Christophe PLAGNIOL-VILLARD * bit 1-0 CIO indirect registers port address select
247318c0b90SJean-Christophe PLAGNIOL-VILLARD * 0 index = 0xE0 data = 0xE1
248318c0b90SJean-Christophe PLAGNIOL-VILLARD * 1 index = 0xE2 data = 0xE3
249318c0b90SJean-Christophe PLAGNIOL-VILLARD * 2 index = 0xE4 data = 0xE5
250318c0b90SJean-Christophe PLAGNIOL-VILLARD * 3 index = 0xEA data = 0xEB
251318c0b90SJean-Christophe PLAGNIOL-VILLARD *
252318c0b90SJean-Christophe PLAGNIOL-VILLARD * There are three CIO I/O register accessed via CIO index port and CIO data port
253318c0b90SJean-Christophe PLAGNIOL-VILLARD * 0x01 CIO 10-17 data
254318c0b90SJean-Christophe PLAGNIOL-VILLARD * 0x02 CIO 20-25 data (bits 7-6 unused)
255318c0b90SJean-Christophe PLAGNIOL-VILLARD * 0x03 CIO 30-37 data
256318c0b90SJean-Christophe PLAGNIOL-VILLARD *
257318c0b90SJean-Christophe PLAGNIOL-VILLARD *
258318c0b90SJean-Christophe PLAGNIOL-VILLARD * The pin function is accessed through normal
259318c0b90SJean-Christophe PLAGNIOL-VILLARD * SIO registers, each register have the same format:
260318c0b90SJean-Christophe PLAGNIOL-VILLARD *
261318c0b90SJean-Christophe PLAGNIOL-VILLARD * Bit Function Value
262318c0b90SJean-Christophe PLAGNIOL-VILLARD * 0 Input/output 1=input
263318c0b90SJean-Christophe PLAGNIOL-VILLARD * 1 Polarity of signal 1=inverted
264318c0b90SJean-Christophe PLAGNIOL-VILLARD * 2 Unused ??
265318c0b90SJean-Christophe PLAGNIOL-VILLARD * 3 Function (normal or special) 1=special
266318c0b90SJean-Christophe PLAGNIOL-VILLARD * 7-4 Unused
267318c0b90SJean-Christophe PLAGNIOL-VILLARD *
268318c0b90SJean-Christophe PLAGNIOL-VILLARD * SIO REG
269318c0b90SJean-Christophe PLAGNIOL-VILLARD * 0xe0 CIO 10 Config
270318c0b90SJean-Christophe PLAGNIOL-VILLARD * 0xe1 CIO 11 Config
271318c0b90SJean-Christophe PLAGNIOL-VILLARD * 0xe2 CIO 12 Config
272318c0b90SJean-Christophe PLAGNIOL-VILLARD * 0xe3 CIO 13 Config
273318c0b90SJean-Christophe PLAGNIOL-VILLARD * 0xe4 CIO 14 Config
274318c0b90SJean-Christophe PLAGNIOL-VILLARD * 0xe5 CIO 15 Config
275318c0b90SJean-Christophe PLAGNIOL-VILLARD * 0xe6 CIO 16 Config
276318c0b90SJean-Christophe PLAGNIOL-VILLARD * 0xe7 CIO 16 Config
277318c0b90SJean-Christophe PLAGNIOL-VILLARD *
278318c0b90SJean-Christophe PLAGNIOL-VILLARD * 0xe8 CIO 20 Config
279318c0b90SJean-Christophe PLAGNIOL-VILLARD * 0xe9 CIO 21 Config
280318c0b90SJean-Christophe PLAGNIOL-VILLARD * 0xea CIO 22 Config
281318c0b90SJean-Christophe PLAGNIOL-VILLARD * 0xeb CIO 23 Config
282318c0b90SJean-Christophe PLAGNIOL-VILLARD * 0xec CIO 24 Config
283318c0b90SJean-Christophe PLAGNIOL-VILLARD * 0xed CIO 25 Config
284318c0b90SJean-Christophe PLAGNIOL-VILLARD *
285318c0b90SJean-Christophe PLAGNIOL-VILLARD * 0xf5 CIO 30 Config
286318c0b90SJean-Christophe PLAGNIOL-VILLARD * 0xf6 CIO 31 Config
287318c0b90SJean-Christophe PLAGNIOL-VILLARD * 0xf7 CIO 32 Config
288318c0b90SJean-Christophe PLAGNIOL-VILLARD * 0xf8 CIO 33 Config
289318c0b90SJean-Christophe PLAGNIOL-VILLARD * 0xf9 CIO 34 Config
290318c0b90SJean-Christophe PLAGNIOL-VILLARD * 0xfa CIO 35 Config
291318c0b90SJean-Christophe PLAGNIOL-VILLARD * 0xfb CIO 36 Config
292318c0b90SJean-Christophe PLAGNIOL-VILLARD * 0xfc CIO 37 Config
293318c0b90SJean-Christophe PLAGNIOL-VILLARD *
294318c0b90SJean-Christophe PLAGNIOL-VILLARD */
295318c0b90SJean-Christophe PLAGNIOL-VILLARD
296318c0b90SJean-Christophe PLAGNIOL-VILLARD #define ALI_CIO_PORT_SEL 0x83
297318c0b90SJean-Christophe PLAGNIOL-VILLARD #define ALI_CIO_INDEX 0xea
298318c0b90SJean-Christophe PLAGNIOL-VILLARD #define ALI_CIO_DATA 0xeb
299318c0b90SJean-Christophe PLAGNIOL-VILLARD
ali512x_set_cio(int enabled)300318c0b90SJean-Christophe PLAGNIOL-VILLARD void ali512x_set_cio(int enabled)
301318c0b90SJean-Christophe PLAGNIOL-VILLARD {
302318c0b90SJean-Christophe PLAGNIOL-VILLARD int i;
303318c0b90SJean-Christophe PLAGNIOL-VILLARD
304318c0b90SJean-Christophe PLAGNIOL-VILLARD ALI_OPEN();
305318c0b90SJean-Christophe PLAGNIOL-VILLARD
306318c0b90SJean-Christophe PLAGNIOL-VILLARD if (enabled) {
307318c0b90SJean-Christophe PLAGNIOL-VILLARD ali_write(0x3, ALI_CIO_PORT_SEL); /* Enable CIO data register */
308318c0b90SJean-Christophe PLAGNIOL-VILLARD } else {
309318c0b90SJean-Christophe PLAGNIOL-VILLARD ali_write(0x3, ALI_CIO_PORT_SEL & ~0x80);
310318c0b90SJean-Christophe PLAGNIOL-VILLARD }
311318c0b90SJean-Christophe PLAGNIOL-VILLARD
312318c0b90SJean-Christophe PLAGNIOL-VILLARD ALI_SELDEV(8);
313318c0b90SJean-Christophe PLAGNIOL-VILLARD
314318c0b90SJean-Christophe PLAGNIOL-VILLARD ali_write(0x30, enabled?1:0);
315318c0b90SJean-Christophe PLAGNIOL-VILLARD
316318c0b90SJean-Christophe PLAGNIOL-VILLARD /* set all pins to input to start with */
317318c0b90SJean-Christophe PLAGNIOL-VILLARD for (i=0xe0;i<0xee;i++) {
318318c0b90SJean-Christophe PLAGNIOL-VILLARD ali_write(i, 1);
319318c0b90SJean-Christophe PLAGNIOL-VILLARD }
320318c0b90SJean-Christophe PLAGNIOL-VILLARD
321318c0b90SJean-Christophe PLAGNIOL-VILLARD for (i=0xf5;i<0xfe;i++) {
322318c0b90SJean-Christophe PLAGNIOL-VILLARD ali_write(i, 1);
323318c0b90SJean-Christophe PLAGNIOL-VILLARD }
324318c0b90SJean-Christophe PLAGNIOL-VILLARD
325318c0b90SJean-Christophe PLAGNIOL-VILLARD ALI_CLOSE();
326318c0b90SJean-Christophe PLAGNIOL-VILLARD }
327318c0b90SJean-Christophe PLAGNIOL-VILLARD
328318c0b90SJean-Christophe PLAGNIOL-VILLARD
ali512x_cio_function(int pin,int special,int inv,int input)329318c0b90SJean-Christophe PLAGNIOL-VILLARD void ali512x_cio_function(int pin, int special, int inv, int input)
330318c0b90SJean-Christophe PLAGNIOL-VILLARD {
331318c0b90SJean-Christophe PLAGNIOL-VILLARD u8 data;
332318c0b90SJean-Christophe PLAGNIOL-VILLARD u8 addr;
333318c0b90SJean-Christophe PLAGNIOL-VILLARD
334318c0b90SJean-Christophe PLAGNIOL-VILLARD /* valid pins are 10-17, 20-25 and 30-37 */
335318c0b90SJean-Christophe PLAGNIOL-VILLARD if (pin >= 10 && pin <= 17) {
336318c0b90SJean-Christophe PLAGNIOL-VILLARD addr = 0xe0+(pin&7);
337318c0b90SJean-Christophe PLAGNIOL-VILLARD } else if (pin >= 20 && pin <= 25) {
338318c0b90SJean-Christophe PLAGNIOL-VILLARD addr = 0xe8+(pin&7);
339318c0b90SJean-Christophe PLAGNIOL-VILLARD } else if (pin >= 30 && pin <= 37) {
340318c0b90SJean-Christophe PLAGNIOL-VILLARD addr = 0xf5+(pin&7);
341318c0b90SJean-Christophe PLAGNIOL-VILLARD } else {
342318c0b90SJean-Christophe PLAGNIOL-VILLARD return;
343318c0b90SJean-Christophe PLAGNIOL-VILLARD }
344318c0b90SJean-Christophe PLAGNIOL-VILLARD
345318c0b90SJean-Christophe PLAGNIOL-VILLARD ALI_OPEN();
346318c0b90SJean-Christophe PLAGNIOL-VILLARD
347318c0b90SJean-Christophe PLAGNIOL-VILLARD ALI_SELDEV(8);
348318c0b90SJean-Christophe PLAGNIOL-VILLARD
349318c0b90SJean-Christophe PLAGNIOL-VILLARD
350318c0b90SJean-Christophe PLAGNIOL-VILLARD data=0xf4;
351318c0b90SJean-Christophe PLAGNIOL-VILLARD if (special) {
352318c0b90SJean-Christophe PLAGNIOL-VILLARD data |= 0x08;
353318c0b90SJean-Christophe PLAGNIOL-VILLARD } else {
354318c0b90SJean-Christophe PLAGNIOL-VILLARD if (inv) {
355318c0b90SJean-Christophe PLAGNIOL-VILLARD data |= 0x02;
356318c0b90SJean-Christophe PLAGNIOL-VILLARD }
357318c0b90SJean-Christophe PLAGNIOL-VILLARD if (input) {
358318c0b90SJean-Christophe PLAGNIOL-VILLARD data |= 0x01;
359318c0b90SJean-Christophe PLAGNIOL-VILLARD }
360318c0b90SJean-Christophe PLAGNIOL-VILLARD }
361318c0b90SJean-Christophe PLAGNIOL-VILLARD
362318c0b90SJean-Christophe PLAGNIOL-VILLARD ali_write(addr, data);
363318c0b90SJean-Christophe PLAGNIOL-VILLARD
364318c0b90SJean-Christophe PLAGNIOL-VILLARD ALI_CLOSE();
365318c0b90SJean-Christophe PLAGNIOL-VILLARD }
366318c0b90SJean-Christophe PLAGNIOL-VILLARD
ali512x_cio_out(int pin,int value)367318c0b90SJean-Christophe PLAGNIOL-VILLARD void ali512x_cio_out(int pin, int value)
368318c0b90SJean-Christophe PLAGNIOL-VILLARD {
369318c0b90SJean-Christophe PLAGNIOL-VILLARD u8 reg;
370318c0b90SJean-Christophe PLAGNIOL-VILLARD u8 data;
371318c0b90SJean-Christophe PLAGNIOL-VILLARD u8 bit;
372318c0b90SJean-Christophe PLAGNIOL-VILLARD
373318c0b90SJean-Christophe PLAGNIOL-VILLARD reg = pin/10;
374318c0b90SJean-Christophe PLAGNIOL-VILLARD bit = 1 << (pin%10);
375318c0b90SJean-Christophe PLAGNIOL-VILLARD
376318c0b90SJean-Christophe PLAGNIOL-VILLARD
377318c0b90SJean-Christophe PLAGNIOL-VILLARD outb(reg, ALI_CIO_INDEX); /* select I/O register */
378318c0b90SJean-Christophe PLAGNIOL-VILLARD data = inb(ALI_CIO_DATA);
379318c0b90SJean-Christophe PLAGNIOL-VILLARD if (value) {
380318c0b90SJean-Christophe PLAGNIOL-VILLARD data |= bit;
381318c0b90SJean-Christophe PLAGNIOL-VILLARD } else {
382318c0b90SJean-Christophe PLAGNIOL-VILLARD data &= ~bit;
383318c0b90SJean-Christophe PLAGNIOL-VILLARD }
384318c0b90SJean-Christophe PLAGNIOL-VILLARD outb(data, ALI_CIO_DATA);
385318c0b90SJean-Christophe PLAGNIOL-VILLARD }
386318c0b90SJean-Christophe PLAGNIOL-VILLARD
ali512x_cio_in(int pin)387318c0b90SJean-Christophe PLAGNIOL-VILLARD int ali512x_cio_in(int pin)
388318c0b90SJean-Christophe PLAGNIOL-VILLARD {
389318c0b90SJean-Christophe PLAGNIOL-VILLARD u8 reg;
390318c0b90SJean-Christophe PLAGNIOL-VILLARD u8 data;
391318c0b90SJean-Christophe PLAGNIOL-VILLARD u8 bit;
392318c0b90SJean-Christophe PLAGNIOL-VILLARD
393318c0b90SJean-Christophe PLAGNIOL-VILLARD /* valid pins are 10-17, 20-25 and 30-37 */
394318c0b90SJean-Christophe PLAGNIOL-VILLARD reg = pin/10;
395318c0b90SJean-Christophe PLAGNIOL-VILLARD bit = 1 << (pin%10);
396318c0b90SJean-Christophe PLAGNIOL-VILLARD
397318c0b90SJean-Christophe PLAGNIOL-VILLARD
398318c0b90SJean-Christophe PLAGNIOL-VILLARD outb(reg, ALI_CIO_INDEX); /* select I/O register */
399318c0b90SJean-Christophe PLAGNIOL-VILLARD data = inb(ALI_CIO_DATA);
400318c0b90SJean-Christophe PLAGNIOL-VILLARD
401318c0b90SJean-Christophe PLAGNIOL-VILLARD return data & bit;
402318c0b90SJean-Christophe PLAGNIOL-VILLARD }
403