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Searched refs:pcie (Results 1 – 25 of 90) sorted by relevance

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/rk3399_rockchip-uboot/drivers/pci/
H A Dpcie_layerscape.c26 static unsigned int dbi_readl(struct ls_pcie *pcie, unsigned int offset) in dbi_readl() argument
28 return in_le32(pcie->dbi + offset); in dbi_readl()
31 static void dbi_writel(struct ls_pcie *pcie, unsigned int value, in dbi_writel() argument
34 out_le32(pcie->dbi + offset, value); in dbi_writel()
37 static unsigned int ctrl_readl(struct ls_pcie *pcie, unsigned int offset) in ctrl_readl() argument
39 if (pcie->big_endian) in ctrl_readl()
40 return in_be32(pcie->ctrl + offset); in ctrl_readl()
42 return in_le32(pcie->ctrl + offset); in ctrl_readl()
45 static void ctrl_writel(struct ls_pcie *pcie, unsigned int value, in ctrl_writel() argument
48 if (pcie->big_endian) in ctrl_writel()
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H A Dpci_mvebu.c107 static void mvebu_get_port_lane(struct mvebu_pcie *pcie, int pex_idx, in mvebu_get_port_lane() argument
115 pcie->port = port[pex_idx]; in mvebu_get_port_lane()
116 pcie->lane = lane[pex_idx]; in mvebu_get_port_lane()
142 static void mvebu_get_port_lane(struct mvebu_pcie *pcie, int pex_idx, in mvebu_get_port_lane() argument
152 pcie->port = port[pex_idx]; in mvebu_get_port_lane()
153 pcie->lane = lane[pex_idx]; in mvebu_get_port_lane()
167 static inline bool mvebu_pcie_link_up(struct mvebu_pcie *pcie) in mvebu_pcie_link_up() argument
170 val = readl(pcie->base + PCIE_STAT_OFF); in mvebu_pcie_link_up()
174 static void mvebu_pcie_set_local_bus_nr(struct mvebu_pcie *pcie, int busno) in mvebu_pcie_set_local_bus_nr() argument
178 stat = readl(pcie->base + PCIE_STAT_OFF); in mvebu_pcie_set_local_bus_nr()
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H A Dpci_tegra.c197 struct tegra_pcie *pcie; member
244 static void afi_writel(struct tegra_pcie *pcie, unsigned long value, in afi_writel() argument
247 writel(value, pcie->afi.start + offset); in afi_writel()
250 static unsigned long afi_readl(struct tegra_pcie *pcie, unsigned long offset) in afi_readl() argument
252 return readl(pcie->afi.start + offset); in afi_readl()
255 static void pads_writel(struct tegra_pcie *pcie, unsigned long value, in pads_writel() argument
258 writel(value, pcie->pads.start + offset); in pads_writel()
262 static unsigned long pads_readl(struct tegra_pcie *pcie, unsigned long offset) in pads_readl() argument
264 return readl(pcie->pads.start + offset); in pads_readl()
287 static int tegra_pcie_conf_address(struct tegra_pcie *pcie, pci_dev_t bdf, in tegra_pcie_conf_address() argument
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H A Dpcie_layerscape_fixup.c26 static int ls_pcie_next_lut_index(struct ls_pcie *pcie) in ls_pcie_next_lut_index() argument
28 if (pcie->next_lut_index < PCIE_LUT_ENTRY_COUNT) in ls_pcie_next_lut_index()
29 return pcie->next_lut_index++; in ls_pcie_next_lut_index()
45 static void lut_writel(struct ls_pcie *pcie, unsigned int value, in lut_writel() argument
48 if (pcie->big_endian) in lut_writel()
49 out_be32(pcie->lut + offset, value); in lut_writel()
51 out_le32(pcie->lut + offset, value); in lut_writel()
57 static void ls_pcie_lut_set_mapping(struct ls_pcie *pcie, int index, u32 devid, in ls_pcie_lut_set_mapping() argument
61 lut_writel(pcie, devid << 16, PCIE_LUT_UDR(index)); in ls_pcie_lut_set_mapping()
62 lut_writel(pcie, streamid | PCIE_LUT_ENABLE, PCIE_LUT_LDR(index)); in ls_pcie_lut_set_mapping()
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H A Dpcie_dw_mvebu.c142 static uintptr_t set_cfg_address(struct pcie_dw_mvebu *pcie, in set_cfg_address() argument
152 writel(0, pcie->ctrl_base + PCIE_ATU_VIEWPORT); in set_cfg_address()
154 if (PCI_BUS(d) == (pcie->first_busno + 1)) in set_cfg_address()
156 writel(PCIE_ATU_TYPE_CFG0, pcie->ctrl_base + PCIE_ATU_CR1); in set_cfg_address()
159 writel(PCIE_ATU_TYPE_CFG1, pcie->ctrl_base + PCIE_ATU_CR1); in set_cfg_address()
161 if (PCI_BUS(d) == pcie->first_busno) { in set_cfg_address()
163 va_address = (uintptr_t)pcie->ctrl_base; in set_cfg_address()
165 writel(d << 8, pcie->ctrl_base + PCIE_ATU_LOWER_TARGET); in set_cfg_address()
166 va_address = (uintptr_t)pcie->cfg_base; in set_cfg_address()
213 struct pcie_dw_mvebu *pcie = dev_get_priv(bus); in pcie_dw_mvebu_read_config() local
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H A Dpcie_xilinx.c37 static bool pcie_xilinx_link_up(struct xilinx_pcie *pcie) in pcie_xilinx_link_up() argument
39 uint32_t pscr = __raw_readl(pcie->cfg_base + XILINX_PCIE_REG_PSCR); in pcie_xilinx_link_up()
60 static int pcie_xilinx_config_address(struct xilinx_pcie *pcie, pci_dev_t bdf, in pcie_xilinx_config_address() argument
68 if ((bus > 0) && !pcie_xilinx_link_up(pcie)) in pcie_xilinx_config_address()
78 addr = pcie->cfg_base; in pcie_xilinx_config_address()
106 struct xilinx_pcie *pcie = dev_get_priv(bus); in pcie_xilinx_read_config() local
110 err = pcie_xilinx_config_address(pcie, bdf, offset, &address); in pcie_xilinx_read_config()
149 struct xilinx_pcie *pcie = dev_get_priv(bus); in pcie_xilinx_write_config() local
153 err = pcie_xilinx_config_address(pcie, bdf, offset, &address); in pcie_xilinx_write_config()
184 struct xilinx_pcie *pcie = dev_get_priv(dev); in pcie_xilinx_ofdata_to_platdata() local
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H A Dpcie_dw_rockchip.c486 static uintptr_t set_cfg_address(struct rk_pcie *pcie, in set_cfg_address() argument
489 int bus = PCI_BUS(d) - pcie->first_busno; in set_cfg_address()
495 va_address = (uintptr_t)pcie->dbi_base; in set_cfg_address()
517 rk_pcie_prog_outbound_atu_unroll(pcie, PCIE_ATU_REGION_INDEX1, in set_cfg_address()
518 atu_type, (u64)pcie->cfg_base, in set_cfg_address()
519 d << 8, pcie->cfg_size); in set_cfg_address()
521 va_address = (uintptr_t)pcie->cfg_base; in set_cfg_address()
533 struct rk_pcie *pcie = dev_get_priv(bus); in rockchip_pcie_rd_conf() local
540 if (!rk_pcie_addr_valid(bdf, pcie->first_busno)) { in rockchip_pcie_rd_conf()
546 va_address = set_cfg_address(pcie, bdf, offset); in rockchip_pcie_rd_conf()
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/rk3399_rockchip-uboot/arch/arm/dts/
H A Dtegra210-p2371-2180.dts24 pcie-controller@01003000 {
48 nvidia,lanes = "pcie-5", "pcie-6";
53 pcie-x1 {
54 nvidia,lanes = "pcie-0";
55 nvidia,function = "pcie-x1";
59 pcie-x4 {
60 nvidia,lanes = "pcie-1", "pcie-2",
61 "pcie-3", "pcie-4";
62 nvidia,function = "pcie-x4";
H A Darmada-xp-mv78460.dtsi107 pcie-controller {
108 compatible = "marvell,armada-xp-pcie";
153 pcie@1,0 {
164 marvell,pcie-port = <0>;
165 marvell,pcie-lane = <0>;
170 pcie@2,0 {
181 marvell,pcie-port = <0>;
182 marvell,pcie-lane = <1>;
187 pcie@3,0 {
198 marvell,pcie-port = <0>;
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H A Darmada-xp-mv78260.dtsi90 pcie-controller {
91 compatible = "marvell,armada-xp-pcie";
132 pcie@1,0 {
143 marvell,pcie-port = <0>;
144 marvell,pcie-lane = <0>;
149 pcie@2,0 {
160 marvell,pcie-port = <0>;
161 marvell,pcie-lane = <1>;
166 pcie@3,0 {
177 marvell,pcie-port = <0>;
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H A Darmada-385.dtsi79 pcie-controller {
80 compatible = "marvell,armada-370-pcie";
107 * pcie@4,0 is not available.
109 pcie@1,0 {
120 marvell,pcie-port = <0>;
121 marvell,pcie-lane = <0>;
127 pcie@2,0 {
138 marvell,pcie-port = <1>;
139 marvell,pcie-lane = <0>;
145 pcie@3,0 {
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H A Dfsl-ls2080a.dtsi93 pcie@3400000 {
94 compatible = "fsl,ls-pcie", "snps,dw-pcie";
108 pcie@3500000 {
109 compatible = "fsl,ls-pcie", "snps,dw-pcie";
123 pcie@3600000 {
124 compatible = "fsl,ls-pcie", "snps,dw-pcie";
138 pcie@3700000 {
139 compatible = "fsl,ls-pcie", "snps,dw-pcie";
H A Darmada-xp-mv78230.dtsi89 pcie-controller {
90 compatible = "marvell,armada-xp-pcie";
117 pcie@1,0 {
128 marvell,pcie-port = <0>;
129 marvell,pcie-lane = <0>;
134 pcie@2,0 {
145 marvell,pcie-port = <0>;
146 marvell,pcie-lane = <1>;
151 pcie@3,0 {
162 marvell,pcie-port = <0>;
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H A Darmada-380.dtsi74 pcie-controller {
75 compatible = "marvell,armada-370-pcie";
98 pcie@1,0 {
109 marvell,pcie-port = <0>;
110 marvell,pcie-lane = <0>;
116 pcie@2,0 {
127 marvell,pcie-port = <1>;
128 marvell,pcie-lane = <0>;
134 pcie@3,0 {
145 marvell,pcie-port = <2>;
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H A Drk3588.dtsi217 pcie3x4: pcie@fe150000 {
218 compatible = "rockchip,rk3588-pcie", "snps,dw-pcie";
247 phy-names = "pcie-phy";
255 reg-names = "pcie-dbi", "pcie-apb";
269 pcie3x2: pcie@fe160000 {
270 compatible = "rockchip,rk3588-pcie", "snps,dw-pcie";
299 phy-names = "pcie-phy";
307 reg-names = "pcie-dbi", "pcie-apb";
321 pcie2x1l0: pcie@fe170000 {
322 compatible = "rockchip,rk3588-pcie", "snps,dw-pcie";
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H A Dfsl-ls1046a.dtsi241 pcie@3400000 {
242 compatible = "fsl,ls-pcie", "snps,dw-pcie";
257 pcie@3500000 {
258 compatible = "fsl,ls-pcie", "snps,dw-pcie";
274 pcie@3600000 {
275 compatible = "fsl,ls-pcie", "snps,dw-pcie";
H A Dfsl-ls1043a.dtsi240 pcie@3400000 {
241 compatible = "fsl,ls-pcie", "snps,dw-pcie";
255 pcie@3500000 {
256 compatible = "fsl,ls-pcie", "snps,dw-pcie";
271 pcie@3600000 {
272 compatible = "fsl,ls-pcie", "snps,dw-pcie";
H A Dkeystone-k2e.dtsi89 pcie1: pcie@21020000 {
90 compatible = "ti,keystone-pcie","snps,dw-pcie";
92 clock-names = "pcie";
H A Darmada-cp110-slave.dtsi114 "cps-pcie_x11", "cps-pcie_x4", "cps-pcie-xor",
262 cps_pcie0: pcie@f4600000 {
263 compatible = "marvell,armada8k-pcie", "snps,dw-pcie";
288 cps_pcie1: pcie@f4620000 {
289 compatible = "marvell,armada8k-pcie", "snps,dw-pcie";
315 cps_pcie2: pcie@f4640000 {
316 compatible = "marvell,armada8k-pcie", "snps,dw-pcie";
H A Darmada-cp110-master.dtsi114 "cpm-pcie_x11", "cpm-pcie_x4", "cpm-pcie-xor",
292 cpm_pcie0: pcie@f2600000 {
293 compatible = "marvell,armada8k-pcie", "snps,dw-pcie";
317 cpm_pcie1: pcie@f2620000 {
318 compatible = "marvell,armada8k-pcie", "snps,dw-pcie";
343 cpm_pcie2: pcie@f2640000 {
344 compatible = "marvell,armada8k-pcie", "snps,dw-pcie";
H A Dtegra124-cei-tk1-som.dts32 pcie-controller@01003000 {
290 pcie {
291 nvidia,lanes = "pcie-0", "pcie-1", "pcie-2", "pcie-3",
292 "pcie-4";
293 nvidia,function = "pcie";
H A Dtegra124-jetson-tk1.dts32 pcie-controller@01003000 {
284 nvidia,lanes = "pcie-0", "pcie-1";
289 pcie {
290 nvidia,lanes = "pcie-2", "pcie-3",
291 "pcie-4";
292 nvidia,function = "pcie";
/rk3399_rockchip-uboot/doc/device-tree-bindings/pci/
H A Darmada8k-pcie.txt7 - compatible : should be "marvell,armada8k-pcie", "snps,dw-pcie".
8 - reg: base addresses and lengths of the pcie control and global control registers.
10 points to the pcie configuration registers as mentioned in dw-pcie dt bindings in the link below.
15 "Documentation/devicetree/bindings/pci/designware-pcie.txt"
19 - phys : phandle to phy node associated with pcie controller.
20 - phy-names : must be "pcie-phy"
25 cpm_pcie0: pcie@f2600000 {
26 compatible = "marvell,armada8k-pcie", "snps,dw-pcie";
/rk3399_rockchip-uboot/board/freescale/common/
H A Dns_access.c48 void set_pcie_ns_access(int pcie, u16 val) in set_pcie_ns_access() argument
50 switch (pcie) { in set_pcie_ns_access()
70 debug("The PCIE%d doesn't exist!\n", pcie); in set_pcie_ns_access()
/rk3399_rockchip-uboot/board/armltd/vexpress64/
H A DMakefile9 obj-$(CONFIG_TARGET_VEXPRESS64_JUNO) += pcie.o

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