1*39a230aaSStefan Roese/* 2*39a230aaSStefan Roese * Device Tree Include file for Marvell Armada 380 SoC. 3*39a230aaSStefan Roese * 4*39a230aaSStefan Roese * Copyright (C) 2014 Marvell 5*39a230aaSStefan Roese * 6*39a230aaSStefan Roese * Lior Amsalem <alior@marvell.com> 7*39a230aaSStefan Roese * Gregory CLEMENT <gregory.clement@free-electrons.com> 8*39a230aaSStefan Roese * Thomas Petazzoni <thomas.petazzoni@free-electrons.com> 9*39a230aaSStefan Roese * 10*39a230aaSStefan Roese * This file is dual-licensed: you can use it either under the terms 11*39a230aaSStefan Roese * of the GPL or the X11 license, at your option. Note that this dual 12*39a230aaSStefan Roese * licensing only applies to this file, and not this project as a 13*39a230aaSStefan Roese * whole. 14*39a230aaSStefan Roese * 15*39a230aaSStefan Roese * a) This file is free software; you can redistribute it and/or 16*39a230aaSStefan Roese * modify it under the terms of the GNU General Public License as 17*39a230aaSStefan Roese * published by the Free Software Foundation; either version 2 of the 18*39a230aaSStefan Roese * License, or (at your option) any later version. 19*39a230aaSStefan Roese * 20*39a230aaSStefan Roese * This file is distributed in the hope that it will be useful 21*39a230aaSStefan Roese * but WITHOUT ANY WARRANTY; without even the implied warranty of 22*39a230aaSStefan Roese * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 23*39a230aaSStefan Roese * GNU General Public License for more details. 24*39a230aaSStefan Roese * 25*39a230aaSStefan Roese * Or, alternatively 26*39a230aaSStefan Roese * 27*39a230aaSStefan Roese * b) Permission is hereby granted, free of charge, to any person 28*39a230aaSStefan Roese * obtaining a copy of this software and associated documentation 29*39a230aaSStefan Roese * files (the "Software"), to deal in the Software without 30*39a230aaSStefan Roese * restriction, including without limitation the rights to use 31*39a230aaSStefan Roese * copy, modify, merge, publish, distribute, sublicense, and/or 32*39a230aaSStefan Roese * sell copies of the Software, and to permit persons to whom the 33*39a230aaSStefan Roese * Software is furnished to do so, subject to the following 34*39a230aaSStefan Roese * conditions: 35*39a230aaSStefan Roese * 36*39a230aaSStefan Roese * The above copyright notice and this permission notice shall be 37*39a230aaSStefan Roese * included in all copies or substantial portions of the Software. 38*39a230aaSStefan Roese * 39*39a230aaSStefan Roese * THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND 40*39a230aaSStefan Roese * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES 41*39a230aaSStefan Roese * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 42*39a230aaSStefan Roese * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT 43*39a230aaSStefan Roese * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY 44*39a230aaSStefan Roese * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 45*39a230aaSStefan Roese * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 46*39a230aaSStefan Roese * OTHER DEALINGS IN THE SOFTWARE. 47*39a230aaSStefan Roese */ 48*39a230aaSStefan Roese 49*39a230aaSStefan Roese#include "armada-38x.dtsi" 50*39a230aaSStefan Roese 51*39a230aaSStefan Roese/ { 52*39a230aaSStefan Roese model = "Marvell Armada 380 family SoC"; 53*39a230aaSStefan Roese compatible = "marvell,armada380"; 54*39a230aaSStefan Roese 55*39a230aaSStefan Roese cpus { 56*39a230aaSStefan Roese #address-cells = <1>; 57*39a230aaSStefan Roese #size-cells = <0>; 58*39a230aaSStefan Roese enable-method = "marvell,armada-380-smp"; 59*39a230aaSStefan Roese 60*39a230aaSStefan Roese cpu@0 { 61*39a230aaSStefan Roese device_type = "cpu"; 62*39a230aaSStefan Roese compatible = "arm,cortex-a9"; 63*39a230aaSStefan Roese reg = <0>; 64*39a230aaSStefan Roese }; 65*39a230aaSStefan Roese }; 66*39a230aaSStefan Roese 67*39a230aaSStefan Roese soc { 68*39a230aaSStefan Roese internal-regs { 69*39a230aaSStefan Roese pinctrl@18000 { 70*39a230aaSStefan Roese compatible = "marvell,mv88f6810-pinctrl"; 71*39a230aaSStefan Roese }; 72*39a230aaSStefan Roese }; 73*39a230aaSStefan Roese 74*39a230aaSStefan Roese pcie-controller { 75*39a230aaSStefan Roese compatible = "marvell,armada-370-pcie"; 76*39a230aaSStefan Roese status = "disabled"; 77*39a230aaSStefan Roese device_type = "pci"; 78*39a230aaSStefan Roese 79*39a230aaSStefan Roese #address-cells = <3>; 80*39a230aaSStefan Roese #size-cells = <2>; 81*39a230aaSStefan Roese 82*39a230aaSStefan Roese msi-parent = <&mpic>; 83*39a230aaSStefan Roese bus-range = <0x00 0xff>; 84*39a230aaSStefan Roese 85*39a230aaSStefan Roese ranges = 86*39a230aaSStefan Roese <0x82000000 0 0x80000 MBUS_ID(0xf0, 0x01) 0x80000 0 0x00002000 87*39a230aaSStefan Roese 0x82000000 0 0x40000 MBUS_ID(0xf0, 0x01) 0x40000 0 0x00002000 88*39a230aaSStefan Roese 0x82000000 0 0x44000 MBUS_ID(0xf0, 0x01) 0x44000 0 0x00002000 89*39a230aaSStefan Roese 0x82000000 0 0x48000 MBUS_ID(0xf0, 0x01) 0x48000 0 0x00002000 90*39a230aaSStefan Roese 0x82000000 0x1 0 MBUS_ID(0x08, 0xe8) 0 1 0 /* Port 0 MEM */ 91*39a230aaSStefan Roese 0x81000000 0x1 0 MBUS_ID(0x08, 0xe0) 0 1 0 /* Port 0 IO */ 92*39a230aaSStefan Roese 0x82000000 0x2 0 MBUS_ID(0x04, 0xe8) 0 1 0 /* Port 1 MEM */ 93*39a230aaSStefan Roese 0x81000000 0x2 0 MBUS_ID(0x04, 0xe0) 0 1 0 /* Port 1 IO */ 94*39a230aaSStefan Roese 0x82000000 0x3 0 MBUS_ID(0x04, 0xd8) 0 1 0 /* Port 2 MEM */ 95*39a230aaSStefan Roese 0x81000000 0x3 0 MBUS_ID(0x04, 0xd0) 0 1 0 /* Port 2 IO */>; 96*39a230aaSStefan Roese 97*39a230aaSStefan Roese /* x1 port */ 98*39a230aaSStefan Roese pcie@1,0 { 99*39a230aaSStefan Roese device_type = "pci"; 100*39a230aaSStefan Roese assigned-addresses = <0x82000800 0 0x80000 0 0x2000>; 101*39a230aaSStefan Roese reg = <0x0800 0 0 0 0>; 102*39a230aaSStefan Roese #address-cells = <3>; 103*39a230aaSStefan Roese #size-cells = <2>; 104*39a230aaSStefan Roese #interrupt-cells = <1>; 105*39a230aaSStefan Roese ranges = <0x82000000 0 0 0x82000000 0x1 0 1 0 106*39a230aaSStefan Roese 0x81000000 0 0 0x81000000 0x1 0 1 0>; 107*39a230aaSStefan Roese interrupt-map-mask = <0 0 0 0>; 108*39a230aaSStefan Roese interrupt-map = <0 0 0 0 &gic GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>; 109*39a230aaSStefan Roese marvell,pcie-port = <0>; 110*39a230aaSStefan Roese marvell,pcie-lane = <0>; 111*39a230aaSStefan Roese clocks = <&gateclk 8>; 112*39a230aaSStefan Roese status = "disabled"; 113*39a230aaSStefan Roese }; 114*39a230aaSStefan Roese 115*39a230aaSStefan Roese /* x1 port */ 116*39a230aaSStefan Roese pcie@2,0 { 117*39a230aaSStefan Roese device_type = "pci"; 118*39a230aaSStefan Roese assigned-addresses = <0x82000800 0 0x40000 0 0x2000>; 119*39a230aaSStefan Roese reg = <0x1000 0 0 0 0>; 120*39a230aaSStefan Roese #address-cells = <3>; 121*39a230aaSStefan Roese #size-cells = <2>; 122*39a230aaSStefan Roese #interrupt-cells = <1>; 123*39a230aaSStefan Roese ranges = <0x82000000 0 0 0x82000000 0x2 0 1 0 124*39a230aaSStefan Roese 0x81000000 0 0 0x81000000 0x2 0 1 0>; 125*39a230aaSStefan Roese interrupt-map-mask = <0 0 0 0>; 126*39a230aaSStefan Roese interrupt-map = <0 0 0 0 &gic GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; 127*39a230aaSStefan Roese marvell,pcie-port = <1>; 128*39a230aaSStefan Roese marvell,pcie-lane = <0>; 129*39a230aaSStefan Roese clocks = <&gateclk 5>; 130*39a230aaSStefan Roese status = "disabled"; 131*39a230aaSStefan Roese }; 132*39a230aaSStefan Roese 133*39a230aaSStefan Roese /* x1 port */ 134*39a230aaSStefan Roese pcie@3,0 { 135*39a230aaSStefan Roese device_type = "pci"; 136*39a230aaSStefan Roese assigned-addresses = <0x82000800 0 0x44000 0 0x2000>; 137*39a230aaSStefan Roese reg = <0x1800 0 0 0 0>; 138*39a230aaSStefan Roese #address-cells = <3>; 139*39a230aaSStefan Roese #size-cells = <2>; 140*39a230aaSStefan Roese #interrupt-cells = <1>; 141*39a230aaSStefan Roese ranges = <0x82000000 0 0 0x82000000 0x3 0 1 0 142*39a230aaSStefan Roese 0x81000000 0 0 0x81000000 0x3 0 1 0>; 143*39a230aaSStefan Roese interrupt-map-mask = <0 0 0 0>; 144*39a230aaSStefan Roese interrupt-map = <0 0 0 0 &gic GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>; 145*39a230aaSStefan Roese marvell,pcie-port = <2>; 146*39a230aaSStefan Roese marvell,pcie-lane = <0>; 147*39a230aaSStefan Roese clocks = <&gateclk 6>; 148*39a230aaSStefan Roese status = "disabled"; 149*39a230aaSStefan Roese }; 150*39a230aaSStefan Roese }; 151*39a230aaSStefan Roese }; 152*39a230aaSStefan Roese}; 153