1*6cc102beSKonstantin PorotchkinArmada-8K PCIe DT details: 2*6cc102beSKonstantin Porotchkin========================== 3*6cc102beSKonstantin Porotchkin 4*6cc102beSKonstantin PorotchkinArmada-8k uses synopsis designware PCIe controller. 5*6cc102beSKonstantin Porotchkin 6*6cc102beSKonstantin PorotchkinRequired properties: 7*6cc102beSKonstantin Porotchkin- compatible : should be "marvell,armada8k-pcie", "snps,dw-pcie". 8*6cc102beSKonstantin Porotchkin- reg: base addresses and lengths of the pcie control and global control registers. 9*6cc102beSKonstantin Porotchkin "ctrl" registers points to the global control registers, while the "config" space 10*6cc102beSKonstantin Porotchkin points to the pcie configuration registers as mentioned in dw-pcie dt bindings in the link below. 11*6cc102beSKonstantin Porotchkin- interrupt-map-mask and interrupt-map, standard PCI properties to 12*6cc102beSKonstantin Porotchkin define the mapping of the PCIe interface to interrupt numbers. 13*6cc102beSKonstantin Porotchkin- All other definitions as per generic PCI bindings 14*6cc102beSKonstantin PorotchkinSee Linux kernel documentation: 15*6cc102beSKonstantin Porotchkin"Documentation/devicetree/bindings/pci/designware-pcie.txt" 16*6cc102beSKonstantin Porotchkin 17*6cc102beSKonstantin PorotchkinOptional properties: 18*6cc102beSKonstantin PorotchkinPHY support is still not supported for armada-8k, once it will, the following parameters can be used: 19*6cc102beSKonstantin Porotchkin- phys : phandle to phy node associated with pcie controller. 20*6cc102beSKonstantin Porotchkin- phy-names : must be "pcie-phy" 21*6cc102beSKonstantin Porotchkin- marvell,reset-gpio : specifies a gpio that needs to be activated for plug-in 22*6cc102beSKonstantin Porotchkin card reset signal release. 23*6cc102beSKonstantin PorotchkinExample: 24*6cc102beSKonstantin Porotchkin 25*6cc102beSKonstantin Porotchkincpm_pcie0: pcie@f2600000 { 26*6cc102beSKonstantin Porotchkin compatible = "marvell,armada8k-pcie", "snps,dw-pcie"; 27*6cc102beSKonstantin Porotchkin reg = <0 0xf2600000 0 0x10000>, 28*6cc102beSKonstantin Porotchkin <0 0xf6f00000 0 0x80000>; 29*6cc102beSKonstantin Porotchkin reg-names = "ctrl", "config"; 30*6cc102beSKonstantin Porotchkin #address-cells = <3>; 31*6cc102beSKonstantin Porotchkin #size-cells = <2>; 32*6cc102beSKonstantin Porotchkin #interrupt-cells = <1>; 33*6cc102beSKonstantin Porotchkin device_type = "pci"; 34*6cc102beSKonstantin Porotchkin dma-coherent; 35*6cc102beSKonstantin Porotchkin 36*6cc102beSKonstantin Porotchkin bus-range = <0 0xff>; 37*6cc102beSKonstantin Porotchkin ranges = 38*6cc102beSKonstantin Porotchkin /* downstream I/O */ 39*6cc102beSKonstantin Porotchkin <0x81000000 0 0xf9000000 0 0xf9000000 0 0x10000 40*6cc102beSKonstantin Porotchkin /* non-prefetchable memory */ 41*6cc102beSKonstantin Porotchkin 0x82000000 0 0xf6000000 0 0xf6000000 0 0xf00000>; 42*6cc102beSKonstantin Porotchkin interrupt-map-mask = <0 0 0 0>; 43*6cc102beSKonstantin Porotchkin interrupt-map = <0 0 0 0 &gic 0 GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; 44*6cc102beSKonstantin Porotchkin interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; 45*6cc102beSKonstantin Porotchkin num-lanes = <1>; 46*6cc102beSKonstantin Porotchkin clocks = <&cpm_syscon0 1 13>; 47*6cc102beSKonstantin Porotchkin marvell,reset-gpio = <&cpm_gpio1 20 GPIO_ACTIVE_HIGH>; 48*6cc102beSKonstantin Porotchkin status = "disabled"; 49*6cc102beSKonstantin Porotchkin}; 50