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Searched refs:msr (Results 1 – 25 of 62) sorted by relevance

123

/rk3399_rockchip-uboot/arch/x86/cpu/ivybridge/
H A Dmodel_206ax.c35 msr_t msr; in enable_vmx() local
42 msr = msr_read(MSR_IA32_FEATURE_CONTROL); in enable_vmx()
44 if (msr.lo & (1 << 0)) { in enable_vmx()
55 msr.hi = 0; in enable_vmx()
56 msr.lo = 0; in enable_vmx()
77 msr.lo |= (1 << 2); in enable_vmx()
79 msr.lo |= (1 << 1); in enable_vmx()
82 msr_write(MSR_IA32_FEATURE_CONTROL, msr); in enable_vmx()
164 msr_t msr = msr_read(MSR_PLATFORM_INFO); in set_power_limits() local
173 if (!(msr.lo & PLATFORM_INFO_SET_TDP)) in set_power_limits()
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/rk3399_rockchip-uboot/arch/x86/cpu/broadwell/
H A Dcpu.c105 msr_t msr, perf_ctl, platform_info; in set_max_freq() local
112 msr = msr_read(MSR_CONFIG_TDP_NOMINAL); in set_max_freq()
113 perf_ctl.lo = (msr.lo & 0xff) << 8; in set_max_freq()
116 msr = msr_read(MSR_PLATFORM_INFO); in set_max_freq()
117 perf_ctl.lo = msr.lo & 0xff00; in set_max_freq()
233 msr_t msr; in initialize_vr_config() local
238 msr = msr_read(MSR_VR_CURRENT_CONFIG); in initialize_vr_config()
243 msr.hi &= 0xc0000000; in initialize_vr_config()
244 msr.hi |= (0x01 << (52 - 32)); /* PSI3 threshold - 1A */ in initialize_vr_config()
245 msr.hi |= (0x05 << (42 - 32)); /* PSI2 threshold - 5A */ in initialize_vr_config()
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/rk3399_rockchip-uboot/arch/x86/include/asm/
H A Dmsr.h27 struct msr { struct
39 struct msr reg; argument
40 struct msr *msrs;
76 unsigned long long native_read_msr(unsigned int msr) in native_read_msr() argument
80 asm volatile("rdmsr" : EAX_EDX_RET(val, low, high) : "c" (msr)); in native_read_msr()
84 static inline void native_write_msr(unsigned int msr, in native_write_msr() argument
87 asm volatile("wrmsr" : : "c" (msr), "a"(low), "d" (high) : "memory"); in native_write_msr()
113 #define rdmsr(msr, val1, val2) \ argument
115 u64 __val = native_read_msr((msr)); \
120 static inline void wrmsr(unsigned msr, unsigned low, unsigned high) in wrmsr() argument
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/rk3399_rockchip-uboot/arch/arm/include/asm/
H A Dmacro.h167 msr cptr_el3, xzr /* Disable coprocessor traps to EL3 */
169 msr cptr_el2, \tmp /* Disable coprocessor traps to EL2 */
172 msr cntvoff_el2, xzr
184 msr sctlr_el2, \tmp
187 msr sp_el2, \tmp /* Migrate SP */
189 msr vbar_el2, \tmp /* Migrate VBAR */
208 msr scr_el3, \tmp
214 msr spsr_el3, \tmp
215 msr elr_el3, \ep
226 msr scr_el3, \tmp
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/rk3399_rockchip-uboot/arch/arm/cpu/armv8/
H A Dstart.S100 3: msr vbar_el3, x0
103 msr scr_el3, x0
104 msr cptr_el3, xzr /* Enable FP/SIMD */
107 msr cntfrq_el0, x0 /* Initialize CNTFRQ */
110 2: msr vbar_el2, x0
112 msr cptr_el2, x0 /* Enable FP/SIMD */
114 1: msr vbar_el1, x0
116 msr cpacr_el1, x0 /* Enable FP/SIMD */
131 msr sctlr_el3, x0
133 msr daifclr, #4 /* Enable SError. SCR_EL3.EA=1 was already set in start.S */
[all …]
H A Dsleep.S134 msr daifset, #0x03
172 msr vbar_el2, x2
173 msr cptr_el2, x3
174 msr ttbr0_el2, x4
175 msr tcr_el2, x5
176 msr mair_el2, x6
177 msr cntvoff_el2, x7
178 msr hcr_el2, x9
181 msr sctlr_el2, x8
186 msr daif, x10
H A Dcache.S28 msr csselr_el1, x12 /* select cache level */
100 msr csselr_el1, x0 /* restore csselr_el1 */
238 3: msr sctlr_el3, x1
240 2: msr sctlr_el2, x1
242 1: msr sctlr_el1, x1
253 3: msr ttbr0_el3, x0
255 2: msr ttbr0_el2, x0
257 1: msr ttbr0_el1, x0
262 3: msr sctlr_el3, x2
264 2: msr sctlr_el2, x2
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/rk3399_rockchip-uboot/arch/x86/cpu/
H A Dlapic.c69 msr_t msr; in enable_lapic() local
71 msr = msr_read(MSR_IA32_APICBASE); in enable_lapic()
72 msr.hi &= 0xffffff00; in enable_lapic()
73 msr.lo |= MSR_IA32_APICBASE_ENABLE; in enable_lapic()
74 msr.lo &= ~MSR_IA32_APICBASE_BASE; in enable_lapic()
75 msr.lo |= LAPIC_DEFAULT_BASE; in enable_lapic()
76 msr_write(MSR_IA32_APICBASE, msr); in enable_lapic()
83 msr_t msr; in disable_lapic() local
85 msr = msr_read(MSR_IA32_APICBASE); in disable_lapic()
86 msr.lo &= ~MSR_IA32_APICBASE_ENABLE; in disable_lapic()
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H A Dturbo.c54 msr_t msr; in turbo_get_state() local
64 msr = msr_read(MSR_IA32_MISC_ENABLES); in turbo_get_state()
65 turbo_en = !(msr.hi & H_MISC_DISABLE_TURBO); in turbo_get_state()
85 msr_t msr; in turbo_enable() local
90 msr = msr_read(MSR_IA32_MISC_ENABLES); in turbo_enable()
91 msr.hi &= ~H_MISC_DISABLE_TURBO; in turbo_enable()
92 msr_write(MSR_IA32_MISC_ENABLES, msr); in turbo_enable()
H A Dmp_init.c171 msr_t msr; in save_msr() local
173 msr = msr_read(index); in save_msr()
175 entry->lo = msr.lo; in save_msr()
176 entry->hi = msr.hi; in save_msr()
189 msr_t msr; in save_bsp_msrs() local
192 msr = msr_read(MTRR_CAP_MSR); in save_bsp_msrs()
193 num_var_mtrrs = msr.lo & 0xff; in save_bsp_msrs()
/rk3399_rockchip-uboot/arch/powerpc/cpu/mpc8xx/
H A Dtraps.c62 regs->msr, regs->msr & MSR_EE ? 1 : 0, in show_regs()
63 regs->msr & MSR_PR ? 1 : 0, regs->msr & MSR_FP ? 1 : 0, in show_regs()
64 regs->msr & MSR_ME ? 1 : 0, regs->msr & MSR_IR ? 1 : 0, in show_regs()
65 regs->msr & MSR_DR ? 1 : 0); in show_regs()
102 switch (regs->msr & 0x000F0000) { in MachineCheckException()
149 regs->nip, regs->msr, regs->trap); in UnknownException()
H A Dcpu.c197 ulong msr, addr; in do_reset() local
206 __asm__ volatile ("mfmsr %0" : "=r" (msr)); in do_reset()
208 msr &= ~0x1030; in do_reset()
209 __asm__ volatile ("mtmsr %0" : : "r" (msr)); in do_reset()
/rk3399_rockchip-uboot/arch/arm/lib/
H A Dgic_64.S120 msr ICC_SRE_EL3, x10
127 msr ICC_SRE_EL2, x10
137 msr ICC_IGRPEN1_EL3, x10
140 msr ICC_CTLR_EL3, xzr
145 msr ICC_IGRPEN1_EL1, x10
148 msr ICC_CTLR_EL1, xzr /* NonSecure ICC_CTLR_EL1 */
152 msr ICC_PMR_EL1, x10
159 msr ICC_SRE_EL3, x10
165 msr ICC_SRE_EL2, x10
169 msr ICC_IGRPEN1_EL3, x10
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/rk3399_rockchip-uboot/arch/powerpc/lib/
H A Dkgdb.c82 unsigned long msr; in kgdb_enter() local
84 kdp->private[0] = msr = get_msr(); in kgdb_enter()
85 set_msr(msr & ~MSR_EE); /* disable interrupts */ in kgdb_enter()
91 regs->msr &= ~MSR_SE; in kgdb_enter()
108 unsigned long msr = kdp->private[0]; in kgdb_exit() local
117 set_msr(msr); in kgdb_exit()
121 regs->msr |= MSR_SE; in kgdb_exit()
123 set_msr(msr | MSR_SE); in kgdb_exit()
172 *ptr++ = regs->msr; in kgdb_getregs()
205 case 65: regs->msr = *ptr; break; in kgdb_putreg()
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H A Dinterrupts.c58 ulong msr = get_msr (); in disable_interrupts() local
60 set_msr (msr & ~MSR_EE); in disable_interrupts()
61 return ((msr & MSR_EE) != 0); in disable_interrupts()
/rk3399_rockchip-uboot/arch/powerpc/cpu/mpc83xx/
H A Dtraps.c59 regs->msr, regs->msr&MSR_EE ? 1 : 0, regs->msr&MSR_PR ? 1 : 0, in show_regs()
60 regs->msr & MSR_FP ? 1 : 0,regs->msr&MSR_ME ? 1 : 0, in show_regs()
61 regs->msr&MSR_IR ? 1 : 0, in show_regs()
62 regs->msr&MSR_DR ? 1 : 0); in show_regs()
136 switch( regs->msr & 0x000F0000) { in MachineCheckException()
202 regs->nip, regs->msr, regs->trap); in UnknownException()
H A Dcpu.c122 ulong msr; in do_reset() local
134 __asm__ __volatile__ ("mfmsr %0":"=r" (msr):); in do_reset()
136 msr &= ~( MSR_EE | MSR_IR | MSR_DR); in do_reset()
137 __asm__ __volatile__ ("mtmsr %0"::"r" (msr)); in do_reset()
157 __asm__ __volatile__ ("mfmsr %0":"=r" (msr):); in do_reset()
159 msr &= ~(MSR_ME | MSR_EE | MSR_IR | MSR_DR); in do_reset()
160 __asm__ __volatile__ ("mtmsr %0"::"r" (msr)); in do_reset()
/rk3399_rockchip-uboot/arch/powerpc/cpu/mpc86xx/
H A Dtraps.c68 regs->msr, regs->msr & MSR_EE ? 1 : 0, in show_regs()
69 regs->msr & MSR_PR ? 1 : 0, regs->msr & MSR_FP ? 1 : 0, in show_regs()
70 regs->msr & MSR_ME ? 1 : 0, regs->msr & MSR_IR ? 1 : 0, in show_regs()
71 regs->msr & MSR_DR ? 1 : 0); in show_regs()
115 switch ( regs->msr & 0x001F0000) { in MachineCheckException()
195 regs->nip, regs->msr, regs->trap); in UnknownException()
/rk3399_rockchip-uboot/arch/x86/cpu/baytrail/
H A Dcpu.c69 msr_t msr; in set_max_freq() local
72 msr = msr_read(MSR_IA32_MISC_ENABLES); in set_max_freq()
73 msr.lo |= (1 << 16); in set_max_freq()
74 msr_write(MSR_IA32_MISC_ENABLES, msr); in set_max_freq()
80 msr = msr_read(MSR_IACORE_RATIOS); in set_max_freq()
81 perf_ctl.lo = (msr.lo & 0x3f0000) >> 8; in set_max_freq()
87 msr = msr_read(MSR_IACORE_VIDS); in set_max_freq()
88 perf_ctl.lo |= (msr.lo & 0x7f0000) >> 16; in set_max_freq()
/rk3399_rockchip-uboot/arch/x86/cpu/intel_common/
H A Dcpu.c70 msr_t flex_ratio, msr; in cpu_set_flex_ratio_to_tdp_nominal() local
79 msr = msr_read(MSR_PLATFORM_INFO); in cpu_set_flex_ratio_to_tdp_nominal()
80 if (((msr.hi >> 1) & 3) == 0) in cpu_set_flex_ratio_to_tdp_nominal()
84 msr = msr_read(MSR_CONFIG_TDP_NOMINAL); in cpu_set_flex_ratio_to_tdp_nominal()
85 nominal_ratio = msr.lo & 0xff; in cpu_set_flex_ratio_to_tdp_nominal()
/rk3399_rockchip-uboot/arch/powerpc/cpu/mpc85xx/
H A Dtraps.c95 regs->msr, regs->msr&MSR_EE ? 1 : 0, regs->msr&MSR_PR ? 1 : 0, in show_regs()
96 regs->msr & MSR_FP ? 1 : 0,regs->msr&MSR_ME ? 1 : 0, in show_regs()
97 regs->msr&MSR_IR ? 1 : 0, in show_regs()
98 regs->msr&MSR_DR ? 1 : 0); in show_regs()
258 regs->nip, regs->msr, regs->trap); in UnknownException()
274 regs->nip, regs->msr, regs->trap); in ExtIntException()
/rk3399_rockchip-uboot/arch/powerpc/include/asm/
H A Dppc.h109 unsigned long msr; in get_msr() local
111 asm volatile ("mfmsr %0" : "=r" (msr) : ); in get_msr()
113 return msr; in get_msr()
116 static inline void set_msr(unsigned long msr) in set_msr() argument
118 asm volatile ("mtmsr %0" : : "r" (msr)); in set_msr()
H A Dptrace.h29 PPC_REG msr; member
50 #define user_mode(regs) (((regs)->msr & MSR_PR) != 0)
/rk3399_rockchip-uboot/arch/arm/cpu/arm926ejs/mxs/
H A Dstart.S72 msr cpsr, r2
78 msr cpsr,r2
/rk3399_rockchip-uboot/drivers/i2c/
H A Dimx_lpi2c.c33 status = readl(&regs->msr); in imx_lpci2c_check_busy_bus()
46 status = readl(&regs->msr); in imx_lpci2c_check_clear_error()
62 writel(0x7f00, &regs->msr); in imx_lpci2c_check_clear_error()
132 writel(0x7f00, &regs->msr); in bus_i2c_receive()
168 writel(0x7f00, &regs->msr); in bus_i2c_start()
200 status = readl(&regs->msr); in bus_i2c_stop()
206 writel(status, &regs->msr); in bus_i2c_stop()

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