| #
7cef7918 |
| 16-Jul-2021 |
Joseph Chen <chenjh@rock-chips.com> |
irq: simplify the #if expression
Use CONFIG_IS_ENABLED() is better.
Signed-off-by: Joseph Chen <chenjh@rock-chips.com>
Change-Id: If4f514cc1dfb9e0f52521954158172bba1eb8f85
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| #
f4fc5f8d |
| 10-Nov-2017 |
Kever Yang <kever.yang@rock-chips.com> |
arm: irq: do not enable irq in SPL/TPL
Change-Id: I6a9b8b883ede2e45e2c5760c633f04bd9ab4fe4e
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
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| #
fa40f8a0 |
| 25-Sep-2017 |
Joseph Chen <chenjh@rock-chips.com> |
ARM: add support for irq interrup framework
both GICV2 and GICV3 are supported
Change-Id: Ie928cc781c0e0830b98d12c4033e45a43befc2ff
Signed-off-by: Joseph Chen <chenjh@rock-chips.com>
|
| #
a69fdc77 |
| 23-Oct-2015 |
Stefano Babic <sbabic@denx.de> |
Merge branch 'master' of git://git.denx.de/u-boot
|
| #
1275456d |
| 15-Oct-2015 |
Tom Rini <trini@konsulko.com> |
Merge branch 'master' of git://git.denx.de/u-boot-arm
|
| #
b1964c72 |
| 20-Aug-2015 |
Thierry Reding <treding@nvidia.com> |
armv8/gic: Fix GIC v2 initialization
Initialize all GICD_IGROUPRn registers and set up GICC_CTLR to enable
interrupts to the primary CPU. This fixes issues seen after booting a
Linux kernel from U-B
armv8/gic: Fix GIC v2 initialization
Initialize all GICD_IGROUPRn registers and set up GICC_CTLR to enable
interrupts to the primary CPU. This fixes issues seen after booting a
Linux kernel from U-Boot.
Suggested-by: Marc Zyngier <marc.zyngier@arm.com>
Suggested-by: Mark Rutland <mark.rutland@arm.com>
Cc: Albert Aribaud <albert.u.boot@aribaud.net>
Cc: Mark Rutland <mark.rutland@arm.com>
Cc: Marc Zyngier <marc.zyngier@arm.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
show more ...
|
| #
3cc83f9d |
| 07-Oct-2014 |
Minkyu Kang <mk7.kang@samsung.com> |
Merge branch 'uboot'
|
| #
2c2277f1 |
| 26-Sep-2014 |
Tom Rini <trini@ti.com> |
Merge branch 'master' of git://git.denx.de/u-boot-fsl-qoriq
|
| #
40f8dec5 |
| 08-Sep-2014 |
York Sun <yorksun@freescale.com> |
armv8/fsl-lsch3: Release secondary cores from boot hold off with Boot Page
Secondary cores need to be released from holdoff by boot release
registers. With GPP bootrom, they can boot from main memor
armv8/fsl-lsch3: Release secondary cores from boot hold off with Boot Page
Secondary cores need to be released from holdoff by boot release
registers. With GPP bootrom, they can boot from main memory
directly. Individual spin table is used for each core. Spin table
and the boot page is reserved in device tree so OS won't overwrite.
Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Arnab Basu <arnab.basu@freescale.com>
show more ...
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| #
c71645ad |
| 14-Mar-2014 |
David Feng <fenghua@phytium.com.cn> |
arm64 patch: gicv3 support
This patch add gicv3 support to uboot armv8 platform.
Changes for v2:
- rename arm/cpu/armv8/gic.S with arm/lib/gic_64.S
- move smp_kick_all_cpus() from gic.S to star
arm64 patch: gicv3 support
This patch add gicv3 support to uboot armv8 platform.
Changes for v2:
- rename arm/cpu/armv8/gic.S with arm/lib/gic_64.S
- move smp_kick_all_cpus() from gic.S to start.S, it would be
implementation dependent.
- Each core initialize it's own ReDistributor instead of master
initializeing all ReDistributors. This is advised by arnab.basu
<arnab.basu@freescale.com>.
Signed-off-by: David Feng <fenghua@phytium.com.cn>
show more ...
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