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Searched refs:mr2 (Results 1 – 19 of 19) sorted by relevance

/rk3399_rockchip-uboot/board/ti/ks2_evm/
H A Dddr3_k2g.c32 .mr2 = 0x00000000ul,
83 .mr2 = 0x00000008ul,
H A Dddr3_cfg.c31 .mr2 = 0x00000018ul,
/rk3399_rockchip-uboot/arch/arm/mach-sunxi/
H A Ddram_sun8i_a23.c40 .mr2 = 16,
117 writel(dram_para.mr2, &mctl_phy->mr2); in mctl_init()
202 writel((dram_para.mr2 << 16) | dram_para.mr3, &mctl_ctl->init4); in mctl_init()
H A Ddram_sun8i_a83t.c137 writel(MCTL_MR2, &mctl_ctl->mr2); in auto_set_timing_para()
142 writel(MCTL_LPDDR3_MR2, &mctl_ctl->mr2); in auto_set_timing_para()
H A Ddram_sun8i_a33.c136 writel(MCTL_MR2, &mctl_ctl->mr2); in auto_set_timing_para()
H A Ddram_sun6i.c125 writel(MCTL_MR2, &mctl_phy->mr2); in mctl_channel_init()
H A Ddram_sun9i.c637 writel(mr[2], &mctl_phy->mr2); in mctl_channel_init()
/rk3399_rockchip-uboot/arch/arm/mach-keystone/include/mach/
H A Dddr3.h31 unsigned int mr2; member
/rk3399_rockchip-uboot/arch/arm/include/asm/arch-sunxi/
H A Ddram_sun8i_a23.h27 u32 mr2; member
187 u32 mr2; /* 0x5c mode register 2 */ member
H A Ddram_sun8i_a33.h77 u32 mr2; /* 0x38 */ member
H A Ddram_sun8i_a83t.h77 u32 mr2; /* 0x38 */ member
H A Ddram_sun9i.h110 u32 mr2; /* 0xa4 mode register 2 */ member
H A Ddram_sun6i.h176 u32 mr2; /* 0x48 mode register 2 */ member
/rk3399_rockchip-uboot/arch/arm/mach-omap2/omap4/
H A Dsdram_elpida.c310 .mr2 = 0x4,
/rk3399_rockchip-uboot/arch/arm/mach-keystone/
H A Dddr3_spd.c37 debug_ddr_cfg("mr2 0x%08X\n", ptr->mr2); in dump_phy_config()
356 spd_cb->phy_cfg.mr2 = DYN_ODT << 9 | TEMP << 7 | (spd->asr & 1) << 6 | in init_ddr3param()
H A Dddr3.c55 __raw_writel(phy_cfg->mr2, base + KS2_DDRPHY_MR2_OFFSET); in ddr3_init_ddrphy()
/rk3399_rockchip-uboot/arch/arm/mach-omap2/omap5/
H A Dsdram.c442 .mr2 = 0x6,
/rk3399_rockchip-uboot/arch/arm/include/asm/
H A Demif.h1197 s8 mr2; member
/rk3399_rockchip-uboot/arch/arm/mach-omap2/
H A Demif-common.c120 set_mr(base, cs, mr_addr, mr_regs->mr2); in do_lpddr2_init()