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Searched refs:max_clk (Results 1 – 16 of 16) sorted by relevance

/rk3399_rockchip-uboot/arch/arm/mach-omap2/omap3/
H A Dsys_info.c246 char *cpu_family_s, *cpu_s, *sec_s, *max_clk; in print_cpuinfo() local
270 max_clk = "720 MHz"; in print_cpuinfo()
272 max_clk = "600 MHz"; in print_cpuinfo()
288 max_clk = "600 MHz"; in print_cpuinfo()
295 max_clk = "800 MHz"; in print_cpuinfo()
300 max_clk = "1 GHz"; in print_cpuinfo()
305 max_clk = "800 MHz"; in print_cpuinfo()
310 max_clk = "1 GHz"; in print_cpuinfo()
315 max_clk = "800 MHz"; in print_cpuinfo()
320 max_clk = "1 GHz"; in print_cpuinfo()
[all …]
/rk3399_rockchip-uboot/drivers/mmc/
H A Datmel_sdhci.c21 u32 max_clk, min_clk = ATMEL_SDHC_MIN_FREQ; in atmel_sdhci_init() local
32 max_clk = at91_get_periph_generated_clk(id); in atmel_sdhci_init()
33 if (!max_clk) { in atmel_sdhci_init()
38 host->max_clk = max_clk; in atmel_sdhci_init()
59 u32 max_clk; in atmel_sdhci_probe() local
95 max_clk = clk_get_rate(&clk); in atmel_sdhci_probe()
96 if (!max_clk) in atmel_sdhci_probe()
99 host->max_clk = max_clk; in atmel_sdhci_probe()
H A Dkona_sdhci.c81 u32 max_clk; in kona_sdhci_init() local
94 &max_clk); in kona_sdhci_init()
99 &max_clk); in kona_sdhci_init()
104 &max_clk); in kona_sdhci_init()
109 &max_clk); in kona_sdhci_init()
124 host->max_clk = max_clk; in kona_sdhci_init()
H A Dmv_sdhci.c68 int mv_sdh_init(unsigned long regbase, u32 max_clk, u32 min_clk, u32 quirks) in mv_sdh_init() argument
80 host->max_clk = max_clk; in mv_sdh_init()
H A Dsdhci.c368 if ((host->max_clk / div) <= clock)
380 if (host->max_clk <= clock) {
386 if ((host->max_clk / div) <= clock)
395 if ((host->max_clk / div) <= clock)
753 if (host->max_clk == 0) {
755 host->max_clk = (caps & SDHCI_CLOCK_V3_BASE_MASK) >>
758 host->max_clk = (caps & SDHCI_CLOCK_BASE_MASK) >>
760 host->max_clk *= 1000000;
762 host->max_clk *= host->clk_mul;
764 if (host->max_clk == 0) {
[all …]
H A Dpic32_sdhci.c59 host->max_clk = f_min_max[1]; in pic32_sdhci_probe()
H A Dzynq_sdhci.c64 host->max_clk = clock; in arasan_sdhci_probe()
H A Ddw_mmc.c910 u32 max_clk, u32 min_clk) argument
917 cfg->f_max = max_clk;
950 int add_dwmci(struct dwmci_host *host, u32 max_clk, u32 min_clk) argument
952 dwmci_setup_cfg(&host->cfg, host, max_clk, min_clk);
H A Dmsm_sdhci.c99 host->max_clk = 0; in msm_sdc_probe()
H A Dbcm2835_sdhci.c207 host->max_clk = emmc_freq; in bcm2835_sdhci_probe()
H A Ds5p_sdhci.c94 host->max_clk = 52000000; in s5p_sdhci_core_init()
H A Drockchip_sdhci.c230 input_clk = host->max_clk; in rockchip_emmc_set_clock()
568 host->max_clk = max_frequency; in rockchip_sdhci_probe()
H A Dxenon_sdhci.c413 host->max_clk = XENON_MMC_MAX_CLK; in xenon_sdhci_probe()
/rk3399_rockchip-uboot/include/
H A Ddwmmc.h282 u32 max_clk, u32 min_clk);
312 int add_dwmci(struct dwmci_host *host, u32 max_clk, u32 min_clk);
H A Dsdhci.h279 unsigned int max_clk; /* Maximum Base Clock frequency */ member
/rk3399_rockchip-uboot/arch/arm/mach-mvebu/include/mach/
H A Dcpu.h142 int mv_sdh_init(unsigned long regbase, u32 max_clk, u32 min_clk, u32 quirks);