| #
df313aa6 |
| 04-Jun-2025 |
Xuhui Lin <xuhui.lin@rock-chips.com> |
drivers: dw_mmc: Add mmc-idmac fdt support
Change-Id: Ie0ebb0e2ac903545d83fae6037ef2dac6c4ba63b Signed-off-by: Xuhui Lin <xuhui.lin@rock-chips.com>
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| #
3aa32998 |
| 07-Jan-2025 |
Yifeng Zhao <yifeng.zhao@rock-chips.com> |
mmc: dw_mmc: synchronize upstream code to calculate data transmission timeout
Synchronize upstream code to calculate data transmission timeout, and optimize the calculation order to avoid data overf
mmc: dw_mmc: synchronize upstream code to calculate data transmission timeout
Synchronize upstream code to calculate data transmission timeout, and optimize the calculation order to avoid data overflow.
Signed-off-by: Yifeng Zhao <yifeng.zhao@rock-chips.com> Change-Id: Ib316499d41858ca6036ab11bfe4627e26de9a9dc
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| #
d8db857f |
| 22-Nov-2024 |
Shawn Lin <shawn.lin@rock-chips.com> |
dw_mmc: Clean interrupts after fifo access
Change-Id: I45a7c5655f03e94552ceb27e07b2dfea7dd1ed4f Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com>
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| #
1aaee36e |
| 13-Nov-2024 |
Shawn Lin <shawn.lin@rock-chips.com> |
dw_mmc: Fix fifo mode data transfer
When the remain data was received, DTO interrupt was generated but not RXDR if water level isn't enough when using SDIO byte mode. Check DTO as well in advanced a
dw_mmc: Fix fifo mode data transfer
When the remain data was received, DTO interrupt was generated but not RXDR if water level isn't enough when using SDIO byte mode. Check DTO as well in advanced and clear the masked bit first.
Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com> Change-Id: I936f9f19733b16fd3e73fbc51c33597d125e4913
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| #
5135be73 |
| 01-Aug-2024 |
Yifeng Zhao <yifeng.zhao@rock-chips.com> |
dw_mmc: send the initialization clock with cmd0
Two TF cards fail to initialize under the controller configuration CLKEN_LOW_PWR. It is necessary to add clock initialization when sending the first c
dw_mmc: send the initialization clock with cmd0
Two TF cards fail to initialize under the controller configuration CLKEN_LOW_PWR. It is necessary to add clock initialization when sending the first command to resolve this issue.
Signed-off-by: Yifeng Zhao <yifeng.zhao@rock-chips.com> Change-Id: I4d44bffd24d14131a61e2332fd555a3d6f92ed0c
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| #
f88a10fc |
| 08-May-2024 |
Yifeng Zhao <yifeng.zhao@rock-chips.com> |
dw_mmc: add default power enable config value for rk3576
Signed-off-by: Yifeng Zhao <yifeng.zhao@rock-chips.com> Change-Id: I2ce85f3c107c51b84413ca2f9ae66b33e4a00c18
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| #
0953e389 |
| 08-May-2024 |
Yifeng Zhao <yifeng.zhao@rock-chips.com> |
dw-mmc: spl: modify the timeout for reading data to 50ms
KOWIN's EMMC has a timeout issue and needs to be increased. bug: [2024-05-07_16:55:54:251]MMC error: The cmd index is 18, ret is -110 [2024-0
dw-mmc: spl: modify the timeout for reading data to 50ms
KOWIN's EMMC has a timeout issue and needs to be increased. bug: [2024-05-07_16:55:54:251]MMC error: The cmd index is 18, ret is -110 [2024-05-07_16:55:54:282]MMC error: The cmd index is 7, ret is -110 [2024-05-07_16:55:54:297]MMC error: The cmd index is 7, ret is -110
Signed-off-by: Yifeng Zhao <yifeng.zhao@rock-chips.com> Change-Id: I188e8a289684926cd6e2d75a82e620197955c8a9
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| #
3e4b5e88 |
| 28-Mar-2024 |
Yifeng Zhao <yifeng.zhao@rock-chips.com> |
mmc: dw_mmc: add card detect by DWMCI_CDETECT
Signed-off-by: Yifeng Zhao <yifeng.zhao@rock-chips.com> Change-Id: I1f94df4a75e016f4b3f0e7d021eb1d1941e6b1aa
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| #
a0f322f5 |
| 11-Dec-2023 |
Yifeng Zhao <yifeng.zhao@rock-chips.com> |
dw_mmc: add a delay before reset controller
It is necessary to wait for several cycles before resetting the controller while the data timeout.
bug: Best phase range 0-68 (7 len) Successfull
dw_mmc: add a delay before reset controller
It is necessary to wait for several cycles before resetting the controller while the data timeout.
bug: Best phase range 0-68 (7 len) Successfully tuned phase to 34, used 16543ms MMC error: The cmd index is 16, ret is -110 MMC error: The cmd index is 16, ret is -110
Signed-off-by: Yifeng Zhao <yifeng.zhao@rock-chips.com> Change-Id: Ibda35bfb07f18c2def3c5d48cfddd0e343a2b92d
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| #
315c0aef |
| 20-Nov-2023 |
Yifeng Zhao <yifeng.zhao@rock-chips.com> |
mmc: optimizing the data timeout time for cmd 21
The tuning data is 128bytes, a timeout of 1ms is sufficient.
Signed-off-by: Yifeng Zhao <yifeng.zhao@rock-chips.com> Change-Id: Ia68f7ef3da5d1599ab1
mmc: optimizing the data timeout time for cmd 21
The tuning data is 128bytes, a timeout of 1ms is sufficient.
Signed-off-by: Yifeng Zhao <yifeng.zhao@rock-chips.com> Change-Id: Ia68f7ef3da5d1599ab11c646dbcb9d35a2eab4cc
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| #
a32c3f92 |
| 21-Jul-2023 |
Yifeng Zhao <yifeng.zhao@rock-chips.com> |
mmc: dw_mmc: do power cycle for sdmmc
1. select pinctrl to idle to prevent power leak 2. control the power cycle by gpio "pwr-en-gpios"
Change-Id: I8bceff3f32f4788da0816aba59fa8e507def2c2c Signed-o
mmc: dw_mmc: do power cycle for sdmmc
1. select pinctrl to idle to prevent power leak 2. control the power cycle by gpio "pwr-en-gpios"
Change-Id: I8bceff3f32f4788da0816aba59fa8e507def2c2c Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com> Signed-off-by: Yifeng Zhao <yifeng.zhao@rock-chips.com>
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| #
bbd0d600 |
| 08-Jun-2023 |
Ziyuan Xu <xzy.xu@rock-chips.com> |
mmc: dw_mmc: set cmd/data timeout according to register
The previous implementation set the timeout to 10s as as a minimum, change it to reasonable value that is depends on register value.
Signed-o
mmc: dw_mmc: set cmd/data timeout according to register
The previous implementation set the timeout to 10s as as a minimum, change it to reasonable value that is depends on register value.
Signed-off-by: Ziyuan Xu <xzy.xu@rock-chips.com> Change-Id: I964a0d98f8849da79dede76db1638b939ad7999d
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| #
699945cb |
| 02-Mar-2022 |
Jason Zhu <jason.zhu@rock-chips.com> |
mmc: add CONFIG_MMC_SIMPLE
Delete hs200 & hs400 & some redundant code.
Signed-off-by: Jason Zhu <jason.zhu@rock-chips.com> Change-Id: I10a61d79357a192a7f978e2b8dea5d4b582bd2af
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| #
850d604a |
| 05-Jan-2022 |
Jason Zhu <jason.zhu@rock-chips.com> |
mmc: dw_mmc: call dm_gpio_free() to free the gpio device
Signed-off-by: Jason Zhu <jason.zhu@rock-chips.com> Change-Id: I9a0ab224bce7767f4d165ecc8dbf12ec8134cdbc
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| #
8cdfda89 |
| 23-Mar-2019 |
Marek Vasut <marex@denx.de> |
UPSTREAM: mmc: dw_mmc: Handle return value from bounce_buffer_start()
The bounce_buffer_start() can return -ENOMEM in case memory allocation failed. However, in that case, the bounce buffer address
UPSTREAM: mmc: dw_mmc: Handle return value from bounce_buffer_start()
The bounce_buffer_start() can return -ENOMEM in case memory allocation failed. However, in that case, the bounce buffer address is the same as the possibly unaligned input address, and the cache maintenance operations were not applied to this address. This could cause subtle problems. Add handling for the bounce_buffer_start() return value to prevent such a problem from happening.
Signed-off-by: Marek Vasut <marex@denx.de> Cc: Jaehoon Chung <jh80.chung@samsung.com> Cc: Simon Glass <sjg@chromium.org> Signed-off-by: Joseph Chen <chenjh@rock-chips.com> Change-Id: I0cdb3196e3ceb1d1f1935e003624afcb05001219 (cherry picked from commit 6ad5aec419782955fa4be79c93f2640fc043f3cf)
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| #
dc58c997 |
| 09-Oct-2021 |
Jason Zhu <jason.zhu@rock-chips.com> |
dwmmc: support sd card detect in spl
Signed-off-by: Jason Zhu <jason.zhu@rock-chips.com> Change-Id: Ia3c03629ee41f79e79744110fdaa6f3b6b7f5597
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| #
ddeaf211 |
| 23-Sep-2021 |
Jason Zhu <jason.zhu@rock-chips.com> |
mmc: dw_mmc: return -EINVAL if sclk is 0
Signed-off-by: Jason Zhu <jason.zhu@rock-chips.com> Change-Id: I141fb51a90e0b3bd76e95de653daae97e747b20b
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| #
6a8d650f |
| 05-Jul-2021 |
Ziyuan Xu <xzy.xu@rock-chips.com> |
mmc: dw_mmc: discard 100us delay after sending command
Signed-off-by: Ziyuan Xu <xzy.xu@rock-chips.com> Change-Id: If4a2044823f539c5966d18f30ae3909ce9eefa6f
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| #
80ac95fc |
| 14-May-2021 |
Ziyuan Xu <xzy.xu@rock-chips.com> |
mmc: dw_mmc: fixes bus-width=<1> handling
Signed-off-by: Ziyuan Xu <xzy.xu@rock-chips.com> Change-Id: Id9ff1e18d659ceb83eb43f22d2d601917b12b9ba
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| #
34d21c9a |
| 19-Jan-2021 |
Jason Zhu <jason.zhu@rock-chips.com> |
UPSTREAM: mmc: dw_mmc: Calculate timeout from transfer length
The current 4-minute data transfer timeout is misleading and broken. Instead of such a long wait, calculate the timeout duration based o
UPSTREAM: mmc: dw_mmc: Calculate timeout from transfer length
The current 4-minute data transfer timeout is misleading and broken. Instead of such a long wait, calculate the timeout duration based on the length of the data transfer. The current formula is the transfer length in bits, divided by a multiplication of bus frequency in Hz, bus width, DDR mode and converted the mSec. The value is bounded from the bottom to 10000 mSec.
Signed-off-by: Marek Vasut <marex@denx.de> Cc: Jaehoon Chung <jh80.chung@samsung.com> Cc: Simon Glass <sjg@chromium.org> Signed-off-by: Jason Zhu <jason.zhu@rock-chips.com> Change-Id: I168b6ceba917d3e621559a92a63fac78abca6bff (cherry picked from commit 4e16f0a67d80b4ce11995b870b5d9c8d11266d0d)
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| #
47f7fd3a |
| 05-Jun-2020 |
Jason Zhu <jason.zhu@rock-chips.com> |
blk/mmc: add function blk_dread_prepare
This function prepares to read data without confirming completed. We can use it to prefetch data and run other process.
Signed-off-by: Jason Zhu <jason.zhu@r
blk/mmc: add function blk_dread_prepare
This function prepares to read data without confirming completed. We can use it to prefetch data and run other process.
Signed-off-by: Jason Zhu <jason.zhu@rock-chips.com> Change-Id: I76116c25dfdb7559b80a0216c414189e85409a3e
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| #
33e40bac |
| 01-Jun-2020 |
Jason Zhu <jason.zhu@rock-chips.com> |
mmc: dw_mmc: set DWMCI_CARDTHRCTL
Since v2.80a, dwmmc controller introduced the card write threshold for HS200 & HS400 mode. So CardThrCtl can be supported during write operation, not only read oper
mmc: dw_mmc: set DWMCI_CARDTHRCTL
Since v2.80a, dwmmc controller introduced the card write threshold for HS200 & HS400 mode. So CardThrCtl can be supported during write operation, not only read operation.
Signed-off-by: Jason Zhu <jason.zhu@rock-chips.com> Change-Id: I7f345660107c2978d2f874d36f2dffd2acdfbcb6
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| #
204f7c39 |
| 29-Mar-2019 |
Jason Zhu <jason.zhu@rock-chips.com> |
mmc: dw_mmc: fix sd card power enable errror
The sd card power is enabled when PWREN is set low by rockchip hardware design.
Change-Id: I4fb54235bd5235030146f77be1e07dc4e729ae06 Signed-off-by: Jaso
mmc: dw_mmc: fix sd card power enable errror
The sd card power is enabled when PWREN is set low by rockchip hardware design.
Change-Id: I4fb54235bd5235030146f77be1e07dc4e729ae06 Signed-off-by: Jason Zhu <jason.zhu@rock-chips.com>
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| #
5743ef64 |
| 22-Feb-2019 |
Jason Zhu <jason.zhu@rock-chips.com> |
mmc: dw_mmc: support get_cd in struct dm_mmc_ops
Add function get_cd to detect storage device directly instead of detect it by mmc command.
Change-Id: I486dee836c62092baabe40fc6de995904849f91d Sign
mmc: dw_mmc: support get_cd in struct dm_mmc_ops
Add function get_cd to detect storage device directly instead of detect it by mmc command.
Change-Id: I486dee836c62092baabe40fc6de995904849f91d Signed-off-by: Jason Zhu <jason.zhu@rock-chips.com>
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| #
5ef89808 |
| 21-Aug-2018 |
Jason Zhu <jason.zhu@rock-chips.com> |
mmc: dw_mmc: set DWMCI_MSIZE to 6
We set the fifo_depth to 0x100 word in Rockchip platform, and fifo_depth/2 must be multiple of dma_multiple_transaction_size. So we can set DWMCI_MSIZE to 6 accordi
mmc: dw_mmc: set DWMCI_MSIZE to 6
We set the fifo_depth to 0x100 word in Rockchip platform, and fifo_depth/2 must be multiple of dma_multiple_transaction_size. So we can set DWMCI_MSIZE to 6 according to max dma_multiple_transaction_size being 128.
The DWMCI_MSIZE must be set as larger as possible. If not, dma fifo will be full, and crc error occur when the clock stop during the data phase.
Change-Id: I013b6f9c272edbc723b2f627e88d30d653c42d1b Signed-off-by: Jason Zhu <jason.zhu@rock-chips.com>
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