18cb78722SStefan Roese /* 28cb78722SStefan Roese * (C) Copyright 2009 38cb78722SStefan Roese * Marvell Semiconductor <www.marvell.com> 48cb78722SStefan Roese * Written-by: Prafulla Wadaskar <prafulla@marvell.com> 58cb78722SStefan Roese * 68cb78722SStefan Roese * SPDX-License-Identifier: GPL-2.0+ 78cb78722SStefan Roese */ 88cb78722SStefan Roese 9250eea74SStefan Roese #ifndef _MVEBU_CPU_H 10250eea74SStefan Roese #define _MVEBU_CPU_H 118cb78722SStefan Roese 128cb78722SStefan Roese #include <asm/system.h> 138cb78722SStefan Roese 148cb78722SStefan Roese #ifndef __ASSEMBLY__ 158cb78722SStefan Roese 168cb78722SStefan Roese #define MVEBU_REG_PCIE_DEVID (MVEBU_REG_PCIE_BASE + 0x00) 178cb78722SStefan Roese #define MVEBU_REG_PCIE_REVID (MVEBU_REG_PCIE_BASE + 0x08) 188cb78722SStefan Roese 198cb78722SStefan Roese enum memory_bank { 208cb78722SStefan Roese BANK0, 218cb78722SStefan Roese BANK1, 228cb78722SStefan Roese BANK2, 238cb78722SStefan Roese BANK3 248cb78722SStefan Roese }; 258cb78722SStefan Roese 268cb78722SStefan Roese enum cpu_winen { 278cb78722SStefan Roese CPU_WIN_DISABLE, 288cb78722SStefan Roese CPU_WIN_ENABLE 298cb78722SStefan Roese }; 308cb78722SStefan Roese 318cb78722SStefan Roese enum cpu_target { 328cb78722SStefan Roese CPU_TARGET_DRAM = 0x0, 338cb78722SStefan Roese CPU_TARGET_DEVICEBUS_BOOTROM_SPI = 0x1, 348cb78722SStefan Roese CPU_TARGET_ETH23 = 0x3, 358cb78722SStefan Roese CPU_TARGET_PCIE02 = 0x4, 368cb78722SStefan Roese CPU_TARGET_ETH01 = 0x7, 378cb78722SStefan Roese CPU_TARGET_PCIE13 = 0x8, 388cb78722SStefan Roese CPU_TARGET_SASRAM = 0x9, 39*a1b6b0a9SMario Six CPU_TARGET_SATA01 = 0xa, /* A38X */ 408cb78722SStefan Roese CPU_TARGET_NAND = 0xd, 41*a1b6b0a9SMario Six CPU_TARGET_SATA23_DFX = 0xe, /* A38X */ 428cb78722SStefan Roese }; 438cb78722SStefan Roese 448cb78722SStefan Roese enum cpu_attrib { 458cb78722SStefan Roese CPU_ATTR_SASRAM = 0x01, 468cb78722SStefan Roese CPU_ATTR_DRAM_CS0 = 0x0e, 478cb78722SStefan Roese CPU_ATTR_DRAM_CS1 = 0x0d, 488cb78722SStefan Roese CPU_ATTR_DRAM_CS2 = 0x0b, 498cb78722SStefan Roese CPU_ATTR_DRAM_CS3 = 0x07, 508cb78722SStefan Roese CPU_ATTR_NANDFLASH = 0x2f, 518cb78722SStefan Roese CPU_ATTR_SPIFLASH = 0x1e, 5221324ddbSStefan Roese CPU_ATTR_SPI0_CS0 = 0x1e, 5321324ddbSStefan Roese CPU_ATTR_SPI0_CS1 = 0x5e, 5421324ddbSStefan Roese CPU_ATTR_SPI1_CS2 = 0x9a, 558cb78722SStefan Roese CPU_ATTR_BOOTROM = 0x1d, 568cb78722SStefan Roese CPU_ATTR_PCIE_IO = 0xe0, 578cb78722SStefan Roese CPU_ATTR_PCIE_MEM = 0xe8, 588cb78722SStefan Roese CPU_ATTR_DEV_CS0 = 0x3e, 598cb78722SStefan Roese CPU_ATTR_DEV_CS1 = 0x3d, 608cb78722SStefan Roese CPU_ATTR_DEV_CS2 = 0x3b, 618cb78722SStefan Roese CPU_ATTR_DEV_CS3 = 0x37, 628cb78722SStefan Roese }; 638cb78722SStefan Roese 649c6d3b7bSStefan Roese enum { 659c6d3b7bSStefan Roese MVEBU_SOC_AXP, 6609e89ab4SStefan Roese MVEBU_SOC_A375, 679c6d3b7bSStefan Roese MVEBU_SOC_A38X, 689c6d3b7bSStefan Roese MVEBU_SOC_UNKNOWN, 699c6d3b7bSStefan Roese }; 709c6d3b7bSStefan Roese 718cb78722SStefan Roese /* 728cb78722SStefan Roese * Default Device Address MAP BAR values 738cb78722SStefan Roese */ 748ed20d65SStefan Roese #define MBUS_PCI_MEM_BASE 0xE8000000 758ed20d65SStefan Roese #define MBUS_PCI_MEM_SIZE (128 << 20) 768ed20d65SStefan Roese #define MBUS_PCI_IO_BASE 0xF1100000 778ed20d65SStefan Roese #define MBUS_PCI_IO_SIZE (64 << 10) 788ed20d65SStefan Roese #define MBUS_SPI_BASE 0xF4000000 798ed20d65SStefan Roese #define MBUS_SPI_SIZE (8 << 20) 808ed20d65SStefan Roese #define MBUS_BOOTROM_BASE 0xF8000000 818ed20d65SStefan Roese #define MBUS_BOOTROM_SIZE (8 << 20) 828cb78722SStefan Roese 838cb78722SStefan Roese struct mbus_win { 848cb78722SStefan Roese u32 base; 858cb78722SStefan Roese u32 size; 868cb78722SStefan Roese u8 target; 878cb78722SStefan Roese u8 attr; 888cb78722SStefan Roese }; 898cb78722SStefan Roese 908cb78722SStefan Roese /* 918cb78722SStefan Roese * System registers 928cb78722SStefan Roese * Ref: Datasheet sec:A.28 938cb78722SStefan Roese */ 948cb78722SStefan Roese struct mvebu_system_registers { 9509e89ab4SStefan Roese #if defined(CONFIG_ARMADA_375) 9609e89ab4SStefan Roese u8 pad1[0x54]; 9709e89ab4SStefan Roese #else 988cb78722SStefan Roese u8 pad1[0x60]; 9909e89ab4SStefan Roese #endif 1008cb78722SStefan Roese u32 rstoutn_mask; /* 0x60 */ 1018cb78722SStefan Roese u32 sys_soft_rst; /* 0x64 */ 1028cb78722SStefan Roese }; 1038cb78722SStefan Roese 1048cb78722SStefan Roese /* 1058cb78722SStefan Roese * GPIO Registers 1068cb78722SStefan Roese * Ref: Datasheet sec:A.19 1078cb78722SStefan Roese */ 1088cb78722SStefan Roese struct kwgpio_registers { 1098cb78722SStefan Roese u32 dout; 1108cb78722SStefan Roese u32 oe; 1118cb78722SStefan Roese u32 blink_en; 1128cb78722SStefan Roese u32 din_pol; 1138cb78722SStefan Roese u32 din; 1148cb78722SStefan Roese u32 irq_cause; 1158cb78722SStefan Roese u32 irq_mask; 1168cb78722SStefan Roese u32 irq_level; 1178cb78722SStefan Roese }; 1188cb78722SStefan Roese 119d718bf2cSStefan Roese struct sar_freq_modes { 120d718bf2cSStefan Roese u8 val; 121d718bf2cSStefan Roese u8 ffc; /* Fabric Frequency Configuration */ 122d718bf2cSStefan Roese u32 p_clk; 123d718bf2cSStefan Roese u32 nb_clk; 124d718bf2cSStefan Roese u32 d_clk; 125d718bf2cSStefan Roese }; 126d718bf2cSStefan Roese 1278cb78722SStefan Roese /* Needed for dynamic (board-specific) mbus configuration */ 1288cb78722SStefan Roese extern struct mvebu_mbus_state mbus_state; 1298cb78722SStefan Roese 1308cb78722SStefan Roese /* 1318cb78722SStefan Roese * functions 1328cb78722SStefan Roese */ 1338cb78722SStefan Roese unsigned int mvebu_sdram_bar(enum memory_bank bank); 1348cb78722SStefan Roese unsigned int mvebu_sdram_bs(enum memory_bank bank); 1358cb78722SStefan Roese void mvebu_sdram_size_adjust(enum memory_bank bank); 1368cb78722SStefan Roese int mvebu_mbus_probe(struct mbus_win windows[], int count); 1379c6d3b7bSStefan Roese int mvebu_soc_family(void); 1382a0b7dc3SStefan Roese u32 mvebu_get_nand_clock(void); 1398cb78722SStefan Roese 140944c7a31SStefan Roese void return_to_bootrom(void); 141944c7a31SStefan Roese 1427f1adcd7SStefan Roese int mv_sdh_init(unsigned long regbase, u32 max_clk, u32 min_clk, u32 quirks); 1437f1adcd7SStefan Roese 144d718bf2cSStefan Roese void get_sar_freq(struct sar_freq_modes *sar_freq); 145d718bf2cSStefan Roese 1468cb78722SStefan Roese /* 1478cb78722SStefan Roese * Highspeed SERDES PHY config init, ported from bin_hdr 1488cb78722SStefan Roese * to mainline U-Boot 1498cb78722SStefan Roese */ 1508cb78722SStefan Roese int serdes_phy_config(void); 1518cb78722SStefan Roese 1528cb78722SStefan Roese /* 1538cb78722SStefan Roese * DDR3 init / training code ported from Marvell bin_hdr. Now 1548cb78722SStefan Roese * available in mainline U-Boot in: 155ff9112dfSStefan Roese * drivers/ddr/marvell 1568cb78722SStefan Roese */ 1578cb78722SStefan Roese int ddr3_init(void); 158913d1be2SStefan Roese 159913d1be2SStefan Roese struct mvebu_lcd_info { 160913d1be2SStefan Roese u32 fb_base; 161913d1be2SStefan Roese int x_res; 162913d1be2SStefan Roese int y_res; 163913d1be2SStefan Roese int x_fp; /* frontporch */ 164913d1be2SStefan Roese int y_fp; 165913d1be2SStefan Roese int x_bp; /* backporch */ 166913d1be2SStefan Roese int y_bp; 167913d1be2SStefan Roese }; 168913d1be2SStefan Roese 169913d1be2SStefan Roese int mvebu_lcd_register_init(struct mvebu_lcd_info *lcd_info); 170913d1be2SStefan Roese 171f61aefc1SStefan Roese /* 172f61aefc1SStefan Roese * get_ref_clk 173f61aefc1SStefan Roese * 174f61aefc1SStefan Roese * return: reference clock in MHz (25 or 40) 175f61aefc1SStefan Roese */ 176f61aefc1SStefan Roese u32 get_ref_clk(void); 177f61aefc1SStefan Roese 1788cb78722SStefan Roese #endif /* __ASSEMBLY__ */ 179250eea74SStefan Roese #endif /* _MVEBU_CPU_H */ 180