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/rk3399_rockchip-uboot/arch/powerpc/cpu/mpc85xx/
H A Dfsl_corenet_serdes.c96 int serdes_get_lane_idx(int lane) in serdes_get_lane_idx() argument
98 return lanes[lane].idx; in serdes_get_lane_idx()
101 int serdes_get_bank_by_lane(int lane) in serdes_get_bank_by_lane() argument
103 return lanes[lane].bank; in serdes_get_bank_by_lane()
106 int serdes_lane_enabled(int lane) in serdes_lane_enabled() argument
111 int bank = lanes[lane].bank; in serdes_lane_enabled()
112 int word = lanes[lane].lpd / 32; in serdes_lane_enabled()
113 int bit = lanes[lane].lpd % 32; in serdes_lane_enabled()
125 return !(srds_lpd_b[bank] & (8 >> (lane - (6 + 4 * bank)))); in serdes_lane_enabled()
190 int lane; in serdes_get_bank_by_device() local
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H A Dp1010_serdes.c58 int lane; in fsl_serdes_init() local
70 for (lane = 0; lane < SRDS1_MAX_LANES; lane++) { in fsl_serdes_init()
71 enum srds_prtcl lane_prtcl = serdes1_cfg_tbl[srds_cfg][lane]; in fsl_serdes_init()
83 for (lane = 0; lane < SRDS2_MAX_LANES; lane++) { in fsl_serdes_init()
84 enum srds_prtcl lane_prtcl = serdes2_cfg_tbl[srds_cfg][lane]; in fsl_serdes_init()
H A Dmpc8544_serdes.c59 int lane; in fsl_serdes_init() local
71 for (lane = 0; lane < SRDS1_MAX_LANES; lane++) { in fsl_serdes_init()
72 enum srds_prtcl lane_prtcl = serdes1_cfg_tbl[srds_cfg][lane]; in fsl_serdes_init()
84 for (lane = 0; lane < SRDS2_MAX_LANES; lane++) { in fsl_serdes_init()
85 enum srds_prtcl lane_prtcl = serdes2_cfg_tbl[srds_cfg][lane]; in fsl_serdes_init()
H A Dfsl_corenet_serdes.h19 int serdes_get_lane_idx(int lane);
20 int serdes_get_bank_by_lane(int lane);
21 int serdes_lane_enabled(int lane);
22 enum srds_prtcl serdes_get_prtcl(int cfg, int lane);
H A Dp1022_serdes.c97 int lane; in fsl_serdes_init() local
109 for (lane = 0; lane < SRDS1_MAX_LANES; lane++) { in fsl_serdes_init()
110 enum srds_prtcl lane_prtcl = serdes1_cfg_tbl[srds_cfg][lane]; in fsl_serdes_init()
122 for (lane = 0; lane < SRDS2_MAX_LANES; lane++) { in fsl_serdes_init()
123 enum srds_prtcl lane_prtcl = serdes2_cfg_tbl[srds_cfg][lane]; in fsl_serdes_init()
H A Dp1023_serdes.c42 int lane; in fsl_serdes_init() local
53 for (lane = 0; lane < SRDS1_MAX_LANES; lane++) { in fsl_serdes_init()
54 enum srds_prtcl lane_prtcl = serdes1_cfg_tbl[srds_cfg][lane]; in fsl_serdes_init()
H A Dc29x_serdes.c48 int lane; in fsl_serdes_init() local
64 for (lane = 0; lane < SRDS1_MAX_LANES; lane++) { in fsl_serdes_init()
65 enum srds_prtcl lane_prtcl = ptr->lanes[lane]; in fsl_serdes_init()
H A Dmpc8548_serdes.c39 int lane; in fsl_serdes_init() local
51 for (lane = 0; lane < SRDS1_MAX_LANES; lane++) { in fsl_serdes_init()
52 enum srds_prtcl lane_prtcl = serdes1_cfg_tbl[srds1_cfg][lane]; in fsl_serdes_init()
H A Dmpc8568_serdes.c39 int lane; in fsl_serdes_init() local
51 for (lane = 0; lane < SRDS1_MAX_LANES; lane++) { in fsl_serdes_init()
52 enum srds_prtcl lane_prtcl = serdes1_cfg_tbl[srds_cfg][lane]; in fsl_serdes_init()
H A Dp2020_serdes.c47 int lane; in fsl_serdes_init() local
59 for (lane = 0; lane < SRDS1_MAX_LANES; lane++) { in fsl_serdes_init()
60 enum srds_prtcl lane_prtcl = serdes1_cfg_tbl[srds_cfg][lane]; in fsl_serdes_init()
/rk3399_rockchip-uboot/drivers/phy/marvell/
H A Dcomphy_mux.c24 int lane, opt, valid; in comphy_mux_check_config() local
28 for (lane = 0; lane < comphy_max_lanes; in comphy_mux_check_config()
29 lane++, comphy_map_data++, mux_data++) { in comphy_mux_check_config()
44 lane, comphy_map_data->type); in comphy_mux_check_config()
45 debug("set lane %d as type %d\n", lane, in comphy_mux_check_config()
50 lane, comphy_map_data->type); in comphy_mux_check_config()
58 u32 type, int lane) in comphy_mux_get_mux_value() argument
84 u32 lane, value, offset, mask; in comphy_mux_reg_write() local
88 for (lane = 0; lane < comphy_max_lanes; in comphy_mux_reg_write()
89 lane++, comphy_map_data++, mux_data++) { in comphy_mux_reg_write()
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H A Dcomphy_core.c89 u32 lane; in comphy_print() local
91 for (lane = 0; lane < chip_cfg->comphy_lanes_count; in comphy_print()
92 lane++, comphy_map_data++) { in comphy_print()
94 printf("Comphy-%d: %-13s\n", lane, in comphy_print()
97 printf("Comphy-%d: %-13s %-10s\n", lane, in comphy_print()
111 int lane; in comphy_probe() local
153 lane = 0; in comphy_probe()
159 comphy_map_data[lane].speed = fdtdec_get_int( in comphy_probe()
161 comphy_map_data[lane].type = fdtdec_get_int( in comphy_probe()
163 comphy_map_data[lane].invert = fdtdec_get_int( in comphy_probe()
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H A Dcomphy_a3700.c610 static void comphy_sgmii_phy_init(u32 lane, u32 speed) in comphy_sgmii_phy_init() argument
635 phy_write16(lane, addr, val, 0xFFFF); in comphy_sgmii_phy_init()
644 static int comphy_sgmii_power_up(u32 lane, u32 speed, u32 invert) in comphy_sgmii_power_up() argument
653 reg_set((void __iomem *)COMPHY_SEL_ADDR, 0, rf_compy_select(lane)); in comphy_sgmii_power_up()
661 reg_set((void __iomem *)COMPHY_PHY_CFG1_ADDR(lane), in comphy_sgmii_power_up()
669 reg_set((void __iomem *)COMPHY_PHY_CFG1_ADDR(lane), in comphy_sgmii_power_up()
677 reg_set((void __iomem *)COMPHY_PHY_CFG1_ADDR(lane), in comphy_sgmii_power_up()
683 reg_set((void __iomem *)COMPHY_PHY_CFG1_ADDR(lane), in comphy_sgmii_power_up()
699 phy_write16(lane, PHY_PWR_PLL_CTRL_ADDR, in comphy_sgmii_power_up()
706 phy_write16(lane, PHY_MISC_REG0_ADDR, 0, rb_ref_clk_sel); in comphy_sgmii_power_up()
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H A Dcomphy_cp110.c20 #define SD_ADDR(base, lane) (base + 0x1000 * lane) argument
21 #define HPIPE_ADDR(base, lane) (SD_ADDR(base, lane) + 0x800) argument
22 #define COMPHY_ADDR(base, lane) (base + 0x28 * lane) argument
87 static int comphy_pcie_power_up(u32 lane, u32 pcie_width, bool clk_src, in comphy_pcie_power_up() argument
92 void __iomem *hpipe_addr = HPIPE_ADDR(hpipe_base, lane); in comphy_pcie_power_up()
93 void __iomem *comphy_addr = COMPHY_ADDR(comphy_base, lane); in comphy_pcie_power_up()
113 if (lane == 0) { in comphy_pcie_power_up()
130 if (pcie_clk && clk_src && (lane == 5)) { in comphy_pcie_power_up()
192 if (lane == 0) { in comphy_pcie_power_up()
195 } else if (lane == (pcie_width - 1)) { in comphy_pcie_power_up()
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/rk3399_rockchip-uboot/board/highbank/
H A Dahci.c82 static void cphy_spread_spectrum_override(u8 phy, u8 lane, u32 val) in cphy_spread_spectrum_override() argument
85 tmp = combo_phy_read(phy, CPHY_RX_INPUT_STS + lane * SPHY_LANE); in cphy_spread_spectrum_override()
87 combo_phy_write(phy, CPHY_RX_INPUT_OVERRIDE + lane * SPHY_LANE, tmp); in cphy_spread_spectrum_override()
90 combo_phy_write(phy, CPHY_RX_INPUT_OVERRIDE + lane * SPHY_LANE, tmp); in cphy_spread_spectrum_override()
94 combo_phy_write(phy, CPHY_RX_INPUT_OVERRIDE + lane * SPHY_LANE, tmp); in cphy_spread_spectrum_override()
97 static void cphy_tx_attenuation_override(u8 phy, u8 lane) in cphy_tx_attenuation_override() argument
103 shift = ((phy == 5) ? 4 : lane) * 4; in cphy_tx_attenuation_override()
110 tmp = combo_phy_read(phy, CPHY_TX_INPUT_STS + lane * SPHY_LANE); in cphy_tx_attenuation_override()
112 combo_phy_write(phy, CPHY_TX_INPUT_OVERRIDE + lane * SPHY_LANE, tmp); in cphy_tx_attenuation_override()
115 combo_phy_write(phy, CPHY_TX_INPUT_OVERRIDE + lane * SPHY_LANE, tmp); in cphy_tx_attenuation_override()
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/rk3399_rockchip-uboot/board/freescale/p2041rdb/
H A Deth.c93 int lane = serdes_get_first_lane(SGMII_FM1_DTSEC1 + port); in board_ft_fman_fixup_port() local
95 if (lane < 0) in board_ft_fman_fixup_port()
97 slot = lane_to_slot[lane]; in board_ft_fman_fixup_port()
113 int lane = serdes_get_first_lane(XAUI_FM1); in board_ft_fman_fixup_port() local
114 if (lane >= 0) { in board_ft_fman_fixup_port()
116 sprintf(phy, "phy_xgmii_%u", lane_to_slot[lane]); in board_ft_fman_fixup_port()
129 int lane; in board_eth_init() local
164 lane = serdes_get_first_lane(SGMII_FM1_DTSEC1 + idx); in board_eth_init()
165 if (lane < 0) in board_eth_init()
167 slot = lane_to_slot[lane]; in board_eth_init()
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/rk3399_rockchip-uboot/arch/powerpc/cpu/mpc86xx/
H A Dmpc8610_serdes.c55 int lane; in fsl_serdes_init() local
67 for (lane = 0; lane < SRDS1_MAX_LANES; lane++) { in fsl_serdes_init()
68 enum srds_prtcl lane_prtcl = serdes1_cfg_tbl[srds_cfg][lane]; in fsl_serdes_init()
80 for (lane = 0; lane < SRDS2_MAX_LANES; lane++) { in fsl_serdes_init()
81 enum srds_prtcl lane_prtcl = serdes2_cfg_tbl[srds_cfg][lane]; in fsl_serdes_init()
H A Dmpc8641_serdes.c64 int lane; in fsl_serdes_init() local
76 for (lane = 0; lane < SRDS1_MAX_LANES; lane++) { in fsl_serdes_init()
77 enum srds_prtcl lane_prtcl = serdes1_cfg_tbl[srds_cfg][lane]; in fsl_serdes_init()
89 for (lane = 0; lane < SRDS2_MAX_LANES; lane++) { in fsl_serdes_init()
90 enum srds_prtcl lane_prtcl = serdes2_cfg_tbl[srds_cfg][lane]; in fsl_serdes_init()
/rk3399_rockchip-uboot/board/freescale/t1040qds/
H A Deth.c300 int lane = serdes_get_first_lane(FSL_SRDS_1, SGMII_FM1_DTSEC1 in board_ft_fman_fixup_port() local
303 if (lane < 0) in board_ft_fman_fixup_port()
305 slot = lane_to_slot[lane]; in board_ft_fman_fixup_port()
318 int i, lane, idx; in fdt_fixup_board_enet() local
324 lane = serdes_get_first_lane(FSL_SRDS_1, in fdt_fixup_board_enet()
326 if (lane < 0) in fdt_fixup_board_enet()
370 int lane, idx, slot; in t1040_handle_phy_interface_sgmii() local
372 lane = serdes_get_first_lane(FSL_SRDS_1, in t1040_handle_phy_interface_sgmii()
375 if (lane < 0) in t1040_handle_phy_interface_sgmii()
377 slot = lane_to_slot[lane]; in t1040_handle_phy_interface_sgmii()
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/rk3399_rockchip-uboot/board/freescale/corenet_ds/
H A Deth_superhydra.c218 int lane, slot, phy; in board_ft_fman_fixup_port() local
225 lane = serdes_get_first_lane(device); in board_ft_fman_fixup_port()
226 slot = lane_to_slot[lane]; in board_ft_fman_fixup_port()
300 int lane, slot; in fdt_fixup_board_enet() local
307 lane = serdes_get_first_lane(SGMII_FM1_DTSEC1 + idx); in fdt_fixup_board_enet()
308 if (lane >= 0) { in fdt_fixup_board_enet()
311 slot = lane_to_slot[lane]; in fdt_fixup_board_enet()
327 lane = serdes_get_first_lane(XAUI_FM1); in fdt_fixup_board_enet()
328 if (lane >= 0) { in fdt_fixup_board_enet()
331 slot = lane_to_slot[lane]; in fdt_fixup_board_enet()
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H A Deth_hydra.c246 int lane = serdes_get_first_lane(XAUI_FM1); in board_ft_fman_fixup_port() local
247 if (lane >= 0) { in board_ft_fman_fixup_port()
249 sprintf(phy, "phy_xgmii_%u", lane_to_slot[lane]); in board_ft_fman_fixup_port()
337 int lane; in fdt_fixup_board_enet() local
344 lane = serdes_get_first_lane(SGMII_FM1_DTSEC1 + idx); in fdt_fixup_board_enet()
345 if (lane >= 0) { in fdt_fixup_board_enet()
360 lane = serdes_get_first_lane(XAUI_FM1); in fdt_fixup_board_enet()
361 if (lane >= 0) in fdt_fixup_board_enet()
372 int lane; in board_eth_init() local
417 lane = serdes_get_first_lane(SGMII_FM1_DTSEC1 + idx); in board_eth_init()
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/rk3399_rockchip-uboot/arch/arm/mach-tegra/
H A Dxusb-padctl-common.c130 const struct tegra_xusb_padctl_lane *lane, in tegra_xusb_padctl_lane_find_function() argument
140 for (i = 0; i < lane->num_funcs; i++) in tegra_xusb_padctl_lane_find_function()
141 if (lane->funcs[i] == func) in tegra_xusb_padctl_lane_find_function()
154 const struct tegra_xusb_padctl_lane *lane; in tegra_xusb_padctl_group_apply() local
158 lane = tegra_xusb_padctl_find_lane(padctl, group->pins[i]); in tegra_xusb_padctl_group_apply()
159 if (!lane) { in tegra_xusb_padctl_group_apply()
164 func = tegra_xusb_padctl_lane_find_function(padctl, lane, in tegra_xusb_padctl_group_apply()
168 group->func, lane->name, func); in tegra_xusb_padctl_group_apply()
172 value = padctl_readl(padctl, lane->offset); in tegra_xusb_padctl_group_apply()
175 value &= ~(lane->mask << lane->shift); in tegra_xusb_padctl_group_apply()
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/rk3399_rockchip-uboot/drivers/soc/keystone/
H A Dkeystone_serdes.c47 struct serdes_cfg lane[SERDES_LANE_CFG_NUM]; member
89 .lane = {
118 u32 size, u32 lane) in ks2_serdes_lane_config() argument
123 ks2_serdes_rmw(base + cfg_lane[i].ofs + SERDES_LANE_REGS(lane), in ks2_serdes_lane_config()
135 ks2_serdes_lane_config(base, cfg->lane, SERDES_LANE_CFG_NUM, i); in ks2_serdes_init_cfg()
161 static void ks2_serdes_lane_reset(u32 base, u32 reset, u32 lane) in ks2_serdes_lane_reset() argument
164 ks2_serdes_rmw(base + SERDES_LANE_REG_028(lane), in ks2_serdes_lane_reset()
167 ks2_serdes_rmw(base + SERDES_LANE_REG_028(lane), in ks2_serdes_lane_reset()
172 struct ks2_serdes *serdes, u32 lane) in ks2_serdes_lane_enable() argument
175 ks2_serdes_lane_reset(base, 0, lane); in ks2_serdes_lane_enable()
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/rk3399_rockchip-uboot/drivers/phy/
H A Dphy-rockchip-samsung-hdptx.c323 #define LANE_REG(lane, offset) (0x400 * (lane) + (offset)) argument
709 u8 lane) in rockchip_hdptx_phy_set_voltage() argument
716 ctrl = &tx_drv_ctrl_rbr_dp_mode[dp->voltage[lane]][dp->pre[lane]]; in rockchip_hdptx_phy_set_voltage()
718 ctrl = &tx_drv_ctrl_rbr[dp->voltage[lane]][dp->pre[lane]]; in rockchip_hdptx_phy_set_voltage()
719 regmap_update_bits(hdptx->regmap, LANE_REG(lane, 0x0c44), in rockchip_hdptx_phy_set_voltage()
722 regmap_update_bits(hdptx->regmap, LANE_REG(lane, 0x0c28), in rockchip_hdptx_phy_set_voltage()
725 regmap_update_bits(hdptx->regmap, LANE_REG(lane, 0x0c30), in rockchip_hdptx_phy_set_voltage()
731 ctrl = &tx_drv_ctrl_r216_r243[dp->voltage[lane]][dp->pre[lane]]; in rockchip_hdptx_phy_set_voltage()
732 regmap_update_bits(hdptx->regmap, LANE_REG(lane, 0x0c44), in rockchip_hdptx_phy_set_voltage()
735 regmap_update_bits(hdptx->regmap, LANE_REG(lane, 0x0c2c), in rockchip_hdptx_phy_set_voltage()
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/rk3399_rockchip-uboot/drivers/video/drm/
H A Ddrm_dp_helper.c43 int lane) in dp_get_lane_status() argument
45 int i = DP_LANE0_1_STATUS + (lane >> 1); in dp_get_lane_status()
46 int s = (lane & 1) * 4; in dp_get_lane_status()
57 int lane; in drm_dp_channel_eq_ok() local
63 for (lane = 0; lane < lane_count; lane++) { in drm_dp_channel_eq_ok()
64 lane_status = dp_get_lane_status(link_status, lane); in drm_dp_channel_eq_ok()
74 int lane; in drm_dp_clock_recovery_ok() local
77 for (lane = 0; lane < lane_count; lane++) { in drm_dp_clock_recovery_ok()
78 lane_status = dp_get_lane_status(link_status, lane); in drm_dp_clock_recovery_ok()
86 int lane) in drm_dp_get_adjust_request_voltage() argument
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