xref: /rk3399_rockchip-uboot/arch/powerpc/cpu/mpc86xx/mpc8610_serdes.c (revision cbe7706ab8aab06c18edaa9b120371f9c8012728)
1af042474SKumar Gala /*
2af042474SKumar Gala  * Copyright 2010 Freescale Semiconductor, Inc.
3af042474SKumar Gala  *
41a459660SWolfgang Denk  * SPDX-License-Identifier:	GPL-2.0+
5af042474SKumar Gala  */
6af042474SKumar Gala 
7af042474SKumar Gala #include <config.h>
8af042474SKumar Gala #include <common.h>
9af042474SKumar Gala #include <asm/io.h>
10af042474SKumar Gala #include <asm/immap_86xx.h>
11af042474SKumar Gala #include <asm/fsl_serdes.h>
12af042474SKumar Gala 
13af042474SKumar Gala #define SRDS1_MAX_LANES		4
14af042474SKumar Gala #define SRDS2_MAX_LANES		4
15af042474SKumar Gala 
16af042474SKumar Gala static u32 serdes1_prtcl_map, serdes2_prtcl_map;
17af042474SKumar Gala 
18af042474SKumar Gala static u8 serdes1_cfg_tbl[][SRDS1_MAX_LANES] = {
19af042474SKumar Gala 	[0x1] = {PCIE1, PCIE1, PCIE1, PCIE1},
20af042474SKumar Gala 	[0x4] = {PCIE1, PCIE1, PCIE1, PCIE1},
21af042474SKumar Gala 	[0x7] = {NONE, NONE, NONE, NONE},
22af042474SKumar Gala };
23af042474SKumar Gala 
24af042474SKumar Gala static u8 serdes2_cfg_tbl[][SRDS2_MAX_LANES] = {
25af042474SKumar Gala 	[0x0] = {PCIE2, PCIE2, PCIE2, PCIE2},
26af042474SKumar Gala 	[0x4] = {PCIE2, PCIE2, PCIE2, PCIE2},
27af042474SKumar Gala 	[0x7] = {NONE, NONE, NONE, NONE},
28af042474SKumar Gala };
29af042474SKumar Gala 
is_serdes_configured(enum srds_prtcl device)30af042474SKumar Gala int is_serdes_configured(enum srds_prtcl device)
31af042474SKumar Gala {
32*71fe2225SHou Zhiqiang 	int ret;
33*71fe2225SHou Zhiqiang 
34*71fe2225SHou Zhiqiang 	if (!(serdes1_prtcl_map & (1 << NONE)))
35*71fe2225SHou Zhiqiang 		fsl_serdes_init();
36*71fe2225SHou Zhiqiang 
37*71fe2225SHou Zhiqiang 	ret = (1 << device) & serdes1_prtcl_map;
38af042474SKumar Gala 
39af042474SKumar Gala 	if (ret)
40af042474SKumar Gala 		return ret;
41af042474SKumar Gala 
42*71fe2225SHou Zhiqiang 	if (!(serdes2_prtcl_map & (1 << NONE)))
43*71fe2225SHou Zhiqiang 		fsl_serdes_init();
44*71fe2225SHou Zhiqiang 
45af042474SKumar Gala 	return (1 << device) & serdes2_prtcl_map;
46af042474SKumar Gala }
47af042474SKumar Gala 
fsl_serdes_init(void)48af042474SKumar Gala void fsl_serdes_init(void)
49af042474SKumar Gala {
50af042474SKumar Gala 	immap_t *immap = (immap_t *) CONFIG_SYS_CCSRBAR;
51af042474SKumar Gala 	ccsr_gur_t *gur = &immap->im_gur;
52af042474SKumar Gala 	u32 pordevsr = in_be32(&gur->pordevsr);
53af042474SKumar Gala 	u32 srds_cfg = (pordevsr & MPC8610_PORDEVSR_IO_SEL) >>
54af042474SKumar Gala 				MPC8610_PORDEVSR_IO_SEL_SHIFT;
55af042474SKumar Gala 	int lane;
56af042474SKumar Gala 
57*71fe2225SHou Zhiqiang 	if (serdes1_prtcl_map & (1 << NONE) &&
58*71fe2225SHou Zhiqiang 	    serdes2_prtcl_map & (1 << NONE))
59*71fe2225SHou Zhiqiang 		return;
60*71fe2225SHou Zhiqiang 
61af042474SKumar Gala 	debug("PORDEVSR[IO_SEL_SRDS] = %x\n", srds_cfg);
62af042474SKumar Gala 
63e51e47d3SAxel Lin 	if (srds_cfg >= ARRAY_SIZE(serdes1_cfg_tbl)) {
64af042474SKumar Gala 		printf("Invalid PORDEVSR[IO_SEL_SRDS] = %d\n", srds_cfg);
65af042474SKumar Gala 		return;
66af042474SKumar Gala 	}
67af042474SKumar Gala 	for (lane = 0; lane < SRDS1_MAX_LANES; lane++) {
68af042474SKumar Gala 		enum srds_prtcl lane_prtcl = serdes1_cfg_tbl[srds_cfg][lane];
69af042474SKumar Gala 		serdes1_prtcl_map |= (1 << lane_prtcl);
70af042474SKumar Gala 	}
71af042474SKumar Gala 
72*71fe2225SHou Zhiqiang 	/* Set the first bit to indicate serdes has been initialized */
73*71fe2225SHou Zhiqiang 	serdes1_prtcl_map |= (1 << NONE);
74*71fe2225SHou Zhiqiang 
75e51e47d3SAxel Lin 	if (srds_cfg >= ARRAY_SIZE(serdes2_cfg_tbl)) {
76af042474SKumar Gala 		printf("Invalid PORDEVSR[IO_SEL_SRDS] = %d\n", srds_cfg);
77af042474SKumar Gala 		return;
78af042474SKumar Gala 	}
79af042474SKumar Gala 
80af042474SKumar Gala 	for (lane = 0; lane < SRDS2_MAX_LANES; lane++) {
81af042474SKumar Gala 		enum srds_prtcl lane_prtcl = serdes2_cfg_tbl[srds_cfg][lane];
82af042474SKumar Gala 		serdes2_prtcl_map |= (1 << lane_prtcl);
83af042474SKumar Gala 	}
84*71fe2225SHou Zhiqiang 
85*71fe2225SHou Zhiqiang 	/* Set the first bit to indicate serdes has been initialized */
86*71fe2225SHou Zhiqiang 	serdes2_prtcl_map |= (1 << NONE);
87af042474SKumar Gala }
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